coreboot-gerrit January 2017

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Patch set updated for coreboot: mb/asus/p5gc-mx: Use common/gpio.h
by Arthur Heymans 06 Jan '17

06 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18047 -gerrit commit 8ad57a1294b3bb4113a91cd9b18b4172f5f38242 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jan 6 20:01:57 2017 +0100 mb/asus/p5gc-mx: Use common/gpio.h Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to set up GPIOs", which was not rebased on addition of this board. Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/Makefile.inc | 2 + src/mainboard/asus/p5gc-mx/gpio.c | 129 ++++++++++++++++++++++++++++++++ src/mainboard/asus/p5gc-mx/romstage.c | 17 ----- 3 files changed, 131 insertions(+), 17 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc index f9621db..9aac7e2 100644 --- a/src/mainboard/asus/p5gc-mx/Makefile.inc +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += cstates.c +romstage-y += gpio.c + diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c new file mode 100644 index 0000000..55c2b3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index f0c48a3..efeaaec 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -44,23 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void setup_ich7_gpios(void) -{ - /* TODO: This is highly board specific and should be moved */ - printk(BIOS_DEBUG, " GPIOS..."); - /* General Registers */ - outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - /* * BSEL0 is connected with GPIO32 * BSEL1 is connected with GPIO33 with inversed logic

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New patch to review for coreboot: mb/asus/p5gc-mx: common/gpio.h
by Arthur Heymans 06 Jan '17

06 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18047 -gerrit commit d0310dc6f720631d84150acbead1469f45582d11 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jan 6 20:01:57 2017 +0100 mb/asus/p5gc-mx: common/gpio.h Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to set up GPIOs", which was not rebased on addition of this board. Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/asus/p5gc-mx/Makefile.inc | 2 + src/mainboard/asus/p5gc-mx/gpio.c | 129 ++++++++++++++++++++++++++++++++ src/mainboard/asus/p5gc-mx/romstage.c | 17 ----- 3 files changed, 131 insertions(+), 17 deletions(-) diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc index f9621db..9aac7e2 100644 --- a/src/mainboard/asus/p5gc-mx/Makefile.inc +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -1 +1,3 @@ ramstage-y += cstates.c +romstage-y += gpio.c + diff --git a/src/mainboard/asus/p5gc-mx/gpio.c b/src/mainboard/asus/p5gc-mx/gpio.c new file mode 100644 index 0000000..55c2b3f --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/gpio.c @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_NATIVE, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index f0c48a3..efeaaec 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -44,23 +44,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void setup_ich7_gpios(void) -{ - /* TODO: This is highly board specific and should be moved */ - printk(BIOS_DEBUG, " GPIOS..."); - /* General Registers */ - outl(0x1f3dffc1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8f7c2, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xe2febb7e, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00006000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00030033, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ -} - /* * BSEL0 is connected with GPIO32 * BSEL1 is connected with GPIO33 with inversed logic

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Patch set updated for coreboot: chromeos: Implement locating and decoding wifi sar data from VPD
by Robbie Zhang 06 Jan '17

06 Jan '17

Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17958 -gerrit commit fdb7c481cc0bf2b422cd98fe080eefc53334a6a2 Author: Robbie Zhang <robbie.zhang(a)intel.com> Date: Fri Dec 23 11:43:07 2016 -0800 chromeos: Implement locating and decoding wifi sar data from VPD A VPD entry "wifi_sar" needs to be created which contains a heximal encoded string in length of 40 bytes. get_wifi_sar_limits() function retrieves and decodes the data from the VPD entry, which would later be consumed by platform code. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061 Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/include/sar.h | 34 ++++++++++++++++++ src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/cros_vpd.h | 1 + src/vendorcode/google/chromeos/sar.c | 53 +++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+) diff --git a/src/include/sar.h b/src/include/sar.h new file mode 100644 index 0000000..c1ae1f0 --- /dev/null +++ b/src/include/sar.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SAR_H_ +#define _SAR_H_ + +#include <stdint.h> + +/* Wifi SAR limit table structure */ +struct wifi_sar_limits { + uint8_t sar_limit[4][10]; /* Total 4 SAR limit sets, each has 10 bytes */ +}; + +/* + * Retrieve the SAR limits data from VPD and decode it. + * sar_limits: Pointer to wifi_sar_limits where the resulted data is stored + * + * Returns: 0 on success, -1 on errors (The VPD entry doesn't exist, or the + * VPD entry contais non-heximal value.) + */ +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits); + +#endif /* _SAR_H_ */ diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e84eb3d..878b068 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -25,6 +25,7 @@ ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c +ramstage-$(CONFIG_USE_SAR) += sar.c ifeq ($(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c ramstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index 96ca8af..1fa56a4 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -8,6 +8,7 @@ #define __CROS_VPD_H__ #define CROS_VPD_REGION_NAME "region" +#define CROS_VPD_WIFI_SAR_NAME "wifi_sar" /* * Reads VPD string value by key. diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c new file mode 100644 index 0000000..4ca014e --- /dev/null +++ b/src/vendorcode/google/chromeos/sar.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <sar.h> +#include "cros_vpd.h" + +/* Retrieve the wifi SAR limits data from VPD and decode it */ +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + const char *wifi_sar_limit_key = CROS_VPD_WIFI_SAR_NAME; + /* + * cros_vpd_gets() reads in one less than size characters from the VPD + * with a terminating null byte ('\0') stored as the last character into + * the buffer, thus the increasing by 1 for buffer_size. + */ + const size_t buffer_size = (sizeof(struct wifi_sar_limits) / + sizeof(uint8_t)) * 2 + 1; + char wifi_sar_limit_str[buffer_size]; + + /* Try to read the SAR limit entry from VPD */ + if (!cros_vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, + ARRAY_SIZE(wifi_sar_limit_str))) { + printk(BIOS_ERR, + "Error: Could not locate '%s' in VPD\n", + wifi_sar_limit_key); + return -1; + } + printk(BIOS_DEBUG, "VPD wifi_sar = %s\n", wifi_sar_limit_str); + + /* Decode the heximal encoded string to binary values */ + if (hexstrtobin(wifi_sar_limit_str, sar_limits, + sizeof(struct wifi_sar_limits)) + < sizeof(struct wifi_sar_limits)) { + printk(BIOS_ERR, + "Error: VPD wifi_sar contains non-heximal value!\n"); + return -1; + } + return 0; +}

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Patch merged into coreboot/master: libpayload: usb: handle situation with no free device address
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit b5623dede7569cf74dd865748d17b0e413c03ee2 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 4 22:22:56 2017 +0100 libpayload: usb: handle situation with no free device address Change-Id: I1308bdca90f1a09d980f384ee85552198a39b965 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1260940 Reviewed-on: https://review.coreboot.org/18036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18036 for details. -gerrit

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Patch merged into coreboot/master: libpayload: xhci: plug leak
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit a370ae855627364694c089e9a69a98fc837bfb0f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 4 22:08:10 2017 +0100 libpayload: xhci: plug leak Change-Id: Ia163872846906c6c78144a984a405812f856f626 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1325835 Reviewed-on: https://review.coreboot.org/18035 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18035 for details. -gerrit

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Patch merged into coreboot/master: libpayload: timer: cast cpu_khz to make sure 64bit math is used
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit 61dac130b2319301969ddf2cb471913045cb9378 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Wed Jan 4 21:59:42 2017 +0100 libpayload: timer: cast cpu_khz to make sure 64bit math is used Change-Id: Iaf84de2330b433076a66c22fa72ffb45e957c0dc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1261177 Reviewed-on: https://review.coreboot.org/18034 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18034 for details. -gerrit

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Patch merged into coreboot/master: util/romcc: avoid shifting more than the variable's width
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit 766c3fec2d8cfc8d0d7bcfd94f98bace8d3309e9 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 2 18:47:50 2017 +0100 util/romcc: avoid shifting more than the variable's width That's undefined behavior in C Change-Id: I671ed8abf02e57a7cc993d1a85354e905f51717d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1229557 Reviewed-on: https://review.coreboot.org/18014 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18014 for details. -gerrit

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Patch set updated for coreboot: util/lint: Add check for the signed-off-by line
by Martin Roth 06 Jan '17

06 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17941 -gerrit commit 900b7c8287872a342df95f4bd8f4fa2453a64455 Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 22 10:54:55 2016 -0700 util/lint: Add check for the signed-off-by line Gerrit will let you push a patch without a signed-off-by line, although I believe it can't actually be merged. Instead of catching it either manually, or when the patch is attempting to be merged, catch this in the jenkins builder. Change-Id: I80161befa157266dd4e3209839a06ff398aab6bb Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-020-signed-off-by | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/util/lint/lint-stable-020-signed-off-by b/util/lint/lint-stable-020-signed-off-by new file mode 100755 index 0000000..40b6e9e --- /dev/null +++ b/util/lint/lint-stable-020-signed-off-by @@ -0,0 +1,23 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check for a signed-off-by line on the latest git commit + +# This test is mainly for the jenkins server +if [ -n "$(command -v git)" ] && [ -d .git ]; then + if [ -z "$(git log -n 1 | grep '[[:space:]]\+Signed-off-by: ')" ]; then + echo "No Signed-off-by line in commit message" + fi +fi

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Patch merged into coreboot/master: nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit 6d0c65ebc6c0f1e8b8d012dcfd42512b7d281515 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 5 17:07:33 2017 +0100 nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See https://review.coreboot.org/18044 for details. -gerrit

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Patch merged into coreboot/master: sb/ich7: Use common/gpio.h to set up GPIOs
by gerrit＠coreboot.org 06 Jan '17

06 Jan '17

the following patch was just integrated into master: commit 62902ca45de871aa59657dd8ec1858c301595634 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Nov 29 14:13:43 2016 +0100 sb/ich7: Use common/gpio.h to set up GPIOs This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17639 for details. -gerrit

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coreboot-gerrit January 2017