the following patch was just integrated into master:
commit 40843efe5d6dddff19a0d7c8c5fe84c75448e739
Author: Philipp Deppenwiese <zaolin(a)das-labor.org>
Date: Wed Jan 4 00:30:38 2017 +0100
payloads/external/SeaBIOS: Bump version to 1.10.1
Changes since SeaBIOS 1.9.3
Release 1.10.0:
* Initial support for Trusted Platform Module (TPM) version 2.0
* Several USB XHCI timing fixes on real hardware
* Support for "LSI MPT Fusion" scsi controllers on QEMU
* Support for virtio devices mapped above 4GB
* Several bug fixes and code cleanups
Release 1.10.1:
* Updates for QEMU for reproducible builds
Change-Id: I465700307d72fa44b6900b38b332603ea505ed09
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/18026
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18026 for details.
-gerrit
the following patch was just integrated into master:
commit 49342cd6880b3f2a8e20957d976914cd4ee7b43d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 5 10:07:19 2017 -0600
arch/x86: fix cmos post logging in non romcc bootblock
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.
BUG=chrome-os-partner:61546
Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18043
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18043 for details.
-gerrit
Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17976
-gerrit
commit 58d403111afe64aa02a3486aecc7a102b3996594
Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
Date: Wed Dec 28 18:56:26 2016 +0800
driver/intel/fsp1_1: Fix boot failure for non-verstage case
Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not started at all.
The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_C_ENVIRONMENT_BOOTBLOCK and
CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this
change.
Tested on Skylake Saddle Brook (Fsp 1.1) and Kabelyake Rvp11 (Fsp 2.0),
romstage can be started successfully.
Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
---
src/drivers/intel/fsp1_1/Makefile.inc | 1 -
src/drivers/intel/fsp1_1/romstage_after_verstage.S | 38 ---------------------
src/soc/intel/skylake/romstage/Makefile.inc | 3 ++
.../skylake/romstage/romstage_after_verstage.S | 39 ++++++++++++++++++++++
4 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 4088293..e2f75ee 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -28,7 +28,6 @@ romstage-y += fsp_util.c
romstage-y += hob.c
romstage-y += raminit.c
romstage-y += romstage.c
-romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += stack.c
romstage-y += stage_cache.c
romstage-$(CONFIG_MMA) += mma_core.c
diff --git a/src/drivers/intel/fsp1_1/romstage_after_verstage.S b/src/drivers/intel/fsp1_1/romstage_after_verstage.S
deleted file mode 100644
index 2a3372f..0000000
--- a/src/drivers/intel/fsp1_1/romstage_after_verstage.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
-
-.text
-.global car_stage_entry
-car_stage_entry:
- call romstage_after_verstage
- #include "after_raminit.S"
-
- movb $0x69, %ah
- jmp .Lhlt
-
-.Lhlt:
- xchg %al, %ah
-#if IS_ENABLED(CONFIG_POST_IO)
- outb %al, $CONFIG_POST_IO_PORT
-#else
- post_code(POST_DEAD_CODE)
-#endif
- movl $LHLT_DELAY, %ecx
-.Lhlt_Delay:
- outb %al, $0xED
- loop .Lhlt_Delay
- jmp .Lhlt
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 877712f..3ea0ffa 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -5,5 +5,8 @@ romstage-y += pmc.c
romstage-y += power_state.c
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
+ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y)
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage_after_verstage.S
+endif
romstage-y += spi.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/romstage_after_verstage.S b/src/soc/intel/skylake/romstage/romstage_after_verstage.S
new file mode 100644
index 0000000..74c31d5
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage_after_verstage.S
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* I/O delay between post codes on failure */
+#define LHLT_DELAY 0x50000
+
+.text
+.global car_stage_entry
+car_stage_entry:
+ call romstage_after_verstage
+ #include "src/drivers/intel/fsp1_1/after_raminit.S"
+
+ movb $0x69, %ah
+ jmp .Lhlt
+
+.Lhlt:
+ xchg %al, %ah
+#if IS_ENABLED(CONFIG_POST_IO)
+ outb %al, $CONFIG_POST_IO_PORT
+#else
+ post_code(POST_DEAD_CODE)
+#endif
+ movl $LHLT_DELAY, %ecx
+.Lhlt_Delay:
+ outb %al, $0xED
+ loop .Lhlt_Delay
+ jmp .Lhlt