coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/x4x: Fix raminit on reset path
by Arthur Heymans 21 Jan '17

21 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18009 -gerrit commit 12802cbb3ce5a0c462998acd146044fee4b075a3 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit on reset path Previously the raminit failed on hot reset and to work around this issue it unconditionally did a cold reset. This has the following issues: * it's slow; * when the OS issues a hot reset some disk drives expect their 5V power supply to remain on, which gets cut off by a cold reset, causing data corruption. To fix this some steps in raminit must be ommited on the reset path. This includes searching for receive enable. To achieve this it stores receive enable results in nvram (which is also needed when implementing S3 suspend/resume from S3). Calling a hot reset after raminit "outb(0x6, 0cf9)" works. Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +- src/northbridge/intel/x4x/raminit_ddr2.c | 143 +++++++++++++++++++----- src/northbridge/intel/x4x/x4x.h | 7 +- 4 files changed, 127 insertions(+), 31 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..fac9d35 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,7 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 0f43795..d76fbb2 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -30,6 +30,7 @@ #include <lib.h> #include <arch/stages.h> #include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -130,6 +131,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -149,8 +151,11 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..4de29cf 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,11 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +/* This northbridge can also occur with ICH10 */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/i82801gx.h> +#endif #include "iomap.h" #include "x4x.h" @@ -257,26 +262,25 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; - u8 reset = 0; pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - reset = 1; /* do magic 0xf0 thing. */ u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - } - if (reset) { + printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); + outb(0x6, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); } static void setioclk_ddr2(struct sysinfo *s) @@ -1486,6 +1490,80 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, uneven; + u16 reg16; + u8 values[18]; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + uneven = lane % 2; + values[i] = (MCHBAR8(0x400*ch + 0x560 + (lane*4))) + << (uneven * 4); + if (uneven) + i++; + } + values[i++] = (MCHBAR32(0x400*ch + 0x248) >> 16) & 0xf; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + values[i++] = reg16 & 0xff; + values[i++] = (reg16 >> 8) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + values[i++] = reg16 & 0xff; + values[i++] = (reg16 >> 8) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i, uneven; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[18]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) + values[i] = cmos_read(128 + i); + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + uneven = lane % 2; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = 0x70 + | ((values[i] >> (4 * uneven)) & 0xf); + if (uneven) + i++; + } + reg32 = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) + | ((values[i++] & 0xf) << 16); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg16 = values[i++]; + reg16 |= values[i++] << 8; + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = values[i++]; + reg16 |= values[i++] << 8; + MCHBAR16(0x400*ch + 0x58c) = reg16; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_WARM_RESET) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -1859,23 +1937,25 @@ void raminit_ddr2(struct sysinfo *s) // Reset if required checkreset_ddr2(s); - // Clear self refresh - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + if (s->boot_path != BOOT_PATH_WARM_RESET) { + // Clear self refresh + MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) + | PMSTS_BOTH_SELFREFRESH; - // Clear host clk gate reg - MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; - // Select DDR2 - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; - // Set freq - MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | - (s->selected_timings.mem_clk << 4) | (1 << 10); + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); - // Overwrite freq if chipset rejects it - s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; - if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { - die("Error: DDR is faster than FSB, halt\n"); + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) + die("Error: DDR is faster than FSB, halt\n"); } udelay(250000); @@ -1885,8 +1965,10 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done clk crossing\n"); // DDR2 IO - setioclk_ddr2(s); - printk(BIOS_DEBUG, "Done I/O clk\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + } // Grant to launch launch_ddr2(s); @@ -1900,16 +1982,21 @@ void raminit_ddr2(struct sysinfo *s) dll_ddr2(s); // RCOMP - rcomp_ddr2(s); - printk(BIOS_DEBUG, "RCOMP\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + } // ODT odt_ddr2(s); printk(BIOS_DEBUG, "Done ODT\n"); // RCOMP update - while ((MCHBAR8(0x130) & 1) != 0 ); - printk(BIOS_DEBUG, "Done RCOMP update\n"); + if (s->boot_path != BOOT_PATH_WARM_RESET) { + while ((MCHBAR8(0x130) & 1) != 0) + ; + printk(BIOS_DEBUG, "Done RCOMP update\n"); + } // Set defaults MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; @@ -1989,7 +2076,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..66d765a 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -87,8 +87,8 @@ #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 1) -#define PMSTS_BOTH_SELFREFRESH (1 << 0) +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) #define CLKCFG_MCHBAR 0x0c00 #define CLKCFG_FSBCLK_SHIFT 0 @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_WARM_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0,

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Patch merged into coreboot/master: pcengines/apu2: Add serial number in SMBIOS
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit 01bf599ea86abb360b0a57b892484dbb9c3ba387 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 16 19:50:28 2017 +0200 pcengines/apu2: Add serial number in SMBIOS Change-Id: Ic8149b1dd19d70935e00881cffa7ead0960d1c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18154 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król <piotr.krol(a)3mdeb.com> See https://review.coreboot.org/18154 for details. -gerrit

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Patch merged into coreboot/master: pcengines/apu2: Add SKU in SMBIOS
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit 104074994d741646016e431a30b8966b3fdfe439 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 16 19:59:52 2017 +0200 pcengines/apu2: Add SKU in SMBIOS Installed memory only, PCB revision cannot be detected. Change-Id: Ib6224018db3de4a7ddd9e6f7f30edc438c3f0702 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18153 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18153 for details. -gerrit

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Patch merged into coreboot/master: pcengines/apu2: Refactor reading memory strap
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit c27df8787801dac421b98c4dbb447e519065ae95 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 16 19:58:53 2017 +0200 pcengines/apu2: Refactor reading memory strap Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18152 for details. -gerrit

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Patch merged into coreboot/master: pcengines/apu2: Change SMBIOS part number
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit 0a06205ec65ea626ab94fa67680476266890044b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 14 09:44:40 2017 +0200 pcengines/apu2: Change SMBIOS part number This string should not include manufacturer name. Change-Id: I63793b16129334ea4930b8b0264a39d7f9849bba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18151 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18151 for details. -gerrit

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Patch merged into coreboot/master: pcengines/apu2: Remove DDI configuration
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit 7747757772f725ed091e5bfe706852a3f868bc5e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 14 13:01:16 2017 +0200 pcengines/apu2: Remove DDI configuration Assembled SoC part does not have integrated graphics. Change-Id: I5d157063cd850d343df73d448e6904c188a09730 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/18150 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18150 for details. -gerrit

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Patch set updated for coreboot: nb/gm45/gma.c: Allow to set pwm frequency from nvram.
by Arthur Heymans 20 Jan '17

20 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18191 -gerrit commit f9cb20c0024917225747fcf975aec6cec9dd23ef Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jan 20 17:36:20 2017 +0100 nb/gm45/gma.c: Allow to set pwm frequency from nvram. Change-Id: I968ff3548a732c08ab51d764d0f7311f3bbce620 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/x200/cmos.layout | 1 + src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..e77aa5e 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -79,6 +79,7 @@ entries # coreboot config options: northbridge 944 8 h 0 volume 952 4 e 11 gfx_uma_size +956 13 h 0 pwm_freq # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4886bb2..a91a8a2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -34,6 +34,7 @@ #include <drivers/intel/gma/i915.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <pc80/mc146818rtc.h> #define BASE_FREQUENCY 96000 @@ -646,7 +647,8 @@ static void gma_pm_init_post_vbios(struct device *const dev) const struct northbridge_intel_gm45_config *const conf = dev->chip_info; u32 reg32; - u8 reg8; + u8 duty; + u16 pwm_freq; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -674,14 +676,26 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - reg8 = 100; - if (conf->duty_cycle != 0) - reg8 = conf->duty_cycle; - if (conf->pwm_freq == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); - else - gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, - conf->pwm_freq, reg8)); + + reg32 = 0x06100610; + duty = 100; + pwm_freq = 0; + if (conf->duty_cycle) + duty = conf->duty_cycle; + + if (conf->pwm_freq) + pwm_freq = conf->pwm_freq; + get_option(&pwm_freq, "pwm_freq"); + /* Check for sanity of cmos value */ + if (pwm_freq < 50) { + printk(BIOS_DEBUG, + "PWM freq below treshhold, using default value\n"); + pwm_freq = conf->pwm_freq; + } + + if (pwm_freq) + reg32 = freq_to_blc_pwm_ctl(dev, pwm_freq, duty); + gtt_write(BLC_PWM_CTL, reg32); } static void gma_func0_init(struct device *dev)

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New patch to review for coreboot: Allow to set pwm frequency from cmos.
by Arthur Heymans 20 Jan '17

20 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18191 -gerrit commit 1326565a9066afcd694ba339e95078d5c783bfe6 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jan 20 17:36:20 2017 +0100 Allow to set pwm frequency from cmos. Change-Id: I968ff3548a732c08ab51d764d0f7311f3bbce620 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/x200/cmos.layout | 1 + src/northbridge/intel/gm45/gma.c | 32 +++++++++++++++++++++++--------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..e77aa5e 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -79,6 +79,7 @@ entries # coreboot config options: northbridge 944 8 h 0 volume 952 4 e 11 gfx_uma_size +956 13 h 0 pwm_freq # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4886bb2..a91a8a2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -34,6 +34,7 @@ #include <drivers/intel/gma/i915.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <pc80/mc146818rtc.h> #define BASE_FREQUENCY 96000 @@ -646,7 +647,8 @@ static void gma_pm_init_post_vbios(struct device *const dev) const struct northbridge_intel_gm45_config *const conf = dev->chip_info; u32 reg32; - u8 reg8; + u8 duty; + u16 pwm_freq; /* Setup Panel Power On Delays */ reg32 = gtt_read(PP_ON_DELAYS); @@ -674,14 +676,26 @@ static void gma_pm_init_post_vbios(struct device *const dev) /* Enable Backlight */ gtt_write(BLC_PWM_CTL2, (1 << 31)); - reg8 = 100; - if (conf->duty_cycle != 0) - reg8 = conf->duty_cycle; - if (conf->pwm_freq == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); - else - gtt_write(BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, - conf->pwm_freq, reg8)); + + reg32 = 0x06100610; + duty = 100; + pwm_freq = 0; + if (conf->duty_cycle) + duty = conf->duty_cycle; + + if (conf->pwm_freq) + pwm_freq = conf->pwm_freq; + get_option(&pwm_freq, "pwm_freq"); + /* Check for sanity of cmos value */ + if (pwm_freq < 50) { + printk(BIOS_DEBUG, + "PWM freq below treshhold, using default value\n"); + pwm_freq = conf->pwm_freq; + } + + if (pwm_freq) + reg32 = freq_to_blc_pwm_ctl(dev, pwm_freq, duty); + gtt_write(BLC_PWM_CTL, reg32); } static void gma_func0_init(struct device *dev)

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Patch set updated for coreboot: Makefile.inc: Explicitly set GNU11 as C language standard
by Nico Huber 20 Jan '17

20 Jan '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17636 -gerrit commit be51e8ab1e7bd89a1eab9d9b3638fe303ba3c2e4 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Tue Nov 29 10:30:44 2016 +0100 Makefile.inc: Explicitly set GNU11 as C language standard Different compiler versions use a different C language standard by default. GCC 4.9 uses GNU89 by default [1], while GCC 5.x uses GNU11 [2]. The discussion on the mailing list in thread *[RFC] Setting C99 by default* [3] resulted in the preference of C11, which results in build errors. So explicitly set it to GNU11, which is also what the current coreboot toolchain with GCC 5.3 is using. [1] https://gcc.gnu.org/onlinedocs/gcc-4.9.4/gcc/C-Dialect-Options.html [2] https://gcc.gnu.org/onlinedocs/gcc-5.4.0/gcc/Standards.html [3] https://www.coreboot.org/pipermail/coreboot/2016-November/082541.html Change-Id: If1569618f8044925ff72dcf3543480b34d4f90d6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index c5ce30f..0c6b351 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -353,7 +353,7 @@ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h CPPFLAGS_common += -I3rdparty -CFLAGS_common += -pipe -g -nostdinc +CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time

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Patch merged into filo/master: drivers/ide_new: Remove unused variable
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit 5d7a9dd1445cd2ac708dd55e40c82c2e8001d729 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jan 20 09:10:55 2017 +0100 drivers/ide_new: Remove unused variable Change-Id: I08d358563b36c67ce8ec21d5ef49312c1418cd42 Found-by: gcc (Debian 6.3.0-3) 6.3.0 20170118 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/18184 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18184 for details. -gerrit

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coreboot-gerrit January 2017