coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: build system: don't run xcompile or git for %clean/%config targets
by Patrick Georgi 19 Jan '17

19 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18182 -gerrit commit 5dc3632921e21b350abf6f05de5b0331cb4272ea Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jan 19 23:20:14 2017 +0100 build system: don't run xcompile or git for %clean/%config targets It takes a long time for no gain: We don't need to update the submodules, we don't need to fetch the revision, we don't need to find the compilers, when all we want to do is to manipulate the .config file or clean the build directory. Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile | 20 ++++++++++---------- Makefile.inc | 4 ++++ payloads/coreinfo/Makefile | 12 +++++++++--- payloads/libpayload/Makefile | 22 +++++++++++----------- 4 files changed, 34 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index 7801c47..2c87feb 100644 --- a/Makefile +++ b/Makefile @@ -30,16 +30,6 @@ ## SUCH DAMAGE. ## -# in addition to the dependency below, create the file if it doesn't exist -# to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) - -.xcompile: util/xcompile/xcompile - rm -f $@ - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null - rm -f $@.tmp - export top := $(CURDIR) export src := src export srck := $(top)/util/kconfig @@ -139,6 +129,16 @@ else include $(DOTCONFIG) +# in addition to the dependency below, create the file if it doesn't exist +# to silence stupid warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile))) + +.xcompile: util/xcompile/xcompile + rm -f $@ + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + rm -f $@.tmp + -include .xcompile ifneq ($(XCOMPILE_COMPLETE),1) diff --git a/Makefile.inc b/Makefile.inc index c5ce30f..43b8bd8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -13,7 +13,11 @@ ## GNU General Public License for more details. ## +ifneq ($(NOCOMPILE),1) GIT:=$(shell [ -e "$(top)/.git" ] && command -v git) +else +GIT:= +endif ####################################################################### # normalize Kconfig variables in a central place diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 486c96c..50659d3 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -20,6 +20,7 @@ srck := $(src)/../../util/kconfig coreinfo_obj := $(src)/build objk := $(src)/build/util/kconfig +ifeq ($(filter %clean,$(MAKECMDGOALS)),) export KERNELVERSION := 0.1.0 export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf @@ -128,6 +129,12 @@ $(coreinfo_obj)/config.h: $(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG)) +include $(srck)/Makefile + +.PHONY: $(PHONY) prepare + +else + clean: rm -rf build/*.elf build/*.o .xcompile @@ -135,6 +142,5 @@ distclean: clean rm -rf build lpbuild rm -f .config* lp.config* -include $(srck)/Makefile - -.PHONY: $(PHONY) prepare clean distclean +.PHONY: clean distclean +endif diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 00fb537..34df485 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -81,14 +81,6 @@ DOXYGEN_OUTPUT_DIR := doxygen all: real-all -# in addition to the dependency below, create the file if it doesn't exist -# to silence stupid warnings about a file that would be generated anyway. -$(if $(wildcard .xcompile),,$(eval $(shell $(top)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile))) - -.xcompile: $(top)/../../util/xcompile/xcompile - $< $(XGCCPATH) > $@.tmp - \mv -f $@.tmp $@ 2> /dev/null - ifeq ($(INNER_SCANBUILD),y) CC:=$(CC_real) HOSTCC:=$(CC_real) --hostcc @@ -101,8 +93,6 @@ include $(srck)/Makefile include $(HAVE_DOTCONFIG) -include .xcompile - ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips @@ -138,7 +128,7 @@ ifeq ($(strip $(HAVE_DOTCONFIG)),) NOCOMPILE:=1 endif ifneq ($(MAKECMDGOALS),) -ifneq ($(filter %config distclean,$(MAKECMDGOALS)),) +ifneq ($(filter %config %clean,$(MAKECMDGOALS)),) NOCOMPILE:=1 endif endif @@ -149,6 +139,16 @@ real-all: config else +# in addition to the dependency below, create the file if it doesn't exist +# to silence stupid warnings about a file that would be generated anyway. +$(if $(wildcard .xcompile)$(NOCOMPILE),,$(eval $(shell $(top)/../../util/xcompile/xcompile $(XGCCPATH) > .xcompile))) + +.xcompile: $(top)/../../util/xcompile/xcompile + $< $(XGCCPATH) > $@.tmp + \mv -f $@.tmp $@ 2> /dev/null + +-include .xcompile + ifneq ($(INNER_SCANBUILD),y) ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y) CC:=clang -m32

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Patch merged into coreboot/master: libpayload: Enable USB HID in veyron configuration
by gerrit＠coreboot.org 19 Jan '17

19 Jan '17

the following patch was just integrated into master: commit 3e7f14bfae5d0c025bcdd892233448c3cc1bdd91 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Dec 19 20:23:44 2016 +0100 libpayload: Enable USB HID in veyron configuration This enables USB HID support in the veyron config, since it seems to work correctly and is needed for interaction with depthcharge on devices without an embedded keyboard (such as veyron_mickey). Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/17930 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/17930 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/snappy: Disable unused devices
by gerrit＠coreboot.org 19 Jan '17

19 Jan '17

the following patch was just integrated into master: commit 926765b11bb1beecce7d8019eaebe5737a798f0d Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sat Jan 14 23:19:16 2017 +0800 mainboard/google/snappy: Disable unused devices The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18140 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: Ignore Audio DMIC IOSSTATE
by gerrit＠coreboot.org 19 Jan '17

19 Jan '17

the following patch was just integrated into master: commit c0eae6112f9c5449b312d6768b618b9f7fde23c9 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Jan 16 14:54:29 2017 -0800 mainboard/google/reef: Ignore Audio DMIC IOSSTATE Audio DMIC PLL needs to be ON in S0ix to support Wake on Voice. This requires GPIO_79 and GPIO_80 to be configured as IGNORE IOSSTATE. So DMIC CLKs will be ON in S0ix. Change-Id: If91045a8664ce853366b670b9db38d620818fbab Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Reviewed-on: https://review.coreboot.org/18155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18155 for details. -gerrit

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New patch to review for coreboot: configs/builder: Remove pre-defined VGA bios file
by Philipp Deppenwiese 19 Jan '17

19 Jan '17

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18181 -gerrit commit ae43b19464d6d752eca36472d1dcbbfc6d50af9d Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Jan 19 22:43:45 2017 +0100 configs/builder: Remove pre-defined VGA bios file Removes the pre-defined VGA bios file and id because the build system includes every vgabios. Also make the VGA output primary by default Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- configs/builder/config.lenovo_t420 | 3 +-- configs/builder/config.lenovo_t420s | 3 +-- configs/builder/config.lenovo_t430s | 3 +-- configs/builder/config.lenovo_t520 | 3 +-- configs/builder/config.lenovo_t530 | 3 +-- configs/builder/config.lenovo_x220 | 3 +-- configs/builder/config.lenovo_x220i | 3 +-- configs/builder/config.lenovo_x230 | 3 +-- 8 files changed, 8 insertions(+), 16 deletions(-) diff --git a/configs/builder/config.lenovo_t420 b/configs/builder/config.lenovo_t420 index bb653b3..e4e4b9b 100644 --- a/configs/builder/config.lenovo_t420 +++ b/configs/builder/config.lenovo_t420 @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0126.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t420s b/configs/builder/config.lenovo_t420s index c6eff36..7593b7a 100644 --- a/configs/builder/config.lenovo_t420s +++ b/configs/builder/config.lenovo_t420s @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0126.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t430s b/configs/builder/config.lenovo_t430s index 177b527..b21dbba 100644 --- a/configs/builder/config.lenovo_t430s +++ b/configs/builder/config.lenovo_t430s @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0166.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t520 b/configs/builder/config.lenovo_t520 index dcdaa5e..1d7816e 100644 --- a/configs/builder/config.lenovo_t520 +++ b/configs/builder/config.lenovo_t520 @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0126.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_t530 b/configs/builder/config.lenovo_t530 index f1da9ea..0106bbc 100644 --- a/configs/builder/config.lenovo_t530 +++ b/configs/builder/config.lenovo_t530 @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0106.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220 b/configs/builder/config.lenovo_x220 index fddd4bc..da5a474 100644 --- a/configs/builder/config.lenovo_x220 +++ b/configs/builder/config.lenovo_x220 @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0126.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x220i b/configs/builder/config.lenovo_x220i index a4b6a9d..5612f5b 100644 --- a/configs/builder/config.lenovo_x220i +++ b/configs/builder/config.lenovo_x220i @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0116.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y diff --git a/configs/builder/config.lenovo_x230 b/configs/builder/config.lenovo_x230 index 183aaad..d897f44 100644 --- a/configs/builder/config.lenovo_x230 +++ b/configs/builder/config.lenovo_x230 @@ -1,8 +1,6 @@ CONFIG_USE_OPTION_TABLE=y CONFIG_USE_BLOBS=y CONFIG_VENDOR_LENOVO=y -CONFIG_VGA_BIOS=y -CONFIG_VGA_BIOS_FILE="site-local/pci8086,0166.rom" CONFIG_HAVE_IFD_BIN=y CONFIG_HAVE_ME_BIN=y CONFIG_DRIVERS_PS2_KEYBOARD=y @@ -17,3 +15,4 @@ CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_LPC_TPM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x80000 CONFIG_PAYLOAD_NONE=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y

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Patch set updated for coreboot: nb/gm45/gma.c: Fix reported Pixel clock
by Arthur Heymans 19 Jan '17

19 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18180 -gerrit commit 45cea315ad121c52430b53d26855172960a8a544 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 19 16:45:45 2017 +0100 nb/gm45/gma.c: Fix reported Pixel clock Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4886bb2..cbb8451 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -203,8 +203,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) @@ -479,8 +479,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); mdelay(1); write32(mmio + FP0(0), (pixel_n << 16)

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New patch to review for coreboot: nb/gm45/gma.c: Fix reported Pixel clock
by Arthur Heymans 19 Jan '17

19 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18180 -gerrit commit 05ea56828ca20ad9b47b427c3a29d9226707d17e Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 19 16:45:45 2017 +0100 nb/gm45/gma.c: Fix reported Pixel clock Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 38bd3ca..357adb1 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -197,8 +197,8 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); write32(mmio + LVDS, (hpolarity << 20) | (vpolarity << 21) @@ -466,8 +466,8 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", - BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / - (pixel_n + 2) / (pixel_p1 * pixel_p2))); + BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / + (pixel_n + 2) / (pixel_p1 * pixel_p2)); mdelay(1); write32(mmio + FP0(0), (pixel_n << 16)

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New patch to review for coreboot: nb/gm45/gma.c: Decode edid before doing native graphic init
by Arthur Heymans 19 Jan '17

19 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18179 -gerrit commit 7027c0cd0134d09246e0439d35dd4a6256d855a5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 19 14:38:34 2017 +0100 nb/gm45/gma.c: Decode edid before doing native graphic init This allows the EDID data to be used outside of the native graphic init path without having to fetch it again. This extends return values of decode_edid to make the distinction between invalid EDID and 'not connected' EDID. TESTED on Lenovo X200 Change-Id: I062b42e282beb88bee46aa17934a01845b9b50bf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/include/edid.h | 6 +++ src/lib/edid.c | 14 +++---- src/northbridge/intel/gm45/gma.c | 88 +++++++++++++++++++--------------------- 3 files changed, 54 insertions(+), 54 deletions(-) diff --git a/src/include/edid.h b/src/include/edid.h index cf81258..f973503 100644 --- a/src/include/edid.h +++ b/src/include/edid.h @@ -91,6 +91,12 @@ struct edid { int hdmi_monitor_detected; }; +enum edid_status { + EDID_NOT_CONFORMANT, + EDID_CONFORMANT, + EDID_ABSENT, +}; + /* Defined in src/lib/edid.c */ int decode_edid(unsigned char *edid, int size, struct edid *out); void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp, diff --git a/src/lib/edid.c b/src/lib/edid.c index d1b9c9f..3dd2b08 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -1056,7 +1056,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) .has_valid_range_descriptor = 1, .has_valid_max_dotclock = 1, .has_valid_string_termination = 1, - .conformant = 1, + .conformant = EDID_CONFORMANT, }; dump_breakdown(edid); @@ -1065,7 +1065,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) if (!edid || memcmp(edid, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8)) { printk(BIOS_SPEW, "No header found\n"); - return 1; + return EDID_ABSENT; } if (manufacturer_name(edid + 0x08)) @@ -1359,7 +1359,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) !c.has_valid_string_termination || !c.has_valid_descriptor_pad || !c.has_preferred_timing) - c.conformant = 0; + c.conformant = EDID_NOT_CONFORMANT; if (!c.conformant) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.4!\n"); if (c.nonconformant_digital_display) @@ -1376,7 +1376,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) !c.has_valid_string_termination || !c.has_valid_descriptor_pad || !c.has_preferred_timing) { - c.conformant = 0; + c.conformant = EDID_NOT_CONFORMANT; } /** * According to E-EDID (EDIDv1.3), has_name_descriptor and @@ -1407,7 +1407,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) } else if (c.claims_one_point_two) { if (c.nonconformant_digital_display || !c.has_valid_string_termination) - c.conformant = 0; + c.conformant = EDID_NOT_CONFORMANT; if (!c.conformant) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.2!\n"); if (c.nonconformant_digital_display) @@ -1417,7 +1417,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) printk(BIOS_ERR, "\tDetailed block string not properly terminated\n"); } else if (c.claims_one_point_oh) { if (c.seen_non_detailed_descriptor) - c.conformant = 0; + c.conformant = EDID_NOT_CONFORMANT; if (!c.conformant) printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.0!\n"); if (c.seen_non_detailed_descriptor) @@ -1435,7 +1435,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out) !c.has_valid_descriptor_ordering || !c.has_valid_range_descriptor || !c.manufacturer_name_well_formed) { - c.conformant = 0; + c.conformant = EDID_CONFORMANT; printk(BIOS_ERR, "EDID block does not conform at all!\n"); if (c.nonconformant_extension) printk(BIOS_ERR, "\tHas %d nonconformant extension block(s)\n", diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 4886bb2..38bd3ca 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -50,12 +50,10 @@ void gtt_write(u32 reg, u32 data) } static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb, + struct edid edid) { - int i; - u8 edid_data[128]; - struct edid edid; struct edid_mode *mode; u32 hactive, vactive, right_border, bottom_border; int hpolarity, vpolarity; @@ -93,15 +91,11 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, - sizeof(edid_data)); - decode_edid(edid_data, - sizeof(edid_data), &edid); - mode = &edid.mode; - /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); + mode = &edid.mode; + hactive = edid.x_resolution; vactive = edid.y_resolution; right_border = mode->hborder; @@ -321,12 +315,11 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb, + struct edid edid) { int i; - u8 edid_data[128]; - struct edid edid; struct edid_mode *mode; u32 hactive, vactive, right_border, bottom_border; int hpolarity, vpolarity; @@ -378,17 +371,11 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, udelay(1); - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, - sizeof(edid_data)); - intel_gmbus_stop(mmio + GMBUS0); - decode_edid(edid_data, - sizeof(edid_data), &edid); - mode = &edid.mode; - - /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); + mode = &edid.mode; + hactive = edid.x_resolution; vactive = edid.y_resolution; right_border = mode->hborder; @@ -591,25 +578,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, } -/* compare the header of the vga edid header */ -/* if vga is not connected it should not have a correct header */ -static u8 vga_connected(u8 *mmio) -{ - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, - sizeof(vga_edid)); - intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); - return 0; - } - } - printk(BIOS_SPEW, "VGA display connected\n"); - return 1; -} - static u32 get_cdclk(struct device *const dev) { const u16 cdclk_sel = @@ -687,6 +655,10 @@ static void gma_pm_init_post_vbios(struct device *const dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u8 *mmio; + u8 edid_data_vga[128], edid_data_lvds[128]; + struct edid edid_vga, edid_lvds; + int lvds_edid_status, vga_edid_status; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -695,14 +667,30 @@ static void gma_func0_init(struct device *dev) /* Init graphics power management */ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + mmio = res2mmio(gtt_res, 0, 0); struct northbridge_intel_gm45_config *conf = dev->chip_info; if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ + printk(BIOS_DEBUG, "Initialising IGD using VBIOS\n"); pci_dev_init(dev); } + printk(BIOS_DEBUG, "LVDS EDID\n"); + intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data_lvds, + sizeof(edid_data_lvds)); + intel_gmbus_stop(mmio + GMBUS0); + lvds_edid_status = decode_edid(edid_data_lvds, + sizeof(edid_data_lvds), &edid_lvds); + + printk(BIOS_DEBUG, "VGA EDID\n"); + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data_vga, + sizeof(edid_data_vga)); + intel_gmbus_stop(mmio + GMBUS0); + vga_edid_status = decode_edid(edid_data_vga, + sizeof(edid_data_vga), &edid_vga); + /* Post VBIOS init */ gma_pm_init_post_vbios(dev); @@ -719,14 +707,20 @@ static void gma_func0_init(struct device *dev) if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base && lfb_res && lfb_res->base) { printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", + "Initializing display without OPROM. MMIO 0x%llx\n", gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) - gma_init_vga(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); + if (vga_edid_status != EDID_ABSENT) { + printk(BIOS_DEBUG, + "Initialising display on VGA output\n"); + gma_init_vga(conf, mmio, physbase, + pio_res->base, lfb_res->base, edid_vga); + } else { + printk(BIOS_DEBUG, + "Initialising display on LVDS output\n"); + gma_init_lvds(conf, mmio, physbase, + pio_res->base, lfb_res->base, + edid_lvds); + } } /* Linux relies on VBT for panel info. */

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Patch set updated for coreboot: nb/x4x/raminit: Fix programming dram timings
by Martin Roth 19 Jan '17

19 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18022 -gerrit commit a4a9c0c986d4e265917cd39a9d3f619da22c6338 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Jan 3 00:49:45 2017 +0100 nb/x4x/raminit: Fix programming dram timings The results were obtained by comparing the MCHBAR registers of vendor bios with coreboot at the same dram timings. This fixes 2 issues: * 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with 800MHz raminit failed; * 1067MHz fsb CPUs did not boot when second dimm slot was populated. TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with DDR2 667 and 800MHz dimms. Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 4 +--- src/northbridge/intel/x4x/raminit_ddr2.c | 16 ++++++++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 122cab5..86f63f1 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -228,9 +228,7 @@ static void sdram_detect_ram_speed(struct sysinfo *s) // Max RAM speed if (s->spd_type == DDR2) { - // FIXME: Limit memory speed to 667MHz if FSB is 1333MHz - maxfreq = (s->max_fsb == FSB_CLOCK_1333MHz) - ? MEM_CLOCK_667MHz : MEM_CLOCK_800MHz; + maxfreq = MEM_CLOCK_800MHz; // Choose common CAS latency from {6,5}, 4 does not work commoncas = 0x60; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..d38f69e 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -520,6 +520,9 @@ static void timings_ddr2(struct sysinfo *s) u8 trpmod = 0; u8 bankmod = 1; u8 pagemod = 0; + u8 adjusted_cas; + + adjusted_cas = s->selected_timings.CAS - 3; u16 fsb2ps[3] = { 5000, // 800 @@ -563,13 +566,14 @@ static void timings_ddr2(struct sysinfo *s) } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - MCHBAR8(0x400*i + 0x2f6) = MCHBAR8(0x400*i + 0x2f6) | 0x3; + MCHBAR8(0x400*i + 0x26f) = MCHBAR8(0x400*i + 0x26f) | 0x3; MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2; - MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) | (twl << 4); + MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) + | (0 << 4); /* tWL - x ?? */ MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) | - s->selected_timings.CAS; + adjusted_cas; MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) | - ((s->selected_timings.CAS + 9) << 8); + ((adjusted_cas + 9) << 8); reg16 = (s->selected_timings.tRAS << 11) | ((twl + 4 + s->selected_timings.tWR) << 6) | @@ -649,7 +653,7 @@ static void timings_ddr2(struct sysinfo *s) fsb = fsb2ps[s->selected_timings.fsb_clk]; ddr = ddr2ps[s->selected_timings.mem_clk]; - reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); + reg32 = (u32)((adjusted_cas + 7 + reg8) * ddr); reg32 = (u32)((reg32 / fsb) << 8); reg32 |= 0x0e000000; if ((fsb2mhz(s->selected_timings.fsb_clk) / @@ -727,7 +731,7 @@ static void timings_ddr2(struct sysinfo *s) MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); - reg8 = (u8)((MCHBAR32(0x258) & ~0x1e0000) >> 17); + reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; MCHBAR8(0x12f) = 0x4c; reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);

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New patch to review for coreboot: rockchip/rk3399: set edp pclk to 25MHz
by Patrick Georgi 19 Jan '17

19 Jan '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18178 -gerrit commit 151d8b429996c1a10b74c368e55723fd3f40c58d Author: Lin Huang <hl(a)rock-chips.com> Date: Wed Jan 18 09:44:34 2017 +0800 rockchip/rk3399: set edp pclk to 25MHz it may cause edp aux transfer error if set the edp pclk clock too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 25 +++++++++++++++++++++++++ src/soc/rockchip/rk3399/display.c | 1 + src/soc/rockchip/rk3399/include/soc/clock.h | 1 + 3 files changed, 27 insertions(+) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 383a761..eb413a1 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -181,6 +181,13 @@ enum { CLK_TSADC_DIV_CON_MASK = 0x3ff, CLK_TSADC_DIV_CON_SHIFT = 0, + /* CLKSEL_CON44 */ + CLK_PCLK_EDP_PLL_SEL_MASK = 1, + CLK_PCLK_EDP_PLL_SEL_SHIFT = 15, + CLK_PCLK_EDP_PLL_SEL_CPLL = 0, + CLK_PCLK_EDP_DIV_CON_MASK = 0x3f, + CLK_PCLK_EDP_DIV_CON_SHIFT = 8, + /* CLKSEL_CON47 & CLKSEL_CON48 */ ACLK_VOP_PLL_SEL_MASK = 0x3, ACLK_VOP_PLL_SEL_SHIFT = 6, @@ -838,3 +845,21 @@ int rkclk_was_watchdog_reset(void) /* Bits 5 and 4 are "second" and "first" global watchdog reset. */ return read32(&cru_ptr->glb_rst_st) & 0x30; } + +void rkclk_configure_edp(unsigned int hz) +{ + int src_clk_div; + + src_clk_div = CPLL_HZ / hz; + assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ)); + + write32(&cru_ptr->clksel_con[44], + RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK << + CLK_PCLK_EDP_PLL_SEL_SHIFT | + CLK_PCLK_EDP_DIV_CON_MASK << + CLK_PCLK_EDP_DIV_CON_SHIFT, + CLK_PCLK_EDP_PLL_SEL_CPLL << + CLK_PCLK_EDP_PLL_SEL_SHIFT | + (src_clk_div - 1) << + CLK_PCLK_EDP_DIV_CON_SHIFT)); +} diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 5199bf3..c7ca891 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -65,6 +65,7 @@ void rk_display_init(device_t dev) case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); rkclk_configure_vop_aclk(vop_id, 200 * MHz); + rkclk_configure_edp(25 * MHz); /* select edp signal from vop0 */ write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 82bf215..3047f73 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -119,5 +119,6 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); int rkclk_was_watchdog_reset(void); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); +void rkclk_configure_edp(unsigned int hz); #endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */

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coreboot-gerrit January 2017