coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: nb/gm45/gma.c: Fix reported Pixel clock
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit 1f060287934219a3b3b7ec0f41d4533e2c450a00 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 19 16:45:45 2017 +0100 nb/gm45/gma.c: Fix reported Pixel clock Change-Id: Ie1c360ac29eb30af6f4b5447add467f3c13ba211 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18180 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/18180 for details. -gerrit

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New patch to review for coreboot: soc/intel/apollolake: correct GPIO 13 IRQ number
by Aaron Durbin 20 Jan '17

20 Jan '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18190 -gerrit commit 871e6af04ecbc38374d59bcfdc6cd0b678e28814 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 20 14:10:26 2017 -0600 soc/intel/apollolake: correct GPIO 13 IRQ number The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/gpio_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 33daf10..18b95c9 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -506,7 +506,7 @@ #define GPIO_10_IRQ 0x6D #define GPIO_11_IRQ 0x6E #define GPIO_12_IRQ 0x6F -#define GPIO_13_IRQ 0x6F +#define GPIO_13_IRQ 0x70 #define GPIO_14_IRQ 0x71 #define GPIO_15_IRQ 0x72 #define GPIO_16_IRQ 0x73

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New patch to review for coreboot: mainboard/google/reef: remove internal pullups on PP1800_S rail
by Aaron Durbin 20 Jan '17

20 Jan '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18189 -gerrit commit 2cbe0d4953868584c24c15f03a70d2c8d871e30f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 20 14:03:50 2017 -0600 mainboard/google/reef: remove internal pullups on PP1800_S rail The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index a764b46..390ef0f 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -58,8 +58,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ - /* Card detect is active LOW. Pull up by 20K */ - PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + /* Card detect is active LOW with external pull up. */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ /* CLK feedback, internal signal, needs 20K pull down */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ @@ -288,7 +288,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */ PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_APIC_LOW(GPIO_13, UP_20K, DEEP), /* PEN_INT_ODL */ + PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */ PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */ PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */ PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */ @@ -299,7 +299,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */ PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, LEVEL), /* EC wake */ PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI(GPIO_24, UP_20K, DEEP), /* PEN_PDCT_ODL */ + PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */ PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */

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Patch merged into coreboot/master: lb_tables: make lb_mainboard and lb_strings record sizes 64-bit aligned
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit 23bb036dcb76c30efa708f09a96184583cc367d1 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Jan 17 23:20:48 2017 -0800 lb_tables: make lb_mainboard and lb_strings record sizes 64-bit aligned They were sized to 32-bit alignment, this grows them to 64 bit-aligned. Change-Id: I494b942c4866a7912fb48a53f9524db20ac53a8c Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/18165 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18165 for details. -gerrit

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Patch merged into coreboot/master: configs/builder: Remove pre-defined VGA bios file
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit 5c765ceff9060d11e7b3b712528ad65ba0149dac Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Thu Jan 19 22:43:45 2017 +0100 configs/builder: Remove pre-defined VGA bios file Removes the pre-defined VGA bios file and id because the build system includes every vgabios. Also make the VGA output primary by default Change-Id: I87d52ef2d1e151c6e54beba64316fe9043668158 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-on: https://review.coreboot.org/18181 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18181 for details. -gerrit

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Patch set updated for coreboot: .gitignore: Don’t track Tint directory
by Paul Menzel 20 Jan '17

20 Jan '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18188 -gerrit commit fcc44743cc8fd32d310da20eb30420374300936a Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Fri Jan 20 17:33:19 2017 +0100 .gitignore: Don’t track Tint directory This is done already for the other payloads. Change-Id: I98eb05404c0e181ad99a61d8c97987ceadd9a53c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index df7bff4..48c9648 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,7 @@ payloads/external/depthcharge/depthcharge/ payloads/external/FILO/filo/ payloads/external/GRUB2/grub2/ payloads/external/SeaBIOS/seabios/ +payloads/external/tint/tint/ payloads/external/U-Boot/u-boot/ payloads/external/Memtest86Plus/memtest86plus/ payloads/external/iPXE/ipxe/

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New patch to review for coreboot: .gitignore: Don’t track `grub.cfg` by git
by Paul Menzel 20 Jan '17

20 Jan '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18188 -gerrit commit 54526e900b23cbcd46eec427f22658911eee7ec0 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Fri Jan 20 17:33:19 2017 +0100 .gitignore: Don’t track `grub.cfg` by git The latest GRUB integration uses the file `grub.cfg` by default. Don’t track that. Change-Id: I98eb05404c0e181ad99a61d8c97987ceadd9a53c Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index df7bff4..48c9648 100644 --- a/.gitignore +++ b/.gitignore @@ -17,6 +17,7 @@ payloads/external/depthcharge/depthcharge/ payloads/external/FILO/filo/ payloads/external/GRUB2/grub2/ payloads/external/SeaBIOS/seabios/ +payloads/external/tint/tint/ payloads/external/U-Boot/u-boot/ payloads/external/Memtest86Plus/memtest86plus/ payloads/external/iPXE/ipxe/

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Patch merged into coreboot/master: util/intelmetool: Try to activate the ME before scanning PCIe for it
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit e8ad3c7b954b81a26073c5a4d529034db993db0e Author: Dan Elkouby <streetwalrus(a)codewalr.us> Date: Mon Jan 16 20:04:51 2017 +0200 util/intelmetool: Try to activate the ME before scanning PCIe for it When the ME is hidden (most likely because it was disabled), it cannot be found until activate_me() is called. Change-Id: Ie1f65f61eb131577d7254af582e2709660f4da27 Signed-off-by: Dan Elkouby <streetwalrus(a)codewalr.us> Reviewed-on: https://review.coreboot.org/18149 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/18149 for details. -gerrit

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Patch merged into coreboot/master: google/snappy: Add weida touchscreen support
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit 26949e65af2860544983e87314c66e68d4e18142 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Wed Jan 18 18:00:11 2017 +0800 google/snappy: Add weida touchscreen support Add weida touchscreen as 2nd touchscreen source BUG=chrome-os-partner:61865 BRANCH=reef TEST=emerge-snappy coreboot, and verified that touchscreen works on snappy. Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18166 for details. -gerrit

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Patch merged into coreboot/master: google/snappy: Use exported GPIOs and ACPI regulator for touchscreen
by gerrit＠coreboot.org 20 Jan '17

20 Jan '17

the following patch was just integrated into master: commit bf68f2286c4850f175a3ea350ebfa67a463f3f33 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Wed Jan 18 10:47:37 2017 +0800 google/snappy: Use exported GPIOs and ACPI regulator for touchscreen ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=None BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/18163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18163 for details. -gerrit

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coreboot-gerrit January 2017