coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/eve: Enable keyboard backlight in bootblock
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18197 -gerrit commit 63383a0e2c0986cb612043ab34200dbbbeb54a24 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 15:42:26 2017 -0800 google/eve: Enable keyboard backlight in bootblock Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 2c524f4..00d265c 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -14,9 +14,13 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <bootblock_common.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pm.h> #include "gpio.h" static void early_config_gpio(void) @@ -26,5 +30,9 @@ static void early_config_gpio(void) void bootblock_mainboard_init(void) { + /* Turn on keyboard backlight to indicate we are booting */ + if (acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_STS)) != ACPI_S3) + google_chromeec_kbbacklight(75); + early_config_gpio(); }

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New patch to review for coreboot: google/eve: Enable keyboard backlight in bootblock
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18197 -gerrit commit 0e07ce0ece7e6865fb5fa0e47e17fc84bcf3b83c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 15:42:26 2017 -0800 google/eve: Enable keyboard backlight in bootblock Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 2c524f4..00d265c 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -14,9 +14,13 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <bootblock_common.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pm.h> #include "gpio.h" static void early_config_gpio(void) @@ -26,5 +30,9 @@ static void early_config_gpio(void) void bootblock_mainboard_init(void) { + /* Turn on keyboard backlight to indicate we are booting */ + if (acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_STS)) != ACPI_S3) + google_chromeec_kbbacklight(75); + early_config_gpio(); }

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New patch to review for coreboot: nvramcui: Declare variable outside for loop
by Paul Menzel 21 Jan '17

21 Jan '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18196 -gerrit commit 8d025e3fc7d8a836683259d336f01616508ebe08 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jan 20 23:29:21 2017 +0100 nvramcui: Declare variable outside for loop Make the code C89 compatible, which doesn’t allow loop initial declarations. Older compilers use C89 by default, so just declare the variable outside. Change-Id: I3c5a8109e66f7a25687f4e4b2c72718d74276e04 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/nvramcui/nvramcui.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 84e5536..97be9df 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -90,8 +90,9 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, FIELD **fields, int numopts, int maxlength) { struct cb_cmos_entries *option = first_cmos_entry(opttbl); + int i; - for (int i = 0; i < numopts; i++) { + for (i = 0; i < numopts; i++) { while ((option->config == 'r') || (strcmp("check_sum", (char *)option->name) == 0)) { option = next_cmos_entry(option); @@ -173,6 +174,7 @@ static void cmos_walk_options(struct cb_cmos_option_table *opttbl, int main(void) { int ch, done; + int i; /* coreboot data structures */ lib_get_sysinfo(); @@ -268,7 +270,7 @@ int main(void) endwin(); - for (int i = 0; i < numopts; i++) { + for (i = 0; i < numopts; i++) { char *name = field_buffer(fields[2 * i], 0); char *value = field_buffer(fields[2 * i + 1], 0); char *ptr;

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Patch merged into coreboot/master: soc/intel/apollolake: correct GPIO 13 IRQ number
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit ba32f0f91cfd79434b53d60a16d4c072fac384ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 20 14:10:26 2017 -0600 soc/intel/apollolake: correct GPIO 13 IRQ number The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/18190 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18190 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: remove internal pullups on PP1800_S rail
by gerrit＠coreboot.org 21 Jan '17

21 Jan '17

the following patch was just integrated into master: commit aa6482e88e2f553ee841284e5b44672eee85d3ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 20 14:03:50 2017 -0600 mainboard/google/reef: remove internal pullups on PP1800_S rail The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18189 for details. -gerrit

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Patch set updated for coreboot: mb/lenovo/t400: Implement hybrid graphic in romstage
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18010 -gerrit commit 05e134def5f49cb45f952459301dc00111b92c82 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 2 16:16:45 2017 +0100 mb/lenovo/t400: Implement hybrid graphic in romstage The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work for t400/t500. Replace it with a custom romstage implementation. Tested on Lenovo T500 with dual graphics: * Intel Native GFX init * AMD VBios * GNU Linux 4.8.13 * SeaBios as payload * Integrated is working (24 W) ** Seems to always run at 100% * Discrete is working (44 W) ** Seems to always run at 100% * Switchable is working (34 W) ** Both GPUs are enabled, with Intel being connected to the panel ** DRI_PRIME allows to use AMD GPU ** ACPI doesn't seem to work (no vgaswitcheroo) Depends on Change-Id: I03578d358f31b605f300a67f5b078eff834e070c Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Depends on Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2 Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t400/Makefile.inc | 1 + src/mainboard/lenovo/t400/cmos.layout | 1 + src/mainboard/lenovo/t400/hybrid_graphics.c | 87 +++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 9 ++- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..150199e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b382efb..c02a70b 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -15,3 +15,4 @@ ramstage-y += dock.c ramstage-y += cstates.c +romstage-y += hybrid_graphics.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..cf31453 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -142,6 +142,7 @@ enumerations 11 12 352M 12 0 Integrated Only 12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c new file mode 100644 index 0000000..2bbb0d2 --- /dev/null +++ b/src/mainboard/lenovo/t400/hybrid_graphics.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/gm45/gm45.h> +#include <console/console.h> +#include <option.h> + +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define MUX_GPIO 22 +#define BCL_CTL_GPIO 19 +#define GFX_PWR_EN_GPIO 49 + +#define HYBRID_DETECT_GPIO 21 + +void hybrid_graphics_init(sysinfo_t *sysinfo); + +static bool hybrid_graphics_installed(void) +{ + if (get_gpio(HYBRID_DETECT_GPIO)) + return false; + else + return true; +} + +void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + /* Set default mode */ + uint8_t hybrid_graphics_mode = 0xff; + + if (hybrid_graphics_installed()) { + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available.\n"); + } else + printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); + + /* Select appropriate hybrid graphics device */ + switch (hybrid_graphics_mode) { + case HYBRID_GRAPHICS_INTEGRATED_ONLY: + printk(BIOS_DEBUG, "Activating Integrated Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + case HYBRID_GRAPHICS_DISCRETE_ONLY: + printk(BIOS_DEBUG, "Activating Discrete Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_SWITCHABLE: + printk(BIOS_DEBUG, "Activating Switchable.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + /* Fall-through */ + default: + /* The display is not connected to a mux or switchable. */ + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 1; + break; + } +} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 013d22c..e76d4c4 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -36,6 +36,8 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +void hybrid_graphics_init(sysinfo_t *sysinfo); + static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -101,8 +103,6 @@ void mainboard_romstage_entry(unsigned long bist) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); @@ -112,6 +112,11 @@ void mainboard_romstage_entry(unsigned long bist) deven |= 2; pci_write_config32(MCH_DEV, D0F0_DEVEN, deven); + /* Configure graphic GPIOs. + * Make sure there's a little delay between + * setup_pch_gpios() and this call ! */ + hybrid_graphics_init(&sysinfo); + raminit(&sysinfo, s3resume); init_pm(&sysinfo, 0);

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Patch set updated for coreboot: mb/lenovo/t400/romstage: Enable D1F0
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18195 -gerrit commit d635e8ddf4466af62100c51508d08b0f13af4cf0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:45:03 2017 +0100 mb/lenovo/t400/romstage: Enable D1F0 Enable PEG (D1F0) to make sure it can be accessed by raminit(). Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/romstage.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index d110d4f..013d22c 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -104,11 +104,15 @@ void mainboard_romstage_entry(unsigned long bist) sysinfo.enable_igd = 1; sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); - raminit(&sysinfo, s3resume); - const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); + u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ - pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); + deven &= ~0x4000; + /* Enable D1F0 (PEG). */ + deven |= 2; + pci_write_config32(MCH_DEV, D0F0_DEVEN, deven); + + raminit(&sysinfo, s3resume); init_pm(&sysinfo, 0);

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Patch set updated for coreboot: nb/intel/gm45/igd: Hide IGD while disabling
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18194 -gerrit commit a50a5e1c4677e0d965bc07e78970f971aecda4aa Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:43:52 2017 +0100 nb/intel/gm45/igd: Hide IGD while disabling Hide the IGD to make sure ramstage doesn't detect it. Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/igd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 74572ca..1164339 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -127,6 +127,11 @@ static void disable_igd(const sysinfo_t *const sysinfo) MCHBAR16(0x119e) = (MCHBAR16(0x119e) & ~(7 << 13)) | (4 << 13); MCHBAR16(0x119e) |= (1 << 12); } + + /* Hide IGD. */ + u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN); + deven &= ~(3 << 3); + pci_write_config32(mch_dev, D0F0_DEVEN, deven); } void init_igd(const sysinfo_t *const sysinfo)

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Patch set updated for coreboot: nb/intel/gm45/nb: Move DEVEN device hiding
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18193 -gerrit commit f4dc5b8dd2a115619caf2679d8428e9f0dc31f43 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:33:20 2017 +0100 nb/intel/gm45/nb: Move DEVEN device hiding Move and improve DEVEN device hiding. Instead of relying only on devicetree, allow the PCI code to scan for devices, and invoke custom PCI driver functions. Therefore the code has been moved to PCI init function. Add support for disabling IGD. Fixes a crash in GNU Linux: In case the IGD is disabled by romstage, Linux still detects the IGD, but as it doesn't have resources assigned, it causes a crash in drm kernel module. Change-Id: I03578d358f31b605f300a67f5b078eff834e070c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/northbridge.c | 79 +++++++++++++++----------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 3cb7d11..65e2052 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -180,14 +180,49 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(device_t d0f0) { + u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + device_t dev; u32 reg32; /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 = pci_read_config32(d0f0, PCI_COMMAND); reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config32(d0f0, PCI_COMMAND, reg32); + + /* Hide internal functions on bus 0. */ + printk(BIOS_INFO, "mch_domain_init: Hiding "); + + dev = dev_find_slot(0, PCI_DEVFN(3, 3)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "ME "); + deven &= ~(1 << 9); + } + + dev = dev_find_slot(0, PCI_DEVFN(2, 1)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "IGD_DC "); + deven &= ~(1 << 4); + } + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "IGD "); + deven &= ~(1 << 3); + } + + dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "PEG "); + deven &= ~(1 << 1); + } + printk(BIOS_INFO, "\n"); + + if (!(deven & (0xf << 6))) + deven &= ~(1 << 14); + + pci_write_config32(d0f0, D0F0_DEVEN, deven); } static struct device_operations pci_domain_ops = { @@ -225,45 +260,7 @@ static void enable_dev(device_t dev) } } -static void gm45_init(void *const chip_info) -{ - int dev, fn, bit_base; - - struct device *const d0f0 = dev_find_slot(0, 0); - - /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { - switch (dev) { - case 3: /* ME */ - fn = 3; - bit_base = 6; - break; - case 2: /* IGD */ - fn = 1; - bit_base = 3; - break; - case 1: /* PEG */ - fn = 0; - bit_base = 1; - break; - } - for (; fn >= 0; --fn) { - const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); - pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); - } - } - - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); - if (!(deven & (0xf << 6))) - pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); -} - struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") .enable_dev = enable_dev, - .init = gm45_init, };

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Patch set updated for coreboot: x86/acpi: Add VFCT table
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18192 -gerrit commit 98c5d413902ab6e3ca59f92ef24e1818d1fded3d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 x86/acpi: Add VFCT table Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 --- src/arch/x86/acpi.c | 25 ++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 ++++++++++++++++++ src/device/pci_device.c | 3 ++ src/device/pci_rom.c | 65 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 7 +++++ 5 files changed, 129 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 53c4135..703bfa1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -589,6 +589,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6854573..f36bd8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -220,6 +220,31 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; + +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; //0x4C + u32 PCIDevice; //0x50 + u32 PCIFunction; //0x54 + u16 VendorID; //0x58 + u16 DeviceID; //0x5A + u16 SSVID; //0x5C + u16 SSID; //0x5E + u32 Revision; //0x60 + u32 ImageLength; //0x64 + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; //0x24 + u32 VBIOSImageOffset; //0x34. + u32 Lib1ImageOffset; //0x38. + u32 Reserved[4]; //0x3C + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -601,6 +626,10 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 06294d0..b2e3c9a 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -735,6 +735,9 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = pci_rom_write_acpi_tables, +#endif .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..20621d3 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -169,3 +169,68 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +/* ACPI */ +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_ERR, "pci_rom_acpi_fill_vfct failed\n"); + return current; + } + + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = rom->size * 512; + memcpy((void *)&header->VbiosContent, rom, header->ImageLength); + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + struct rom_header *rom; + + /* Only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* Only handle enabled devices */ + if (!device->enabled) + return current; + + /* Probe for option rom */ + rom = pci_rom_probe(device); + if (!rom) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} +#endif diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..3f09778 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -35,6 +36,12 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); + u32 map_oprom_vendev(u32 vendev); #endif

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coreboot-gerrit January 2017