coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

1 participants
852 discussions

Patch set updated for coreboot: util/blobtool: Add new tool for compiling/decompiling data blobs
by Damien Zammit 21 Jan '17

21 Jan '17

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17445 -gerrit commit a9d6a3d2f929bba382fc006c3500c3d724687a5e Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Nov 16 21:06:54 2016 +1100 util/blobtool: Add new tool for compiling/decompiling data blobs Given a specification of bitfields defined e.g. as follows: specfile: { "field1" : 8, "field2" : 4, "field3" : 4 } and a set of values for setting defaults: setterfile: { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } You can generate a binary packed blob as follows: ./blobtool specfile setterfile binaryoutput binaryoutput: ff ff The reverse is also possible, i.e. you can regenerate the setter: ./blobtool -d specfile binaryoutput setterorig setterorig: # AUTOGENERATED SETTER BY BLOBTOOL { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } This tool comes with spec/set files for X200 flash descriptor and ICH9M GbE region, and can be extended or used to decompile other data blobs with known specs. Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- util/blobtool/Makefile | 29 +++ util/blobtool/blobtool.l | 145 ++++++++++++ util/blobtool/blobtool.y | 537 ++++++++++++++++++++++++++++++++++++++++++ util/blobtool/gbe-ich9m.set | 88 +++++++ util/blobtool/gbe-ich9m.spec | 142 +++++++++++ util/blobtool/ifd-x200.set | 167 +++++++++++++ util/blobtool/ifd-x200.spec | 187 +++++++++++++++ util/blobtool/it8718f-ec.spec | 368 +++++++++++++++++++++++++++++ 8 files changed, 1663 insertions(+) diff --git a/util/blobtool/Makefile b/util/blobtool/Makefile new file mode 100644 index 0000000..ee706db --- /dev/null +++ b/util/blobtool/Makefile @@ -0,0 +1,29 @@ +CC = gcc +YACC = bison +LEX = flex +TARGET=blobtool + +$(TARGET): $(TARGET).lex.o $(TARGET).tab.o + $(CC) $^ -Wall -Wno-unused-function -g -lfl -o $@ + +$(TARGET).lex.c: $(TARGET).l $(TARGET).tab.h + $(LEX) -o $(patsubst $(TARGET).l,$(TARGET).lex.c,$<) $< + +$(TARGET).tab.c $(TARGET).tab.h: $(TARGET).y + $(YACC) -d $< + +# Use this target to generate GbE for X200 +gen-gbe-ich9m: + ./blobtool gbe-ich9m.spec gbe-ich9m.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + +# Use this target to generate IFD for X200 +gen-ifd-x200: + ./blobtool ifd-x200.spec ifd-x200.set flashregion_0_fd.bin + +.PHONY: clean gen-gbe-ich9m gen-ifd-x200 + +clean: + rm -f *.lex.c *.tab.c *.tab.h *.o blobtool flashregion_0_fd.bin flashregion_3_gbe.bin diff --git a/util/blobtool/blobtool.l b/util/blobtool/blobtool.l new file mode 100644 index 0000000..43c2b15 --- /dev/null +++ b/util/blobtool/blobtool.l @@ -0,0 +1,145 @@ +/* + * blobtool - Compiler/Decompiler for data blobs with specs + * Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +%{ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include "blobtool.tab.h" + +extern struct blob binary; + +unsigned int parsehex (char *s) +{ + unsigned int i, nib, val = 0; + unsigned int nibs = strlen(s) - 2; + + for (i = 2; i < nibs + 2; i++) { + if (s[i] >= '0' && s[i] <= '9') { + nib = s[i] - '0'; + } else if (s[i] >= 'a' && s[i] <= 'f') { + nib = s[i] - 'a' + 10; + } else if (s[i] >= 'A' && s[i] <= 'F') { + nib = s[i] - 'A' + 10; + } else { + return 0; + } + val |= nib << (((nibs - 1) - (i - 2)) * 4); + } + return val; +} + +char* stripquotes (char *string) +{ + char *stripped; + unsigned int len = strlen(string); + if (len >= 2 && string[0] == '\"' && string[len-1] == '\"') { + stripped = (char *) malloc (len - 2 + 1); + snprintf (stripped, len - 2 + 1, "%s", string+1); + stripped[len-2] = '\0'; + return stripped; + } else { + return 0; + } +} + +%} + +%option noyywrap +%option nounput + +DIGIT1to9 [1-9] +DIGIT [0-9] +DIGITS {DIGIT}+ +INT {DIGIT}|{DIGIT1to9}{DIGITS}|-{DIGIT}|-{DIGIT1to9}{DIGITS} +FRAC [.]{DIGITS} +E [eE][+-]? +EXP {E}{DIGITS} +HEX_DIGIT [0-9a-fA-F] +HEX_DIGITS {HEX_DIGIT}+ +NUMBER {INT}|{INT}{FRAC}|{INT}{EXP}|{INT}{FRAC}{EXP} +UNICODECHAR \\u{HEX_DIGIT}{HEX_DIGIT}{HEX_DIGIT}{HEX_DIGIT} +ALPHA [a-zA-Z] +SPECIAL [()\[\]"'@_\-+:;/\\.,<> ] +VARCHAR {ALPHA}|{DIGIT}|{SPECIAL} +CHAR {VARCHAR}|{UNICODECHAR} +CHARS {CHAR}+ +QUOTE ["] +HEX_PREFIX [0][x] +HEX {HEX_PREFIX}{HEX_DIGITS} +STRING {QUOTE}{QUOTE}|{QUOTE}{CHARS}{QUOTE} +COMMENT [#]{CHARS}[\n]|[#]\n + +%% + +{STRING} { + yylval.str = stripquotes(yytext); + return name; +}; + +{NUMBER} { + yylval.u32 = atoi(yytext); + return val; +}; + +{HEX} { + yylval.u32 = parsehex(yytext); + return val; +}; + +\{ { + return '{'; +}; + +\} { + return '}'; +}; + +\[ { + return '['; +}; + +\] { + return ']'; +}; + +, { + return ','; +}; + +: { + return ':'; +}; + += { + return '='; +}; + +[ \t\n]+ /* ignore whitespace */; + +{COMMENT} /* ignore comments */ + +\% { + return '%'; +}; + +<<EOF>> { return eof; }; + +%% + +void set_input_string(char* in) { + yy_scan_string(in); +} + diff --git a/util/blobtool/blobtool.y b/util/blobtool/blobtool.y new file mode 100644 index 0000000..909102d --- /dev/null +++ b/util/blobtool/blobtool.y @@ -0,0 +1,537 @@ +/* + * blobtool - Compiler/Decompiler for data blobs with specs + * Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +%{ +#include <stdio.h> +#include <inttypes.h> +#include <stdlib.h> +#include <string.h> +//#define YYDEBUG 1 +int yylex (void); +void yyerror (char const *); + +struct field { + char *name; + unsigned int width; + unsigned int value; + struct field *next; +}; + +extern struct field *sym_table; +struct field *putsym (char const *, unsigned int); +struct field *getsym (char const *); + +struct field *sym_table; +struct field *sym_table_tail; + +FILE* fp; + +/* Bit array intermediary representation */ +struct blob { + unsigned int bloblen; + unsigned char *blb; + unsigned short checksum; + unsigned char *actualblob; + unsigned int lenactualblob; +}; + +#define VALID_BIT 0x80 +#define MAX_WIDTH 32 +#define CHECKSUM_SIZE 16 + +struct blob *binary; + +unsigned char* value_to_bits (unsigned int v, unsigned int w) +{ + unsigned int i; + unsigned char* bitarr; + + if (w > MAX_WIDTH) w = MAX_WIDTH; + bitarr = (unsigned char *) malloc (w * sizeof (unsigned char)); + memset (bitarr, 0, w); + + for (i = 0; i < w; i++) { + bitarr[i] = VALID_BIT | ((v & (1 << i)) >> i); + } + return bitarr; +} + +/* Store each bit of a bitfield in a new byte sequentially 0x80 or 0x81 */ +void append_field_to_blob (unsigned char b[], unsigned int w) +{ + unsigned int i, j; + binary->blb = (unsigned char *) realloc (binary->blb, binary->bloblen + w); + for (j = 0, i = binary->bloblen; i < binary->bloblen + w; i++, j++) { + binary->blb[i] = VALID_BIT | (b[j] & 1); + //fprintf (stderr, "blob[%d] = %d\n", i, binary->blb[i] & 1); + } + binary->bloblen += w; +} + +void set_bitfield(char *name, unsigned int value) +{ + unsigned long long i; + struct field *bf = getsym (name); + if (bf) { + bf->value = value & 0xffffffff; + i = (1 << bf->width) - 1; + if (bf->width > 8 * sizeof (unsigned int)) { + fprintf(stderr, "Overflow in bitfield, truncating bits to fit\n"); + bf->value = value & i; + } + //fprintf(stderr, "Setting `%s` = %d\n", bf->name, bf->value); + } else { + fprintf(stderr, "Can't find bitfield `%s` in spec\n", name); + } +} + +void set_bitfield_array(char *name, unsigned int n, unsigned int value) +{ + unsigned int i; + unsigned int len = strlen (name); + char *namen = (char *) malloc ((len + 9) * sizeof (char)); + for (i = 0; i < n; i++) { + snprintf (namen, len + 8, "%s%x", name, i); + set_bitfield (namen, value); + } + free(namen); +} + +void create_new_bitfield(char *name, unsigned int width) +{ + struct field *bf; + + if (!(bf = putsym (name, width))) return; + //fprintf(stderr, "Added bitfield `%s` : %d\n", bf->name, width); +} + +void create_new_bitfields(char *name, unsigned int n, unsigned int width) +{ + unsigned int i; + unsigned int len = strlen (name); + char *namen = (char *) malloc ((len + 9) * sizeof (char)); + for (i = 0; i < n; i++) { + snprintf (namen, len + 8, "%s%x", name, i); + create_new_bitfield (namen, width); + } + free(namen); +} + +struct field *putsym (char const *sym_name, unsigned int w) +{ + if (getsym(sym_name)) { + fprintf(stderr, "Cannot add duplicate named bitfield `%s`\n", sym_name); + return 0; + } + struct field *ptr = (struct field *) malloc (sizeof (struct field)); + ptr->name = (char *) malloc (strlen (sym_name) + 1); + strcpy (ptr->name, sym_name); + ptr->width = w; + ptr->value = 0; + ptr->next = (struct field *)0; + if (sym_table_tail) { + sym_table_tail->next = ptr; + } else { + sym_table = ptr; + } + sym_table_tail = ptr; + return ptr; +} + +struct field *getsym (char const *sym_name) +{ + struct field *ptr; + for (ptr = sym_table; ptr != (struct field *) 0; + ptr = (struct field *)ptr->next) { + if (strcmp (ptr->name, sym_name) == 0) + return ptr; + } + return 0; +} + +void dump_all_values (void) +{ + struct field *ptr; + for (ptr = sym_table; ptr != (struct field *) 0; + ptr = (struct field *)ptr->next) { + fprintf(stderr, "%s = %d (%d bits)\n", + ptr->name, + ptr->value, + ptr->width); + } +} + +void empty_field_table(void) +{ + struct field *ptr; + struct field *ptrnext; + + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptrnext) { + if (ptr) { + ptrnext = ptr->next; + free(ptr); + } else { + ptrnext = (struct field *) 0; + } + } + sym_table = 0; + sym_table_tail = 0; +} + +void create_binary_blob (void) +{ + if (binary && binary->blb) { + free(binary->blb); + free(binary); + } + binary = (struct blob *) malloc (sizeof (struct blob)); + binary->blb = (unsigned char *) malloc (sizeof (unsigned char)); + binary->bloblen = 0; + binary->blb[0] = VALID_BIT; +} + +void interpret_next_blob_value (struct field *f) +{ + int i; + unsigned int v = 0; + + if (binary->bloblen >= binary->lenactualblob * 8) { + f->value = 0; + return; + } + + for (i = 0; i < f->width; i++) { + v |= (binary->blb[binary->bloblen++] & 1) << i; + } + + f->value = v; +} + +/* {}%BIN -> {} */ +void generate_setter_bitfields(unsigned char *bin) +{ + unsigned int i; + struct field *ptr; + + /* Convert bytes to bit array */ + for (i = 0; i < binary->lenactualblob; i++) { + append_field_to_blob (value_to_bits(bin[i], 8), 8); + } + + /* Reset blob position to zero */ + binary->bloblen = 0; + + fprintf (fp, "# AUTOGENERATED SETTER BY BLOBTOOL\n{\n"); + + /* Traverse spec and output bitfield setters based on blob values */ + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + + interpret_next_blob_value(ptr); + fprintf (fp, "\t\"%s\" = 0x%x,\n", ptr->name, ptr->value); + } + fseek(fp, -2, SEEK_CUR); + fprintf (fp, "\n}\n"); +} + +void generate_binary_with_gbe_checksum(void) +{ + int i; + unsigned short checksum; + + /* traverse spec, push to blob and add up for checksum */ + struct field *ptr; + unsigned int uptochksum = 0; + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + if (strcmp (ptr->name, "checksum_gbe") == 0) { + /* Stop traversing because we hit checksum */ + ptr = ptr->next; + break; + } + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), + ptr->width); + uptochksum += ptr->width; + } + + /* deserialize bits of blob up to checksum */ + for (i = 0; i < uptochksum; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + + /* incremental 16 bit checksum */ + if ((i % 16) < 8) { + binary->checksum += byte; + } else { + binary->checksum += byte << 8; + } + } + + checksum = (0xbaba - binary->checksum) & 0xffff; + + /* Now write checksum */ + set_bitfield ("checksum_gbe", checksum); + + fprintf(fp, "%c", checksum & 0xff); + fprintf(fp, "%c", (checksum & 0xff00) >> 8); + + append_field_to_blob (value_to_bits(checksum, 16), 16); + + for (; ptr != (struct field *) 0; ptr = ptr->next) { + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), ptr->width); + } + + /* deserialize rest of blob past checksum */ + for (i = uptochksum + CHECKSUM_SIZE; i < binary->bloblen; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + } +} + +/* {}{} -> BIN */ +void generate_binary(void) +{ + unsigned int i; + struct field *ptr; + + if (binary->bloblen % 8) { + fprintf (stderr, "ERROR: Spec must be multiple of 8 bits wide\n"); + exit (1); + } + + if (getsym ("checksum_gbe")) { + generate_binary_with_gbe_checksum(); + return; + } + + /* traverse spec, push to blob */ + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), + ptr->width); + } + + /* deserialize bits of blob */ + for (i = 0; i < binary->bloblen; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + } +} + +%} + +%union +{ + char *str; + unsigned int u32; + unsigned int *u32array; + unsigned char u8; + unsigned char *u8array; +} + +%token <str> name +%token <u32> val +%token <u32array> vals +%token <u8> hexbyte +%token <u8array> binblob +%token <u8> eof + +%left '%' +%left '{' '}' +%left ',' +%left ':' +%left '=' + +%% + +input: + /* empty */ +| input spec setter eof { empty_field_table(); YYACCEPT;} +| input spec blob { fprintf (stderr, "Parsed all bytes\n"); + empty_field_table(); YYACCEPT;} +; + +blob: + '%' eof { generate_setter_bitfields(binary->actualblob); } +; + +spec: + '{' '}' { fprintf (stderr, "No spec\n"); } +| '{' specmembers '}' { fprintf (stderr, "Parsed all spec\n"); + create_binary_blob(); } +; + +specmembers: + specpair +| specpair ',' specmembers +; + +specpair: + name ':' val { create_new_bitfield($1, $3); } +| name '[' val ']' ':' val { create_new_bitfields($1, $3, $6); } +; + +setter: + '{' '}' { fprintf (stderr, "No values\n"); } +| '{' valuemembers '}' { fprintf (stderr, "Parsed all values\n"); + generate_binary(); } +; + +valuemembers: + setpair +| setpair ',' valuemembers +; + +setpair: + name '=' val { set_bitfield($1, $3); } +| name '[' val ']' '=' val { set_bitfield_array($1, $3, $6); } +; + +%% + +/* Called by yyparse on error. */ +void yyerror (char const *s) +{ + fprintf (stderr, "yyerror: %s\n", s); +} + +/* Declarations */ +void set_input_string(char* in); + +/* This function parses a string */ +int parse_string(unsigned char* in) { + set_input_string ((char *)in); + return yyparse (); +} + +int main (int argc, char *argv[]) +{ + unsigned int lenspec, lensetter; + unsigned char *parsestring; + unsigned char c; + unsigned int pos = 0; + int ret = 0; + +#if YYDEBUG == 1 + yydebug = 1; +#endif + create_binary_blob(); + binary->lenactualblob = 0; + + if (argc == 4 && strcmp(argv[1], "-d") != 0) { + /* Compile mode */ + + /* Load Spec */ + fp = fopen(argv[1], "r"); + fseek(fp, 0, SEEK_END); + lenspec = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) malloc (lenspec); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fread(parsestring, 1, lenspec, fp); + fclose(fp); + + /* Load Setter */ + fp = fopen(argv[2], "r"); + fseek(fp, 0, SEEK_END); + lensetter = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) realloc (parsestring, + lenspec + lensetter); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fread(parsestring + lenspec, 1, lensetter, fp); + fclose(fp); + + /* Open output and parse string - output to fp */ + fp = fopen(argv[3], "wb"); + ret = parse_string(parsestring); + free(parsestring); + } else if (argc == 5 && strcmp (argv[1], "-d") == 0) { + /* Decompile mode */ + + /* Load Spec */ + fp = fopen(argv[2], "r"); + fseek(fp, 0, SEEK_END); + lenspec = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) malloc (lenspec + 1); + fread(parsestring, 1, lenspec, fp); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fclose(fp); + + /* Add binary read trigger token */ + parsestring[lenspec] = '%'; + + /* Load Actual Binary */ + fp = fopen(argv[3], "rb"); + fseek(fp, 0, SEEK_END); + binary->lenactualblob = ftell(fp); + fseek(fp, 0, SEEK_SET); + binary->actualblob = (unsigned char *) malloc (binary->lenactualblob); + if (!binary->actualblob) { + printf("Out of memory\n"); + exit(1); + } + fread(binary->actualblob, 1, binary->lenactualblob, fp); + fclose(fp); + + /* Open output and parse - output to fp */ + fp = fopen(argv[4], "w"); + ret = parse_string(parsestring); + free(parsestring); + free(binary->actualblob); + fclose(fp); + } else { + printf("Usage: Compile mode\n\n"); + printf(" blobtool spec setter binaryoutput\n"); + printf(" (file) (file) (file)\n"); + printf(" OR : Decompile mode\n\n"); + printf(" blobtool -d spec binary setteroutput\n"); + } + return ret; +} diff --git a/util/blobtool/gbe-ich9m.set b/util/blobtool/gbe-ich9m.set new file mode 100644 index 0000000..01f85ab --- /dev/null +++ b/util/blobtool/gbe-ich9m.set @@ -0,0 +1,88 @@ +# +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# GbE values for ICH9M +{ + # Hardcoded chipset values + "reserved04" = 0xffff, + "version05" = 0x1083, + "reserved06" = 0xffff, + "reserved07" = 0xffff, + "pbalow" = 0xffff, + "pbahigh" = 0xffff, + "pci_loadvid" = 1, + "pci_loadssid" = 1, + "pci_pmen" = 1, + "pci_auxpwr" = 1, + "pci_reserved4" = 1, + "sh_phy_enpwrdown" = 1, + "sh_reserved1" = 0x5, + "sh_reserved3" = 1, + "sh_sign" = 0x2, + "cw1_extcfgptr" = 0x020, + "cw1_oemload" = 1, + "cw1_reserved1" = 1, + "cw2_extphylen" = 0x05, + "l1_reserved2" = 1, + "l1_reserved4" = 1, + "l1_lplu_non_d0a" = 1, + "l1_gbedis_non_d0a" = 1, + "reserved19" = 0x2b40, + "reserved1a" = 0x0043, + "reserved1c" = 0x10f5, + "reserved1d" = 0xbaad, + "_82567lm" = 0x10f5, + "_82567lf" = 0x10bf, + "reserved20" = 0xbaad, + "_82567v" = 0x10cb, + "reserved22_0" = 0xbaad, + "reserved22_1" = 0xbaad, + + # Hardcoded PXE setup (disabled) + "pxe30_defbootsel" = 0x3, + "pxe30_ctrlsprompt" = 0x3, + "pxe30_pxeabsent" = 1, + "pxe31_disablemenu" = 1, + "pxe31_disabletitle" = 1, + "pxe31_signature" = 1, + "pxe32_buildnum" = 0x18, + "pxe32_minorversion" = 0x3, + "pxe32_majorversion" = 0x1, + "pxe33_basecodeabsent" = 1, + "pxe33_undipresent" = 1, + "pxe33_reserved1" = 1, + "pxe33_signature" = 1, + "pxe_padding"[11] = 0xffff, + + # GbE power settings + "lanpwr_d3pwr" = 1, + "lanpwr_d0pwr" = 13, + + # GbE LED modes + "l1_led1mode" = 0xb, + "l1_led1blinks" = 1, + "l02_led0mode" = 0x2, + "l02_led2mode" = 0x1, + + # Padding 0xf80 bytes + "padding"[0xf80] = 0xff, + + # TODO: make command line switch for these + + # Configurable PCI IDs + "ssdid" = 0x20ee, + "ssvid" = 0x17aa, + "did" = 0x10f5, + "vid" = 0x8086 +} diff --git a/util/blobtool/gbe-ich9m.spec b/util/blobtool/gbe-ich9m.spec new file mode 100644 index 0000000..45eed0e --- /dev/null +++ b/util/blobtool/gbe-ich9m.spec @@ -0,0 +1,142 @@ +# +# Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> +# Leah Rowe <info(a)minifree.org> +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Datasheets: +# +# http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-… +# https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-… + +# The datasheet says that this spec covers the following pci ids: +# 8086:10F5 - Intel 82567LM gigabit ethernet controller +# 8086:10BF - Intel 82567LF gigabit ethernet controller +# 8086:10CB - Intel 82567V gigabit ethernet controller + +# GbE SPEC for ICH9M (82567LM/LF/V) +{ + "macaddress"[6] : 8, + "ba_reserved1_0" : 8, + "ba_reserved1_1" : 3, + "ba_ibootagent" : 1, + "ba_reserved2" : 4, + "reserved04" : 16, + "version05" : 16, + "reserved06" : 16, + "reserved07" : 16, + "pbalow" : 16, + "pbahigh" : 16, + "pci_loadvid" : 1, + "pci_loadssid" : 1, + "pci_reserved1" : 1, + "pci_reserved2" : 3, + "pci_pmen" : 1, + "pci_auxpwr" : 1, + "pci_reserved3" : 4, + "pci_reserved4" : 4, + "ssdid" : 16, + "ssvid" : 16, + "did" : 16, + "vid" : 16, + "devrevid" : 16, + "lanpwr_d3pwr" : 5, + "lanpwr_reserved" : 3, + "lanpwr_d0pwr" : 8, + "reserved11" : 16, + "reserved12" : 16, + "sh_reserved1" : 3, + "sh_force_halfduplex" : 1, + "sh_force_lowspeed" : 1, + "sh_reserved2_0" : 3, + "sh_reserved2_1" : 1, + "sh_phy_enpwrdown" : 1, + "sh_reserved3" : 1, + "sh_reserved4" : 3, + "sh_sign" : 2, + "cw1_extcfgptr" : 12, + "cw1_oemload" : 1, + "cw1_reserved1" : 1, + "cw1_reserved2" : 1, + "cw1_reserved3" : 1, + "cw2_reserved" : 8, + "cw2_extphylen" : 8, + "extcfg16" : 16, + "l1_led1mode" : 4, + "l1_reserved1" : 1, + "l1_led1fastblink" : 1, + "l1_led1invert" : 1, + "l1_led1blinks" : 1, + "l1_reserved2" : 1, + "l1_lplu_all" : 1, + "l1_lplu_non_d0a" : 1, + "l1_gbedis_non_d0a" : 1, + "l1_reserved3" : 2, + "l1_gbedis" : 1, + "l1_reserved4" : 1, + "l02_led0mode" : 4, + "l02_reserved1" : 1, + "l02_led0fastblink" : 1, + "l02_led0invert" : 1, + "l02_led0blinks" : 1, + "l02_led2mode" : 4, + "l02_reserved2" : 1, + "l02_led2fastblink" : 1, + "l02_led2invert" : 1, + "l02_led2blinks" : 1, + "reserved19" : 16, + "reserved1a" : 16, + "reserved1b" : 16, + "reserved1c" : 16, + "reserved1d" : 16, + "_82567lm" : 16, + "_82567lf" : 16, + "reserved20" : 16, + "_82567v" : 16, + "reserved22_"[14] : 16, + "pxe30_protocolsel" : 2, + "pxe30_reserved1" : 1, + "pxe30_defbootsel" : 2, + "pxe30_reserved2" : 1, + "pxe30_ctrlsprompt" : 2, + "pxe30_dispsetup" : 1, + "pxe30_reserved3" : 1, + "pxe30_forcespeed" : 2, + "pxe30_forcefullduplex" : 1, + "pxe30_reserved4" : 1, + "pxe30_efipresent" : 1, + "pxe30_pxeabsent" : 1, + "pxe31_disablemenu" : 1, + "pxe31_disabletitle" : 1, + "pxe31_disableprotsel" : 1, + "pxe31_disablebootorder": 1, + "pxe31_disablelegacywak": 1, + "pxe31_disableflash_pro": 1, + "pxe31_reserved1" : 2, + "pxe31_ibootagentmode" : 3, + "pxe31_reserved2" : 3, + "pxe31_signature" : 2, + "pxe32_buildnum" : 8, + "pxe32_minorversion" : 4, + "pxe32_majorversion" : 4, + "pxe33_basecodeabsent" : 1, + "pxe33_undipresent" : 1, + "pxe33_reserved1" : 1, + "pxe33_efiundipresent" : 1, + "pxe33_reserved2_0" : 4, + "pxe33_reserved2_1" : 6, + "pxe33_signature" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "padding"[0xf80] : 8 +} diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set new file mode 100644 index 0000000..2894562 --- /dev/null +++ b/util/blobtool/ifd-x200.set @@ -0,0 +1,167 @@ +# +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# X200 Liberated Flash Descriptor +# Layout: +# 0x0000 - 0x1000 : IFD +# 0x1000 - 0x3000 : GbE x2 +# 0x3000 - ROMSIZE : BIOS +{ + "fd_signature" = 0xff0a55a, + + "flmap0_fcba" = 0x1, + "flmap0_nc" = 0x0, + "flmap0_reserved0" = 0x0, + "flmap0_frba" = 0x4, + "flmap0_nr" = 0x2, + "flmap0_reserved1" = 0x0, + "flmap1_fmba" = 0x6, + "flmap1_nm" = 0x2, + "flmap1_reserved" = 0x0, + "flmap1_fisba" = 0x10, + "flmap1_isl" = 0x2, + "flmap2_fmsba" = 0x20, + "flmap2_msl" = 0x1, + "flmap2_reserved" = 0x0, + + "flcomp_density1" = 0x4, + "flcomp_density2" = 0x2, + "flcomp_reserved0" = 0x0, + "flcomp_reserved1" = 0x0, + "flcomp_reserved2" = 0x0, + "flcomp_readclockfreq" = 0x0, + "flcomp_fastreadsupp" = 0x1, + "flcomp_fastreadfreq" = 0x1, + "flcomp_w_eraseclkfreq" = 0x0, + "flcomp_r_statclkfreq" = 0x0, + "flcomp_reserved3" = 0x0, + "flill" = 0x0, + "flbp" = 0x0, + "comp_padding"[0x24] = 0xff, + + "flreg0_base" = 0x0, + "flreg0_reserved0" = 0x0, + "flreg0_limit" = 0x0, + "flreg0_reserved1" = 0x0, + "flreg1_base" = 0x3, + "flreg1_reserved0" = 0x0, + "flreg1_limit" = 0x7ff, + "flreg1_reserved1" = 0x0, + "flreg2_base" = 0x1fff, + "flreg2_reserved0" = 0x0, + "flreg2_limit" = 0x0, + "flreg2_reserved1" = 0x0, + "flreg3_base" = 0x1, + "flreg3_reserved0" = 0x0, + "flreg3_limit" = 0x2, + "flreg3_reserved1" = 0x0, + "flreg4_base" = 0x1fff, + "flreg4_reserved0" = 0x0, + "flreg4_limit" = 0x0, + "flreg4_reserved1" = 0x0, + "flreg_padding"[12] = 0xff, + + "flmstr1_requesterid" = 0x0, + "flmstr1_r_fd" = 0x1, + "flmstr1_r_bios" = 0x1, + "flmstr1_r_me" = 0x1, + "flmstr1_r_gbe" = 0x1, + "flmstr1_r_pd" = 0x1, + "flmstr1_r_reserved" = 0x0, + "flmstr1_w_fd" = 0x1, + "flmstr1_w_bios" = 0x1, + "flmstr1_w_me" = 0x1, + "flmstr1_w_gbe" = 0x1, + "flmstr1_w_pd" = 0x1, + "flmstr1_w_reserved" = 0x0, + "flmstr2_requesterid" = 0x0, + "flmstr2_r_fd" = 0x0, + "flmstr2_r_bios" = 0x0, + "flmstr2_r_me" = 0x0, + "flmstr2_r_gbe" = 0x0, + "flmstr2_r_pd" = 0x0, + "flmstr2_r_reserved" = 0x0, + "flmstr2_w_fd" = 0x0, + "flmstr2_w_bios" = 0x0, + "flmstr2_w_me" = 0x0, + "flmstr2_w_gbe" = 0x0, + "flmstr2_w_pd" = 0x0, + "flmstr2_w_reserved" = 0x0, + "flmstr3_requesterid" = 0x218, + "flmstr3_r_fd" = 0x0, + "flmstr3_r_bios" = 0x0, + "flmstr3_r_me" = 0x0, + "flmstr3_r_gbe" = 0x1, + "flmstr3_r_pd" = 0x0, + "flmstr3_r_reserved" = 0x0, + "flmstr3_w_fd" = 0x0, + "flmstr3_w_bios" = 0x0, + "flmstr3_w_me" = 0x0, + "flmstr3_w_gbe" = 0x1, + "flmstr3_w_pd" = 0x0, + "flmstr3_w_reserved" = 0x0, + "flmstr_padding"[0x94] = 0xff, + + "ich0_medisable" = 0x1, + "ich0_reserved0" = 0x4, + "ich0_tcomode" = 0x1, + "ich0_mesmbusaddr" = 0x64, + "ich0_bmcmode" = 0x0, + "ich0_trippointsel" = 0x0, + "ich0_reserved1" = 0x0, + "ich0_integratedgbe" = 0x1, + "ich0_lanphy" = 0x1, + "ich0_reserved2" = 0x0, + "ich0_dmireqiddisable" = 0x0, + "ich0_me2smbusaddr" = 0x0, + "ich1_dynclk_nmlink" = 0x1, + "ich1_dynclk_smlink" = 0x1, + "ich1_dynclk_mesmbus" = 0x1, + "ich1_dynclk_sst" = 0x1, + "ich1_reserved0" = 0x0, + "ich1_nmlink_npostreqs" = 0x1, + "ich1_reserved1" = 0x0, + "ich1_reserved2" = 0x0, + "ichstrap_padding"[0xf8] = 0xff, + "mch0_medisable" = 0x1, + "mch0_mebootfromflash" = 0x0, + "mch0_tpmdisable" = 0x1, + "mch0_reserved0" = 0x7, + "mch0_spifingerprinton" = 0x1, + "mch0_mealtdisable" = 0x0, + "mch0_reserved1" = 0xff, + "mch0_reserved2" = 0xffff, + "mchstrap_padding"[0xcdc] = 0xff, + + "mevscc_jid0" = 0x1720c2, + "mevscc_vscc0" = 0x20052005, + "mevscc_jid1" = 0x1730ef, + "mevscc_vscc1" = 0x20052005, + "mevscc_jid2" = 0x481f, + "mevscc_vscc2" = 0x20152015, + "mevscc_padding"[4] = 0xff, + "mevscc_tablebase" = 0xee, + "mevscc_tablelength" = 0x6, + "mevscc_reserved" = 0x0, + + "oem_magic0" = 0x4c, + "oem_magic1" = 0x49, + "oem_magic2" = 0x42, + "oem_magic3" = 0x45, + "oem_magic4" = 0x52, + "oem_magic5" = 0x41, + "oem_magic6" = 0x54, + "oem_magic7" = 0x45, + "oem_padding"[0xf8] = 0xff +} diff --git a/util/blobtool/ifd-x200.spec b/util/blobtool/ifd-x200.spec new file mode 100644 index 0000000..0cdbb9d --- /dev/null +++ b/util/blobtool/ifd-x200.spec @@ -0,0 +1,187 @@ +# +# Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> +# Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Info on flash descriptor (page 845 onwards): +# +# http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datash… + +# Flash Descriptor SPEC for GM45/ICH9M +{ + # Signature for descriptor mode + "fd_signature" : 32, + + # Flash map registers + "flmap0_fcba" : 8, + "flmap0_nc" : 2, + "flmap0_reserved0" : 6, + "flmap0_frba" : 8, + "flmap0_nr" : 3, + "flmap0_reserved1" : 5, + "flmap1_fmba" : 8, + "flmap1_nm" : 3, + "flmap1_reserved" : 5, + "flmap1_fisba" : 8, + "flmap1_isl" : 8, + "flmap2_fmsba" : 8, + "flmap2_msl" : 8, + "flmap2_reserved" : 16, + + # Component section + "flcomp_density1" : 3, + "flcomp_density2" : 3, + "flcomp_reserved0" : 2, + "flcomp_reserved1" : 8, + "flcomp_reserved2" : 1, + "flcomp_readclockfreq" : 3, + "flcomp_fastreadsupp" : 1, + "flcomp_fastreadfreq" : 3, + "flcomp_w_eraseclkfreq" : 3, + "flcomp_r_statclkfreq" : 3, + "flcomp_reserved3" : 2, + "flill" : 32, + "flbp" : 32, + "comp_padding"[36] : 8, + + # Region section + "flreg0_base" : 13, + "flreg0_reserved0" : 3, + "flreg0_limit" : 13, + "flreg0_reserved1" : 3, + "flreg1_base" : 13, + "flreg1_reserved0" : 3, + "flreg1_limit" : 13, + "flreg1_reserved1" : 3, + "flreg2_base" : 13, + "flreg2_reserved0" : 3, + "flreg2_limit" : 13, + "flreg2_reserved1" : 3, + "flreg3_base" : 13, + "flreg3_reserved0" : 3, + "flreg3_limit" : 13, + "flreg3_reserved1" : 3, + "flreg4_base" : 13, + "flreg4_reserved0" : 3, + "flreg4_limit" : 13, + "flreg4_reserved1" : 3, + "flreg_padding"[12] : 8, + + # Master access section + + # 1: Host CPU/BIOS + "flmstr1_requesterid" : 16, + "flmstr1_r_fd" : 1, + "flmstr1_r_bios" : 1, + "flmstr1_r_me" : 1, + "flmstr1_r_gbe" : 1, + "flmstr1_r_pd" : 1, + "flmstr1_r_reserved" : 3, + "flmstr1_w_fd" : 1, + "flmstr1_w_bios" : 1, + "flmstr1_w_me" : 1, + "flmstr1_w_gbe" : 1, + "flmstr1_w_pd" : 1, + "flmstr1_w_reserved" : 3, + + # 2: ME + "flmstr2_requesterid" : 16, + "flmstr2_r_fd" : 1, + "flmstr2_r_bios" : 1, + "flmstr2_r_me" : 1, + "flmstr2_r_gbe" : 1, + "flmstr2_r_pd" : 1, + "flmstr2_r_reserved" : 3, + "flmstr2_w_fd" : 1, + "flmstr2_w_bios" : 1, + "flmstr2_w_me" : 1, + "flmstr2_w_gbe" : 1, + "flmstr2_w_pd" : 1, + "flmstr2_w_reserved" : 3, + + # 3: GbE + "flmstr3_requesterid" : 16, + "flmstr3_r_fd" : 1, + "flmstr3_r_bios" : 1, + "flmstr3_r_me" : 1, + "flmstr3_r_gbe" : 1, + "flmstr3_r_pd" : 1, + "flmstr3_r_reserved" : 3, + "flmstr3_w_fd" : 1, + "flmstr3_w_bios" : 1, + "flmstr3_w_me" : 1, + "flmstr3_w_gbe" : 1, + "flmstr3_w_pd" : 1, + "flmstr3_w_reserved" : 3, + + "flmstr_padding"[148] : 8, + + # ICHSTRAP0 + "ich0_medisable" : 1, + "ich0_reserved0" : 6, + "ich0_tcomode" : 1, + "ich0_mesmbusaddr" : 7, + "ich0_bmcmode" : 1, + "ich0_trippointsel" : 1, + "ich0_reserved1" : 2, + "ich0_integratedgbe" : 1, + "ich0_lanphy" : 1, + "ich0_reserved2" : 3, + "ich0_dmireqiddisable" : 1, + "ich0_me2smbusaddr" : 7, + + # ICHSTRAP1 + "ich1_dynclk_nmlink" : 1, + "ich1_dynclk_smlink" : 1, + "ich1_dynclk_mesmbus" : 1, + "ich1_dynclk_sst" : 1, + "ich1_reserved0" : 4, + "ich1_nmlink_npostreqs" : 1, + "ich1_reserved1" : 7, + "ich1_reserved2" : 16, + + "ichstrap_padding"[248] : 8, + + # MCHSTRAP0 + "mch0_medisable" : 1, + "mch0_mebootfromflash" : 1, + "mch0_tpmdisable" : 1, + "mch0_reserved0" : 3, + "mch0_spifingerprinton" : 1, + # Alternate disable - allows ME to perform chipset + # init functions but disables FW apps such as AMT + "mch0_mealtdisable" : 1, + "mch0_reserved1" : 8, + "mch0_reserved2" : 16, + + "mchstrap_padding"[3292]: 8, + + # ME VSCC Table + "mevscc_jid0" : 32, + "mevscc_vscc0" : 32, + "mevscc_jid1" : 32, + "mevscc_vscc1" : 32, + "mevscc_jid2" : 32, + "mevscc_vscc2" : 32, + "mevscc_padding"[4] : 8, + + # Descriptor Map 2 Record + "mevscc_tablebase" : 8, + "mevscc_tablelength" : 8, + "mevscc_reserved" : 16, + + # OEM section + "oem_magic"[8] : 8, + "oem_padding"[248] : 8 +} diff --git a/util/blobtool/it8718f-ec.spec b/util/blobtool/it8718f-ec.spec new file mode 100644 index 0000000..7fa325f --- /dev/null +++ b/util/blobtool/it8718f-ec.spec @@ -0,0 +1,368 @@ +# ITE IT8718F SuperIO EC registers +{ + # 00 Configuration register + "conf00_start" : 1, + "conf00_smien" : 1, + "conf00_irqen" : 1, + "conf00_irqclr" : 1, + "conf00_ro_one" : 1, + "conf00_copen" : 1, + "conf00_vbat" : 1, + "conf00_initreset" : 1, + + # 01 Interrupt Status register 1 + "irq1_maxfantac1" : 1, + "irq1_maxfantac2" : 1, + "irq1_maxfantac3" : 1, + "irq1_maxfantac4" : 1, + "irq1_copen" : 1, + "irq1_reserved0" : 1, + "irq1_maxfantac5" : 1, + "irq1_reserved1" : 1, + + # 02 Interrupt Status register 2 + "irq2_limit_vin"[8] : 1, + + # 03 Interrupt Status register 3 + "irq3_limit_temp1" : 1, + "irq3_limit_temp2" : 1, + "irq3_limit_temp3" : 1, + "irq3_reserved" : 5, + + # 04 SMI Mask register 1 + "smi1_dis_fantac1" : 1, + "smi1_dis_fantac2" : 1, + "smi1_dis_fantac3" : 1, + "smi1_dis_fantac4" : 1, + "smi1_dis_copen" : 1, + "smi1_reserved0" : 1, + "smi1_dis_fantac5" : 1, + "smi1_reserved1" : 1, + + # 05 SMI Mask register 2 + "smi2_dis_vin"[8] : 1, + + # 06 SMI Mask register 3 + "smi3_dis_temp1" : 1, + "smi3_dis_temp2" : 1, + "smi3_dis_temp3" : 1, + "smi3_reserved" : 5, + + # 07 Interrupt Mask register 1 + "irqmask1_fantac1" : 1, + "irqmask1_fantac2" : 1, + "irqmask1_fantac3" : 1, + "irqmask1_fantac4" : 1, + "irqmask1_copen" : 1, + "irqmask1_reserved0" : 1, + "irqmask1_fantac5" : 1, + "irqmask1_reserved1" : 1, + + # 08 Interrupt Mask register 2 + "irqmask2_vin"[8] : 1, + + # 09 Interrupt Mask register 3 + "irqmask3_temp1" : 1, + "irqmask3_temp2" : 1, + "irqmask3_temp3" : 1, + "irqmask3_reserved" : 4, + "irqmask3_extsensor" : 1, + + # 0a Interface Selection register + "iface_reserved" : 4, + "iface_extsensor_select": 3, + "iface_pseudo_eoc" : 1, + + # 0b Fan PWM smoothing step selection reg + "fanpwm_reserved" : 6, + "fanpwm_smoothing_step" : 2, + + # 0c Fan Tachometer 16 bit enable register + "fantach16_en_tac1" : 1, + "fantach16_en_tac2" : 1, + "fantach16_en_tac3" : 1, + "fantach16_tmpin1_enh" : 1, + "fantach16_en_tac4" : 1, + "fantach16_en_tac5" : 1, + "fantach16_tmpin2_enh" : 1, + "fantach16_tmpin3_enh" : 1, + + # 0d-0f Fan Tachmometer read registers + "fantach_lo_counts1" : 8, + "fantach_lo_counts2" : 8, + "fantach_lo_counts3" : 8, + + # 10-12 Fan Tachometer limit registers + "fantach_lo_limit1" : 8, + "fantach_lo_limit2" : 8, + "fantach_lo_limit3" : 8, + + # 13 Fan controller main control register + "fanctlmain_mode1" : 1, + "fanctlmain_mode2" : 1, + "fanctlmain_mode3" : 1, + "fanctlmain_reserved0" : 1, + "fanctlmain_en_tac1" : 1, + "fanctlmain_en_tac2" : 1, + "fanctlmain_en_tac3" : 1, + "fanctlmain_reserved1" : 1, + + # 14 FAN_CTL control register + "fanctl_enable1" : 1, + "fanctl_enable2" : 1, + "fanctl_enable3" : 1, + "fanctl_minduty_sel" : 1, + # 000: 48Mhz (PWM Frequency 375Khz) + # 001: 24Mhz (PWM Frequency 187.5Khz) + # 010: 12Mhz (PWM Frequency 93.75Khz) + # 011: 8Mhz (PWM Frequency 62.5Khz) + # 100: 6Mhz (PWM Frequency 46.875Khz) + # 101: 3Mhz (PWM Frequency 23.43Khz) + # 110: 1.5Mhz (PWM Frequency 11.7Khz) + # 111: 0.75Mhz (PWM Frequency 5.86Khz) + "fanctl_pwm_base_clock" : 3, + "fanctl_allpolarity" : 1, + + # 15 FAN_CTL1 PWM control register + "fanctl1_tmpin_sel" : 2, + "fanctl1_steps" : 5, + "fanctl1_pwm_mode" : 1, + + # 16 FAN_CTL2 PWM control register + "fanctl2_tmpin_sel" : 2, + "fanctl2_steps" : 5, + "fanctl2_pwm_mode" : 1, + + # 17 FAN_CTL3 PWM control register + "fanctl3_tmpin_sel" : 2, + "fanctl3_steps" : 5, + "fanctl3_pwm_mode" : 1, + + # 18-1a Fan Tachometer extended read registers + "fantach_hi_counts1" : 8, + "fantach_hi_counts2" : 8, + "fantach_hi_counts3" : 8, + + # 1b-1d Fan Tachometer extended limit registers + "fantach_hi_limit1" : 8, + "fantach_hi_limit2" : 8, + "fantach_hi_limit3" : 8, + + "reserved1e" : 8, + "reserved1f" : 8, + + + # 20-27 Reading registers + "vin"[8] : 8, + + "vbat" : 8, + "tmpin1" : 8, + "tmpin2" : 8, + "tmpin3" : 8, + "reserved2c" : 8, + "reserved2d" : 8, + "reserved2e" : 8, + "reserved2f" : 8, + "limit_hi_vin0" : 8, + "limit_lo_vin0" : 8, + "limit_hi_vin1" : 8, + "limit_lo_vin1" : 8, + "limit_hi_vin2" : 8, + "limit_lo_vin2" : 8, + "limit_hi_vin3" : 8, + "limit_lo_vin3" : 8, + "limit_hi_vin4" : 8, + "limit_lo_vin4" : 8, + "limit_hi_vin5" : 8, + "limit_lo_vin5" : 8, + "limit_hi_vin6" : 8, + "limit_lo_vin6" : 8, + "limit_hi_vin7" : 8, + "limit_lo_vin7" : 8, + "limit_hi_tmpin1" : 8, + "limit_lo_tmpin1" : 8, + "limit_hi_tmpin2" : 8, + "limit_lo_tmpin2" : 8, + "limit_hi_tmpin3" : 8, + "limit_lo_tmpin3" : 8, + + "reserved46" : 8, + "reserved47" : 8, + "reserved48" : 8, + "reserved49" : 8, + "reserved4a" : 8, + "reserved4b" : 8, + "reserved4c" : 8, + "reserved4d" : 8, + "reserved4e" : 8, + "reserved4f" : 8, + + # 50 ADC Voltage channel enable register + "adc_scan_enable_vin"[8]: 1, + + # 51 ADC Temperature channel enable register + "therm_diode_tmpin1" : 1, + "therm_diode_tmpin2" : 1, + "therm_diode_tmpin3" : 1, + # Mututally exclusive settings + "therm_resistor_tmpin1" : 1, + "therm_resistor_tmpin2" : 1, + "therm_resistor_tmpin3" : 1, + "therm_reserved" : 2, + + "therm_limit_tmpin1" : 8, + "therm_limit_tmpin2" : 8, + "therm_limit_tmpin3" : 8, + + # 55 Temperature extra channel enable reg + "therm_resistor_vin4" : 1, + "therm_resistor_vin5" : 1, + "therm_resistor_vin6" : 1, + "adc_fanctl2_pwm_duty" : 1, + # 000: 48Mhz (PWM Frequency 375Khz) + # 001: 24Mhz (PWM Frequency 187.5Khz) + # 010: 12Mhz (PWM Frequency 93.75Khz) + # 011: 8Mhz (PWM Frequency 62.5Khz) + # 100: 6Mhz (PWM Frequency 46.875Khz) + # 101: 3Mhz (PWM Frequency 23.43Khz) + # 110: 1.5Mhz (PWM Frequency 11.7Khz) + # 111: 0.75Mhz (PWM Frequency 5.86Khz) + "adc_fanctl2_pwm_bclk" : 3, + "adc_tmpin3_ext_select" : 1, + + "thermal_zero_diode1" : 8, + "thermal_zero_diode2" : 8, + "ite_vendor_id" : 8, + "thermal_zero_diode3" : 8, + "reserved5a" : 8, + "ite_code_id" : 8, + + "beep_fantac" : 1, + "beep_vin" : 1, + "beep_tmpin" : 1, + "beep_reserved" : 1, + # ADC clock select + # 000: 500Khz (Default) + # 001: 250Khz + # 010: 125K + # 011: 62.5Khz + # 100: 31.25Khz + # 101: 24Mhz + # 110: 1Mhz + # 111: 2Mhz + "adc_clock_select" : 3, + "thermal_zero_adj_en" : 1, + + "beep_fan_freq_div" : 4, + "beep_fan_tone_div" : 4, + "beep_volt_freq_div" : 4, + "beep_volt_tone_div" : 4, + "beep_temp_freq_div" : 4, + "beep_temp_tone_div" : 4, + + # 60 SmartGuardian registers + "sguard1_temp_lim_off" : 8, + "sguard1_temp_lim_fan" : 8, + "reserved62" : 8, + "sguard1_pwm_start" : 7, + "sguard1_pwm_slope6" : 1, + "sguard1_pwm_slope05" : 6, + "sguard1_pwm_reserved" : 1, + "sguard1_fan_smooth_en" : 1, + "sguard1_temp_interval" : 5, + "sguard1_temp_reserved" : 2, + "sguard1_temp_pwm_lin" : 1, + "reserved66" : 8, + "reserved67" : 8, + "sguard2_temp_lim_off" : 8, + "sguard2_temp_lim_fan" : 8, + "reserved6a" : 8, + "sguard2_pwm_start" : 7, + "sguard2_pwm_slope6" : 1, + "sguard2_pwm_slope05" : 6, + "sguard2_pwm_reserved" : 1, + "sguard2_fan_smooth_en" : 1, + "sguard2_temp_interval" : 5, + "sguard2_temp_reserved" : 2, + "sguard2_temp_pwm_lin" : 1, + "reserved6e" : 8, + "reserved6f" : 8, + "sguard3_temp_lim_off" : 8, + "sguard3_temp_lim_fan" : 8, + "reserved72" : 8, + "sguard3_pwm_start" : 7, + "sguard3_pwm_slope6" : 1, + "sguard3_pwm_slope05" : 6, + "sguard3_pwm_reserved" : 1, + "sguard3_fan_smooth_en" : 1, + "sguard3_temp_interval" : 5, + "sguard3_temp_reserved" : 2, + "sguard3_temp_pwm_lin" : 1, + "reserved76" : 8, + "reserved77" : 8, + "reserved78" : 8, + "reserved79" : 8, + "reserved7a" : 8, + "reserved7b" : 8, + "reserved7c" : 8, + "reserved7d" : 8, + "reserved7e" : 8, + "reserved7f" : 8, + + # 80 Fan Tachometer 4-5 read registers + "fantach_lo_counts4" : 8, + "fantach_hi_counts4" : 8, + "fantach_lo_counts5" : 8, + "fantach_hi_counts5" : 8, + "fantach_lo_limit4" : 8, + "fantach_hi_limit4" : 8, + "fantach_lo_limit5" : 8, + "fantach_hi_limit5" : 8, + + # 88 External temperature sensor host status + "ext_host_busy" : 1, + "ext_host_fnsh" : 1, + "ext_host_r_fcs_error" : 1, + "ext_host_w_fcs_error" : 1, + "ext_host_peci_highz" : 1, + "ext_host_sst_slave" : 1, + "ext_host_sst_bus" : 1, + "ext_host_data_fifo_clr": 1, + + "ext_host_target_addr" : 8, + "ext_host_write_length" : 8, + "ext_host_read_length" : 8, + "ext_host_cmd" : 8, + "ext_host_writedata" : 8, + + "ext_hostctl_start" : 1, + "ext_hostctl_sst_amdsi" : 1, + "ext_hostctl_sst_ctl" : 1, + "ext_hostctl_resetfifo" : 1, + "ext_hostctl_fcs_abort" : 1, + "ext_hostctl_start_en" : 1, + # Auto-Start Control + # The host will start the transaction + # at a regular rate automatically. + # 00: 32 Hz + # 01: 16 Hz + # 10: 8 Hz + # 11: 4 Hz + "ext_hostctl_start_ctl" : 2, + + "ext_host_readdata" : 8, + + "fan1_temp_limit_start" : 8, + "fan1_slope_pwm" : 7, + "fan1_temp_input_sel0" : 1, + "fan1_ctlmode_temp_ivl" : 5, + "fan1_ctlmode_target" : 2, + "fan1_temp_input_sel1" : 1, + "reserved93" : 8, + "fan2_temp_limit_start" : 8, + "fan2_slope_pwm" : 7, + "fan2_temp_input_sel0" : 1, + "fan2_ctlmode_temp_ivl" : 5, + "fan2_ctlmode_target" : 2, + "fan2_temp_input_sel1" : 1 +}

1 0

New patch to review for coreboot: mb/lenovo/t400/romstage: Enable D1F0
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18195 -gerrit commit e88e3783d436c9189f2dc3c4f58b0a0a1eb1d1a8 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:45:03 2017 +0100 mb/lenovo/t400/romstage: Enable D1F0 Enable PEG (D1F0) to make sure it can be accessed by raminit(). Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/romstage.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index d110d4f..b23a5d3 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -104,11 +104,14 @@ void mainboard_romstage_entry(unsigned long bist) sysinfo.enable_igd = 1; sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); - raminit(&sysinfo, s3resume); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); /* Disable D4F0 (unknown signal controller). */ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven & ~0x4000); + /* Enable D1F0 (PEG). */ + pci_write_config32(MCH_DEV, D0F0_DEVEN, deven | 2); + + raminit(&sysinfo, s3resume); init_pm(&sysinfo, 0);

1 0

New patch to review for coreboot: nb/intel/gm45/igd: Hide IGD while disabling
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18194 -gerrit commit 04c8d0c77bb6b3736c1989379083f45c74b38eb0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:43:52 2017 +0100 nb/intel/gm45/igd: Hide IGD while disabling Hide the IGD to make sure ramstage doesn't detect it. Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/igd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index 74572ca..1164339 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -127,6 +127,11 @@ static void disable_igd(const sysinfo_t *const sysinfo) MCHBAR16(0x119e) = (MCHBAR16(0x119e) & ~(7 << 13)) | (4 << 13); MCHBAR16(0x119e) |= (1 << 12); } + + /* Hide IGD. */ + u32 deven = pci_read_config32(mch_dev, D0F0_DEVEN); + deven &= ~(3 << 3); + pci_write_config32(mch_dev, D0F0_DEVEN, deven); } void init_igd(const sysinfo_t *const sysinfo)

1 0

New patch to review for coreboot: nb/intel/gm45/nb: Move DEVEN device hiding
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18193 -gerrit commit 497133dba325e65f1064ccea3f29528e1b6952ad Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Jan 21 10:33:20 2017 +0100 nb/intel/gm45/nb: Move DEVEN device hiding Move and improve DEVEN device hiding. Instead of relying only on devicetree, allow the PCI code to scan for devices, and invoke custom PCI driver functions. Therefore the code has been moved to PCI init function. Add support for disabling IGD. Fixes a crash in GNU Linux: In case the IGD is disabled by romstage, Linux still detects the IGD, but as it doesn't have resources assigned, it causes a crash in drm kernel module. Change-Id: I03578d358f31b605f300a67f5b078eff834e070c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/northbridge.c | 79 +++++++++++++++----------------- 1 file changed, 38 insertions(+), 41 deletions(-) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 3cb7d11..65e2052 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -180,14 +180,49 @@ static void mch_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -static void mch_domain_init(device_t dev) +static void mch_domain_init(device_t d0f0) { + u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + device_t dev; u32 reg32; /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 = pci_read_config32(d0f0, PCI_COMMAND); reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config32(d0f0, PCI_COMMAND, reg32); + + /* Hide internal functions on bus 0. */ + printk(BIOS_INFO, "mch_domain_init: Hiding "); + + dev = dev_find_slot(0, PCI_DEVFN(3, 3)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "ME "); + deven &= ~(1 << 9); + } + + dev = dev_find_slot(0, PCI_DEVFN(2, 1)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "IGD_DC "); + deven &= ~(1 << 4); + } + + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "IGD "); + deven &= ~(1 << 3); + } + + dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (dev && !dev->enabled) { + printk(BIOS_INFO, "PEG "); + deven &= ~(1 << 1); + } + printk(BIOS_INFO, "\n"); + + if (!(deven & (0xf << 6))) + deven &= ~(1 << 14); + + pci_write_config32(d0f0, D0F0_DEVEN, deven); } static struct device_operations pci_domain_ops = { @@ -225,45 +260,7 @@ static void enable_dev(device_t dev) } } -static void gm45_init(void *const chip_info) -{ - int dev, fn, bit_base; - - struct device *const d0f0 = dev_find_slot(0, 0); - - /* Hide internal functions based on devicetree info. */ - for (dev = 3; dev > 0; --dev) { - switch (dev) { - case 3: /* ME */ - fn = 3; - bit_base = 6; - break; - case 2: /* IGD */ - fn = 1; - bit_base = 3; - break; - case 1: /* PEG */ - fn = 0; - bit_base = 1; - break; - } - for (; fn >= 0; --fn) { - const struct device *const d = - dev_find_slot(0, PCI_DEVFN(dev, fn)); - if (!d || d->enabled) continue; - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); - pci_write_config32(d0f0, D0F0_DEVEN, - deven & ~(1 << (bit_base + fn))); - } - } - - const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); - if (!(deven & (0xf << 6))) - pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); -} - struct chip_operations northbridge_intel_gm45_ops = { CHIP_NAME("Intel GM45 Northbridge") .enable_dev = enable_dev, - .init = gm45_init, };

1 0

New patch to review for coreboot: x86/acpi: Add VFCT table
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18192 -gerrit commit 251b35ae3c52f1519336e27ad1c95612d9e4653b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 31 20:04:23 2016 +0200 x86/acpi: Add VFCT table Add VFCT table to provide PCI Optiom Rom for AMD graphic devices. Useful for GNU Linux payloads and embedded dual GPU systems. Tested on Lenovo T500 with AMD RV635 as secondary gpu. Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422 --- src/arch/x86/acpi.c | 25 ++++++++++++++++ src/arch/x86/include/arch/acpi.h | 29 ++++++++++++++++++ src/device/pci_device.c | 1 + src/device/pci_rom.c | 63 ++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_rom.h | 7 +++++ 5 files changed, 125 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 53c4135..703bfa1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -589,6 +589,31 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)) +{ + acpi_header_t *header = &(vfct->header); + unsigned long current = (unsigned long)vfct + sizeof(struct acpi_vfct); + + memset((void *)vfct, 0, sizeof(struct acpi_vfct)); + + /* Fill out header fields. */ + memcpy(header->signature, "VFCT", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(struct acpi_vfct); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_vfct(device, vfct, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)vfct; + header->checksum = acpi_checksum((void *)vfct, header->length); +} + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) { diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 6854573..f36bd8c 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -220,6 +220,31 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; + +/* VFCT image header */ +struct acpi_vfct_image_hdr { + u32 PCIBus; //0x4C + u32 PCIDevice; //0x50 + u32 PCIFunction; //0x54 + u16 VendorID; //0x58 + u16 DeviceID; //0x5A + u16 SSVID; //0x5C + u16 SSID; //0x5E + u32 Revision; //0x60 + u32 ImageLength; //0x64 + u8 VbiosContent; // dummy - copy VBIOS here +} __attribute__ ((packed)); + +/* VFCT (VBIOS Fetch Table) */ +struct acpi_vfct { + struct acpi_table_header header; + u8 TableUUID[16]; //0x24 + u32 VBIOSImageOffset; //0x34. + u32 Lib1ImageOffset; //0x38. + u32 Reserved[4]; //0x3C + struct acpi_vfct_image_hdr image_hdr; +} __attribute__ ((packed)); + typedef struct acpi_ivrs_info { } __attribute__ ((packed)) acpi_ivrs_info_t; @@ -601,6 +626,10 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_vfct(struct device *device, + struct acpi_vfct *vfct, + unsigned long (*acpi_fill_vfct)(struct device *device, struct acpi_vfct *vfct_struct, unsigned long current)); + void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 06294d0..5a52eb6 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -735,6 +735,7 @@ struct device_operations default_pci_ops_dev = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .write_acpi_tables = pci_rom_write_acpi_tables, .init = pci_dev_init, .scan_bus = 0, .enable = 0, diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 8366fea..f657688 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -169,3 +169,66 @@ struct rom_header *pci_rom_load(struct device *dev, pci_ram_image_start += rom_size; return (struct rom_header *) (pci_ram_image_start-rom_size); } + +/* ACPI */ +static unsigned long +pci_rom_acpi_fill_vfct(struct device *device, + struct acpi_vfct *vfct_struct, + unsigned long current) +{ + struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr; + struct rom_header *rom; + + vfct_struct->VBIOSImageOffset = (size_t)header - (size_t)vfct_struct; + + rom = pci_rom_probe(device); + if (!rom) { + printk(BIOS_ERR, "pci_rom_acpi_fill_vfct failed\n"); + return current; + } + + header->DeviceID = device->device; + header->VendorID = device->vendor; + header->PCIBus = device->bus->secondary; + header->PCIFunction = PCI_FUNC(device->path.pci.devfn); + header->PCIDevice = PCI_SLOT(device->path.pci.devfn); + header->ImageLength = rom->size * 512; + memcpy((void *)&header->VbiosContent, rom, header->ImageLength); + + current += header->ImageLength; + return current; +} + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + struct acpi_vfct *vfct; + struct rom_header *rom; + + /* Only handle VGA devices */ + if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) + return current; + + /* Only handle enabled devices */ + if (!device->enabled) + return current; + + /* Probe for option rom */ + rom = pci_rom_probe(device); + if (!rom) + return current; + + /* AMD/ATI uses VFCT */ + if (device->vendor == PCI_VENDOR_ID_ATI) { + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current); + vfct = (struct acpi_vfct *)current; + acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct); + current += vfct->header.length; + acpi_add_table(rsdp, vfct); + } + + return current; +} diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 2fb2f7a..3f09778 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -2,6 +2,7 @@ #define PCI_ROM_H #include <endian.h> #include <stddef.h> +#include <arch/acpi.h> #define PCI_ROM_HDR 0xAA55 #define PCI_DATA_HDR (uint32_t) ( ('R' << 24) | ('I' << 16) | ('C' << 8) | 'P' ) @@ -35,6 +36,12 @@ struct pci_data { struct rom_header *pci_rom_probe(struct device *dev); struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header); + +unsigned long +pci_rom_write_acpi_tables(struct device *device, + unsigned long current, + struct acpi_rsdp *rsdp); + u32 map_oprom_vendev(u32 vendev); #endif

1 0

Patch set updated for coreboot: mb/lenovo/t400: Implement hybrid graphic in romstage
by Patrick Rudolph 21 Jan '17

21 Jan '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18010 -gerrit commit a0de0c323da37b6bc734b052e7518e835c3f8400 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Jan 2 16:16:45 2017 +0100 mb/lenovo/t400: Implement hybrid graphic in romstage The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work for t400/t500. Replace it with a custom romstage implementation. Tested on Lenovo T500 with dual graphics: * Intel Native GFX init * AMD VBios * GNU Linux 4.8.13 * SeaBios as payload * Integrated is working (24 W) ** Seems to always run at 100% * Discrete is working (44 W) ** Seems to always run at 100% * Switchable is working (34 W) ** Both GPUs are enabled, with Intel being connected to the panel ** DRI_PRIME allows to use AMD GPU ** ACPI doesn't seem to work (no vgaswitcheroo) Depends on Change-Id: I03578d358f31b605f300a67f5b078eff834e070c Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201 Depends on Change-Id: Ia3c1516c54c28bbe5a127153912c9682e975bea2 Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 1 - src/mainboard/lenovo/t400/Makefile.inc | 1 + src/mainboard/lenovo/t400/cmos.layout | 1 + src/mainboard/lenovo/t400/hybrid_graphics.c | 87 +++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/romstage.c | 9 ++- 5 files changed, 96 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index f21f672..150199e 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 - select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index b382efb..c02a70b 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -15,3 +15,4 @@ ramstage-y += dock.c ramstage-y += cstates.c +romstage-y += hybrid_graphics.c diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..cf31453 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -142,6 +142,7 @@ enumerations 11 12 352M 12 0 Integrated Only 12 1 Discrete Only +12 2 Switchable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c new file mode 100644 index 0000000..2bbb0d2 --- /dev/null +++ b/src/mainboard/lenovo/t400/hybrid_graphics.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <string.h> +#include <southbridge/intel/common/gpio.h> +#include <northbridge/intel/gm45/gm45.h> +#include <console/console.h> +#include <option.h> + +#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 +#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 +#define HYBRID_GRAPHICS_SWITCHABLE 2 + +#define MUX_GPIO 22 +#define BCL_CTL_GPIO 19 +#define GFX_PWR_EN_GPIO 49 + +#define HYBRID_DETECT_GPIO 21 + +void hybrid_graphics_init(sysinfo_t *sysinfo); + +static bool hybrid_graphics_installed(void) +{ + if (get_gpio(HYBRID_DETECT_GPIO)) + return false; + else + return true; +} + +void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + /* Set default mode */ + uint8_t hybrid_graphics_mode = 0xff; + + if (hybrid_graphics_installed()) { + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + printk(BIOS_DEBUG, "Hybrid graphics available.\n"); + } else + printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); + + /* Select appropriate hybrid graphics device */ + switch (hybrid_graphics_mode) { + case HYBRID_GRAPHICS_INTEGRATED_ONLY: + printk(BIOS_DEBUG, "Activating Integrated Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); + + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 0; + break; + case HYBRID_GRAPHICS_DISCRETE_ONLY: + printk(BIOS_DEBUG, "Activating Discrete Only.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + sysinfo->enable_igd = 0; + sysinfo->enable_peg = 1; + break; + case HYBRID_GRAPHICS_SWITCHABLE: + printk(BIOS_DEBUG, "Activating Switchable.\n"); + set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); + set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); + set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); + + /* Fall-through */ + default: + /* The display is not connected to a mux or switchable. */ + sysinfo->enable_igd = 1; + sysinfo->enable_peg = 1; + break; + } +} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index b23a5d3..659e562 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -36,6 +36,8 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) +void hybrid_graphics_init(sysinfo_t *sysinfo); + static void early_lpc_setup(void) { /* Set up SuperIO LPC forwards */ @@ -101,8 +103,6 @@ void mainboard_romstage_entry(unsigned long bist) memset(&sysinfo, 0, sizeof(sysinfo)); sysinfo.spd_map[0] = 0x50; sysinfo.spd_map[2] = 0x51; - sysinfo.enable_igd = 1; - sysinfo.enable_peg = 0; get_gmch_info(&sysinfo); const u32 deven = pci_read_config32(MCH_DEV, D0F0_DEVEN); @@ -111,6 +111,11 @@ void mainboard_romstage_entry(unsigned long bist) /* Enable D1F0 (PEG). */ pci_write_config32(MCH_DEV, D0F0_DEVEN, deven | 2); + /* Configure graphic GPIOs. + * Make sure there's a little delay between + * setup_pch_gpios() and this call ! */ + hybrid_graphics_init(&sysinfo); + raminit(&sysinfo, s3resume); init_pm(&sysinfo, 0);

1 0

Patch set updated for coreboot: util/blobtool: Add new tool for compiling/decompiling data blobs
by Damien Zammit 21 Jan '17

21 Jan '17

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17445 -gerrit commit 906d7f1b27151c41e9b456141fa57ac9d7101277 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Nov 16 21:06:54 2016 +1100 util/blobtool: Add new tool for compiling/decompiling data blobs Given a specification of bitfields defined e.g. as follows: specfile: { "field1" : 8, "field2" : 4, "field3" : 4 } and a set of values for setting defaults: setterfile: { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } You can generate a binary packed blob as follows: ./blobtool specfile setterfile binaryoutput binaryoutput: ff ff The reverse is also possible, i.e. you can regenerate the setter: ./blobtool -d specfile binaryoutput setterorig setterorig: # AUTOGENERATED SETTER BY BLOBTOOL { "field1" = 0xff, "field2" = 0xf, "field3" = 0xf } This tool comes with spec/set files for X200 flash descriptor and ICH9M GbE region, and can be extended or used to decompile other data blobs with known specs. Change-Id: I744d6b421003feb4fc460133603af7e6bd80b1d6 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- util/blobtool/Makefile | 29 +++ util/blobtool/blobtool.l | 144 ++++++++++++ util/blobtool/blobtool.y | 537 +++++++++++++++++++++++++++++++++++++++++++ util/blobtool/gbe-ich9m.set | 88 +++++++ util/blobtool/gbe-ich9m.spec | 142 ++++++++++++ util/blobtool/ifd-x200.set | 167 ++++++++++++++ util/blobtool/ifd-x200.spec | 187 +++++++++++++++ 7 files changed, 1294 insertions(+) diff --git a/util/blobtool/Makefile b/util/blobtool/Makefile new file mode 100644 index 0000000..ee706db --- /dev/null +++ b/util/blobtool/Makefile @@ -0,0 +1,29 @@ +CC = gcc +YACC = bison +LEX = flex +TARGET=blobtool + +$(TARGET): $(TARGET).lex.o $(TARGET).tab.o + $(CC) $^ -Wall -Wno-unused-function -g -lfl -o $@ + +$(TARGET).lex.c: $(TARGET).l $(TARGET).tab.h + $(LEX) -o $(patsubst $(TARGET).l,$(TARGET).lex.c,$<) $< + +$(TARGET).tab.c $(TARGET).tab.h: $(TARGET).y + $(YACC) -d $< + +# Use this target to generate GbE for X200 +gen-gbe-ich9m: + ./blobtool gbe-ich9m.spec gbe-ich9m.set gbe1.bin + # duplicate binary as per spec + cat gbe1.bin gbe1.bin > flashregion_3_gbe.bin + rm -f gbe1.bin + +# Use this target to generate IFD for X200 +gen-ifd-x200: + ./blobtool ifd-x200.spec ifd-x200.set flashregion_0_fd.bin + +.PHONY: clean gen-gbe-ich9m gen-ifd-x200 + +clean: + rm -f *.lex.c *.tab.c *.tab.h *.o blobtool flashregion_0_fd.bin flashregion_3_gbe.bin diff --git a/util/blobtool/blobtool.l b/util/blobtool/blobtool.l new file mode 100644 index 0000000..e6a09ab --- /dev/null +++ b/util/blobtool/blobtool.l @@ -0,0 +1,144 @@ +/* + * blobtool - Compiler/Decompiler for data blobs with specs + * Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +%{ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include "blobtool.tab.h" + +extern struct blob binary; + +unsigned int parsehex (char *s) +{ + unsigned int i, nib, val = 0; + unsigned int nibs = strlen(s) - 2; + + for (i = 2; i < nibs + 2; i++) { + if (s[i] >= '0' && s[i] <= '9') { + nib = s[i] - '0'; + } else if (s[i] >= 'a' && s[i] <= 'f') { + nib = s[i] - 'a' + 10; + } else if (s[i] >= 'A' && s[i] <= 'F') { + nib = s[i] - 'A' + 10; + } else { + return 0; + } + val |= nib << (((nibs - 1) - (i - 2)) * 4); + } + return val; +} + +char* stripquotes (char *string) +{ + char *stripped; + unsigned int len = strlen(string); + if (len >= 2 && string[0] == '\"' && string[len-1] == '\"') { + stripped = (char *) malloc (len - 2 + 1); + snprintf (stripped, len - 2 + 1, "%s", string+1); + stripped[len-2] = '\0'; + return stripped; + } else { + return 0; + } +} + +%} + +%option nounput + +DIGIT1to9 [1-9] +DIGIT [0-9] +DIGITS {DIGIT}+ +INT {DIGIT}|{DIGIT1to9}{DIGITS}|-{DIGIT}|-{DIGIT1to9}{DIGITS} +FRAC [.]{DIGITS} +E [eE][+-]? +EXP {E}{DIGITS} +HEX_DIGIT [0-9a-fA-F] +HEX_DIGITS {HEX_DIGIT}+ +NUMBER {INT}|{INT}{FRAC}|{INT}{EXP}|{INT}{FRAC}{EXP} +UNICODECHAR \\u{HEX_DIGIT}{HEX_DIGIT}{HEX_DIGIT}{HEX_DIGIT} +ALPHA [a-zA-Z] +SPECIAL [()\[\]"'@_\-+:;/\\.,<> ] +VARCHAR {ALPHA}|{DIGIT}|{SPECIAL} +CHAR {VARCHAR}|{UNICODECHAR} +CHARS {CHAR}+ +QUOTE ["] +HEX_PREFIX [0][x] +HEX {HEX_PREFIX}{HEX_DIGITS} +STRING {QUOTE}{QUOTE}|{QUOTE}{CHARS}{QUOTE} +COMMENT [#]{CHARS}[\n]|[#]\n + +%% + +{STRING} { + yylval.str = stripquotes(yytext); + return name; +}; + +{NUMBER} { + yylval.u32 = atoi(yytext); + return val; +}; + +{HEX} { + yylval.u32 = parsehex(yytext); + return val; +}; + +\{ { + return '{'; +}; + +\} { + return '}'; +}; + +\[ { + return '['; +}; + +\] { + return ']'; +}; + +, { + return ','; +}; + +: { + return ':'; +}; + += { + return '='; +}; + +[ \t\n]+ /* ignore whitespace */; + +{COMMENT} /* ignore comments */ + +\% { + return '%'; +}; + +<<EOF>> { return eof; }; + +%% + +void set_input_string(char* in) { + yy_scan_string(in); +} + diff --git a/util/blobtool/blobtool.y b/util/blobtool/blobtool.y new file mode 100644 index 0000000..909102d --- /dev/null +++ b/util/blobtool/blobtool.y @@ -0,0 +1,537 @@ +/* + * blobtool - Compiler/Decompiler for data blobs with specs + * Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +%{ +#include <stdio.h> +#include <inttypes.h> +#include <stdlib.h> +#include <string.h> +//#define YYDEBUG 1 +int yylex (void); +void yyerror (char const *); + +struct field { + char *name; + unsigned int width; + unsigned int value; + struct field *next; +}; + +extern struct field *sym_table; +struct field *putsym (char const *, unsigned int); +struct field *getsym (char const *); + +struct field *sym_table; +struct field *sym_table_tail; + +FILE* fp; + +/* Bit array intermediary representation */ +struct blob { + unsigned int bloblen; + unsigned char *blb; + unsigned short checksum; + unsigned char *actualblob; + unsigned int lenactualblob; +}; + +#define VALID_BIT 0x80 +#define MAX_WIDTH 32 +#define CHECKSUM_SIZE 16 + +struct blob *binary; + +unsigned char* value_to_bits (unsigned int v, unsigned int w) +{ + unsigned int i; + unsigned char* bitarr; + + if (w > MAX_WIDTH) w = MAX_WIDTH; + bitarr = (unsigned char *) malloc (w * sizeof (unsigned char)); + memset (bitarr, 0, w); + + for (i = 0; i < w; i++) { + bitarr[i] = VALID_BIT | ((v & (1 << i)) >> i); + } + return bitarr; +} + +/* Store each bit of a bitfield in a new byte sequentially 0x80 or 0x81 */ +void append_field_to_blob (unsigned char b[], unsigned int w) +{ + unsigned int i, j; + binary->blb = (unsigned char *) realloc (binary->blb, binary->bloblen + w); + for (j = 0, i = binary->bloblen; i < binary->bloblen + w; i++, j++) { + binary->blb[i] = VALID_BIT | (b[j] & 1); + //fprintf (stderr, "blob[%d] = %d\n", i, binary->blb[i] & 1); + } + binary->bloblen += w; +} + +void set_bitfield(char *name, unsigned int value) +{ + unsigned long long i; + struct field *bf = getsym (name); + if (bf) { + bf->value = value & 0xffffffff; + i = (1 << bf->width) - 1; + if (bf->width > 8 * sizeof (unsigned int)) { + fprintf(stderr, "Overflow in bitfield, truncating bits to fit\n"); + bf->value = value & i; + } + //fprintf(stderr, "Setting `%s` = %d\n", bf->name, bf->value); + } else { + fprintf(stderr, "Can't find bitfield `%s` in spec\n", name); + } +} + +void set_bitfield_array(char *name, unsigned int n, unsigned int value) +{ + unsigned int i; + unsigned int len = strlen (name); + char *namen = (char *) malloc ((len + 9) * sizeof (char)); + for (i = 0; i < n; i++) { + snprintf (namen, len + 8, "%s%x", name, i); + set_bitfield (namen, value); + } + free(namen); +} + +void create_new_bitfield(char *name, unsigned int width) +{ + struct field *bf; + + if (!(bf = putsym (name, width))) return; + //fprintf(stderr, "Added bitfield `%s` : %d\n", bf->name, width); +} + +void create_new_bitfields(char *name, unsigned int n, unsigned int width) +{ + unsigned int i; + unsigned int len = strlen (name); + char *namen = (char *) malloc ((len + 9) * sizeof (char)); + for (i = 0; i < n; i++) { + snprintf (namen, len + 8, "%s%x", name, i); + create_new_bitfield (namen, width); + } + free(namen); +} + +struct field *putsym (char const *sym_name, unsigned int w) +{ + if (getsym(sym_name)) { + fprintf(stderr, "Cannot add duplicate named bitfield `%s`\n", sym_name); + return 0; + } + struct field *ptr = (struct field *) malloc (sizeof (struct field)); + ptr->name = (char *) malloc (strlen (sym_name) + 1); + strcpy (ptr->name, sym_name); + ptr->width = w; + ptr->value = 0; + ptr->next = (struct field *)0; + if (sym_table_tail) { + sym_table_tail->next = ptr; + } else { + sym_table = ptr; + } + sym_table_tail = ptr; + return ptr; +} + +struct field *getsym (char const *sym_name) +{ + struct field *ptr; + for (ptr = sym_table; ptr != (struct field *) 0; + ptr = (struct field *)ptr->next) { + if (strcmp (ptr->name, sym_name) == 0) + return ptr; + } + return 0; +} + +void dump_all_values (void) +{ + struct field *ptr; + for (ptr = sym_table; ptr != (struct field *) 0; + ptr = (struct field *)ptr->next) { + fprintf(stderr, "%s = %d (%d bits)\n", + ptr->name, + ptr->value, + ptr->width); + } +} + +void empty_field_table(void) +{ + struct field *ptr; + struct field *ptrnext; + + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptrnext) { + if (ptr) { + ptrnext = ptr->next; + free(ptr); + } else { + ptrnext = (struct field *) 0; + } + } + sym_table = 0; + sym_table_tail = 0; +} + +void create_binary_blob (void) +{ + if (binary && binary->blb) { + free(binary->blb); + free(binary); + } + binary = (struct blob *) malloc (sizeof (struct blob)); + binary->blb = (unsigned char *) malloc (sizeof (unsigned char)); + binary->bloblen = 0; + binary->blb[0] = VALID_BIT; +} + +void interpret_next_blob_value (struct field *f) +{ + int i; + unsigned int v = 0; + + if (binary->bloblen >= binary->lenactualblob * 8) { + f->value = 0; + return; + } + + for (i = 0; i < f->width; i++) { + v |= (binary->blb[binary->bloblen++] & 1) << i; + } + + f->value = v; +} + +/* {}%BIN -> {} */ +void generate_setter_bitfields(unsigned char *bin) +{ + unsigned int i; + struct field *ptr; + + /* Convert bytes to bit array */ + for (i = 0; i < binary->lenactualblob; i++) { + append_field_to_blob (value_to_bits(bin[i], 8), 8); + } + + /* Reset blob position to zero */ + binary->bloblen = 0; + + fprintf (fp, "# AUTOGENERATED SETTER BY BLOBTOOL\n{\n"); + + /* Traverse spec and output bitfield setters based on blob values */ + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + + interpret_next_blob_value(ptr); + fprintf (fp, "\t\"%s\" = 0x%x,\n", ptr->name, ptr->value); + } + fseek(fp, -2, SEEK_CUR); + fprintf (fp, "\n}\n"); +} + +void generate_binary_with_gbe_checksum(void) +{ + int i; + unsigned short checksum; + + /* traverse spec, push to blob and add up for checksum */ + struct field *ptr; + unsigned int uptochksum = 0; + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + if (strcmp (ptr->name, "checksum_gbe") == 0) { + /* Stop traversing because we hit checksum */ + ptr = ptr->next; + break; + } + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), + ptr->width); + uptochksum += ptr->width; + } + + /* deserialize bits of blob up to checksum */ + for (i = 0; i < uptochksum; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + + /* incremental 16 bit checksum */ + if ((i % 16) < 8) { + binary->checksum += byte; + } else { + binary->checksum += byte << 8; + } + } + + checksum = (0xbaba - binary->checksum) & 0xffff; + + /* Now write checksum */ + set_bitfield ("checksum_gbe", checksum); + + fprintf(fp, "%c", checksum & 0xff); + fprintf(fp, "%c", (checksum & 0xff00) >> 8); + + append_field_to_blob (value_to_bits(checksum, 16), 16); + + for (; ptr != (struct field *) 0; ptr = ptr->next) { + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), ptr->width); + } + + /* deserialize rest of blob past checksum */ + for (i = uptochksum + CHECKSUM_SIZE; i < binary->bloblen; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + } +} + +/* {}{} -> BIN */ +void generate_binary(void) +{ + unsigned int i; + struct field *ptr; + + if (binary->bloblen % 8) { + fprintf (stderr, "ERROR: Spec must be multiple of 8 bits wide\n"); + exit (1); + } + + if (getsym ("checksum_gbe")) { + generate_binary_with_gbe_checksum(); + return; + } + + /* traverse spec, push to blob */ + for (ptr = sym_table; ptr != (struct field *) 0; ptr = ptr->next) { + append_field_to_blob ( + value_to_bits(ptr->value, ptr->width), + ptr->width); + } + + /* deserialize bits of blob */ + for (i = 0; i < binary->bloblen; i += 8) { + unsigned char byte = (((binary->blb[i+0] & 1) << 0) + | ((binary->blb[i+1] & 1) << 1) + | ((binary->blb[i+2] & 1) << 2) + | ((binary->blb[i+3] & 1) << 3) + | ((binary->blb[i+4] & 1) << 4) + | ((binary->blb[i+5] & 1) << 5) + | ((binary->blb[i+6] & 1) << 6) + | ((binary->blb[i+7] & 1) << 7) + ); + fprintf(fp, "%c", byte); + } +} + +%} + +%union +{ + char *str; + unsigned int u32; + unsigned int *u32array; + unsigned char u8; + unsigned char *u8array; +} + +%token <str> name +%token <u32> val +%token <u32array> vals +%token <u8> hexbyte +%token <u8array> binblob +%token <u8> eof + +%left '%' +%left '{' '}' +%left ',' +%left ':' +%left '=' + +%% + +input: + /* empty */ +| input spec setter eof { empty_field_table(); YYACCEPT;} +| input spec blob { fprintf (stderr, "Parsed all bytes\n"); + empty_field_table(); YYACCEPT;} +; + +blob: + '%' eof { generate_setter_bitfields(binary->actualblob); } +; + +spec: + '{' '}' { fprintf (stderr, "No spec\n"); } +| '{' specmembers '}' { fprintf (stderr, "Parsed all spec\n"); + create_binary_blob(); } +; + +specmembers: + specpair +| specpair ',' specmembers +; + +specpair: + name ':' val { create_new_bitfield($1, $3); } +| name '[' val ']' ':' val { create_new_bitfields($1, $3, $6); } +; + +setter: + '{' '}' { fprintf (stderr, "No values\n"); } +| '{' valuemembers '}' { fprintf (stderr, "Parsed all values\n"); + generate_binary(); } +; + +valuemembers: + setpair +| setpair ',' valuemembers +; + +setpair: + name '=' val { set_bitfield($1, $3); } +| name '[' val ']' '=' val { set_bitfield_array($1, $3, $6); } +; + +%% + +/* Called by yyparse on error. */ +void yyerror (char const *s) +{ + fprintf (stderr, "yyerror: %s\n", s); +} + +/* Declarations */ +void set_input_string(char* in); + +/* This function parses a string */ +int parse_string(unsigned char* in) { + set_input_string ((char *)in); + return yyparse (); +} + +int main (int argc, char *argv[]) +{ + unsigned int lenspec, lensetter; + unsigned char *parsestring; + unsigned char c; + unsigned int pos = 0; + int ret = 0; + +#if YYDEBUG == 1 + yydebug = 1; +#endif + create_binary_blob(); + binary->lenactualblob = 0; + + if (argc == 4 && strcmp(argv[1], "-d") != 0) { + /* Compile mode */ + + /* Load Spec */ + fp = fopen(argv[1], "r"); + fseek(fp, 0, SEEK_END); + lenspec = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) malloc (lenspec); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fread(parsestring, 1, lenspec, fp); + fclose(fp); + + /* Load Setter */ + fp = fopen(argv[2], "r"); + fseek(fp, 0, SEEK_END); + lensetter = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) realloc (parsestring, + lenspec + lensetter); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fread(parsestring + lenspec, 1, lensetter, fp); + fclose(fp); + + /* Open output and parse string - output to fp */ + fp = fopen(argv[3], "wb"); + ret = parse_string(parsestring); + free(parsestring); + } else if (argc == 5 && strcmp (argv[1], "-d") == 0) { + /* Decompile mode */ + + /* Load Spec */ + fp = fopen(argv[2], "r"); + fseek(fp, 0, SEEK_END); + lenspec = ftell(fp); + fseek(fp, 0, SEEK_SET); + parsestring = (unsigned char *) malloc (lenspec + 1); + fread(parsestring, 1, lenspec, fp); + if (!parsestring) { + printf("Out of memory\n"); + exit(1); + } + fclose(fp); + + /* Add binary read trigger token */ + parsestring[lenspec] = '%'; + + /* Load Actual Binary */ + fp = fopen(argv[3], "rb"); + fseek(fp, 0, SEEK_END); + binary->lenactualblob = ftell(fp); + fseek(fp, 0, SEEK_SET); + binary->actualblob = (unsigned char *) malloc (binary->lenactualblob); + if (!binary->actualblob) { + printf("Out of memory\n"); + exit(1); + } + fread(binary->actualblob, 1, binary->lenactualblob, fp); + fclose(fp); + + /* Open output and parse - output to fp */ + fp = fopen(argv[4], "w"); + ret = parse_string(parsestring); + free(parsestring); + free(binary->actualblob); + fclose(fp); + } else { + printf("Usage: Compile mode\n\n"); + printf(" blobtool spec setter binaryoutput\n"); + printf(" (file) (file) (file)\n"); + printf(" OR : Decompile mode\n\n"); + printf(" blobtool -d spec binary setteroutput\n"); + } + return ret; +} diff --git a/util/blobtool/gbe-ich9m.set b/util/blobtool/gbe-ich9m.set new file mode 100644 index 0000000..01f85ab --- /dev/null +++ b/util/blobtool/gbe-ich9m.set @@ -0,0 +1,88 @@ +# +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +# GbE values for ICH9M +{ + # Hardcoded chipset values + "reserved04" = 0xffff, + "version05" = 0x1083, + "reserved06" = 0xffff, + "reserved07" = 0xffff, + "pbalow" = 0xffff, + "pbahigh" = 0xffff, + "pci_loadvid" = 1, + "pci_loadssid" = 1, + "pci_pmen" = 1, + "pci_auxpwr" = 1, + "pci_reserved4" = 1, + "sh_phy_enpwrdown" = 1, + "sh_reserved1" = 0x5, + "sh_reserved3" = 1, + "sh_sign" = 0x2, + "cw1_extcfgptr" = 0x020, + "cw1_oemload" = 1, + "cw1_reserved1" = 1, + "cw2_extphylen" = 0x05, + "l1_reserved2" = 1, + "l1_reserved4" = 1, + "l1_lplu_non_d0a" = 1, + "l1_gbedis_non_d0a" = 1, + "reserved19" = 0x2b40, + "reserved1a" = 0x0043, + "reserved1c" = 0x10f5, + "reserved1d" = 0xbaad, + "_82567lm" = 0x10f5, + "_82567lf" = 0x10bf, + "reserved20" = 0xbaad, + "_82567v" = 0x10cb, + "reserved22_0" = 0xbaad, + "reserved22_1" = 0xbaad, + + # Hardcoded PXE setup (disabled) + "pxe30_defbootsel" = 0x3, + "pxe30_ctrlsprompt" = 0x3, + "pxe30_pxeabsent" = 1, + "pxe31_disablemenu" = 1, + "pxe31_disabletitle" = 1, + "pxe31_signature" = 1, + "pxe32_buildnum" = 0x18, + "pxe32_minorversion" = 0x3, + "pxe32_majorversion" = 0x1, + "pxe33_basecodeabsent" = 1, + "pxe33_undipresent" = 1, + "pxe33_reserved1" = 1, + "pxe33_signature" = 1, + "pxe_padding"[11] = 0xffff, + + # GbE power settings + "lanpwr_d3pwr" = 1, + "lanpwr_d0pwr" = 13, + + # GbE LED modes + "l1_led1mode" = 0xb, + "l1_led1blinks" = 1, + "l02_led0mode" = 0x2, + "l02_led2mode" = 0x1, + + # Padding 0xf80 bytes + "padding"[0xf80] = 0xff, + + # TODO: make command line switch for these + + # Configurable PCI IDs + "ssdid" = 0x20ee, + "ssvid" = 0x17aa, + "did" = 0x10f5, + "vid" = 0x8086 +} diff --git a/util/blobtool/gbe-ich9m.spec b/util/blobtool/gbe-ich9m.spec new file mode 100644 index 0000000..45eed0e --- /dev/null +++ b/util/blobtool/gbe-ich9m.spec @@ -0,0 +1,142 @@ +# +# Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> +# Leah Rowe <info(a)minifree.org> +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Datasheets: +# +# http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-… +# https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-… + +# The datasheet says that this spec covers the following pci ids: +# 8086:10F5 - Intel 82567LM gigabit ethernet controller +# 8086:10BF - Intel 82567LF gigabit ethernet controller +# 8086:10CB - Intel 82567V gigabit ethernet controller + +# GbE SPEC for ICH9M (82567LM/LF/V) +{ + "macaddress"[6] : 8, + "ba_reserved1_0" : 8, + "ba_reserved1_1" : 3, + "ba_ibootagent" : 1, + "ba_reserved2" : 4, + "reserved04" : 16, + "version05" : 16, + "reserved06" : 16, + "reserved07" : 16, + "pbalow" : 16, + "pbahigh" : 16, + "pci_loadvid" : 1, + "pci_loadssid" : 1, + "pci_reserved1" : 1, + "pci_reserved2" : 3, + "pci_pmen" : 1, + "pci_auxpwr" : 1, + "pci_reserved3" : 4, + "pci_reserved4" : 4, + "ssdid" : 16, + "ssvid" : 16, + "did" : 16, + "vid" : 16, + "devrevid" : 16, + "lanpwr_d3pwr" : 5, + "lanpwr_reserved" : 3, + "lanpwr_d0pwr" : 8, + "reserved11" : 16, + "reserved12" : 16, + "sh_reserved1" : 3, + "sh_force_halfduplex" : 1, + "sh_force_lowspeed" : 1, + "sh_reserved2_0" : 3, + "sh_reserved2_1" : 1, + "sh_phy_enpwrdown" : 1, + "sh_reserved3" : 1, + "sh_reserved4" : 3, + "sh_sign" : 2, + "cw1_extcfgptr" : 12, + "cw1_oemload" : 1, + "cw1_reserved1" : 1, + "cw1_reserved2" : 1, + "cw1_reserved3" : 1, + "cw2_reserved" : 8, + "cw2_extphylen" : 8, + "extcfg16" : 16, + "l1_led1mode" : 4, + "l1_reserved1" : 1, + "l1_led1fastblink" : 1, + "l1_led1invert" : 1, + "l1_led1blinks" : 1, + "l1_reserved2" : 1, + "l1_lplu_all" : 1, + "l1_lplu_non_d0a" : 1, + "l1_gbedis_non_d0a" : 1, + "l1_reserved3" : 2, + "l1_gbedis" : 1, + "l1_reserved4" : 1, + "l02_led0mode" : 4, + "l02_reserved1" : 1, + "l02_led0fastblink" : 1, + "l02_led0invert" : 1, + "l02_led0blinks" : 1, + "l02_led2mode" : 4, + "l02_reserved2" : 1, + "l02_led2fastblink" : 1, + "l02_led2invert" : 1, + "l02_led2blinks" : 1, + "reserved19" : 16, + "reserved1a" : 16, + "reserved1b" : 16, + "reserved1c" : 16, + "reserved1d" : 16, + "_82567lm" : 16, + "_82567lf" : 16, + "reserved20" : 16, + "_82567v" : 16, + "reserved22_"[14] : 16, + "pxe30_protocolsel" : 2, + "pxe30_reserved1" : 1, + "pxe30_defbootsel" : 2, + "pxe30_reserved2" : 1, + "pxe30_ctrlsprompt" : 2, + "pxe30_dispsetup" : 1, + "pxe30_reserved3" : 1, + "pxe30_forcespeed" : 2, + "pxe30_forcefullduplex" : 1, + "pxe30_reserved4" : 1, + "pxe30_efipresent" : 1, + "pxe30_pxeabsent" : 1, + "pxe31_disablemenu" : 1, + "pxe31_disabletitle" : 1, + "pxe31_disableprotsel" : 1, + "pxe31_disablebootorder": 1, + "pxe31_disablelegacywak": 1, + "pxe31_disableflash_pro": 1, + "pxe31_reserved1" : 2, + "pxe31_ibootagentmode" : 3, + "pxe31_reserved2" : 3, + "pxe31_signature" : 2, + "pxe32_buildnum" : 8, + "pxe32_minorversion" : 4, + "pxe32_majorversion" : 4, + "pxe33_basecodeabsent" : 1, + "pxe33_undipresent" : 1, + "pxe33_reserved1" : 1, + "pxe33_efiundipresent" : 1, + "pxe33_reserved2_0" : 4, + "pxe33_reserved2_1" : 6, + "pxe33_signature" : 2, + "pxe_padding"[11] : 16, + "checksum_gbe" : 16, + "padding"[0xf80] : 8 +} diff --git a/util/blobtool/ifd-x200.set b/util/blobtool/ifd-x200.set new file mode 100644 index 0000000..2894562 --- /dev/null +++ b/util/blobtool/ifd-x200.set @@ -0,0 +1,167 @@ +# +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# +# X200 Liberated Flash Descriptor +# Layout: +# 0x0000 - 0x1000 : IFD +# 0x1000 - 0x3000 : GbE x2 +# 0x3000 - ROMSIZE : BIOS +{ + "fd_signature" = 0xff0a55a, + + "flmap0_fcba" = 0x1, + "flmap0_nc" = 0x0, + "flmap0_reserved0" = 0x0, + "flmap0_frba" = 0x4, + "flmap0_nr" = 0x2, + "flmap0_reserved1" = 0x0, + "flmap1_fmba" = 0x6, + "flmap1_nm" = 0x2, + "flmap1_reserved" = 0x0, + "flmap1_fisba" = 0x10, + "flmap1_isl" = 0x2, + "flmap2_fmsba" = 0x20, + "flmap2_msl" = 0x1, + "flmap2_reserved" = 0x0, + + "flcomp_density1" = 0x4, + "flcomp_density2" = 0x2, + "flcomp_reserved0" = 0x0, + "flcomp_reserved1" = 0x0, + "flcomp_reserved2" = 0x0, + "flcomp_readclockfreq" = 0x0, + "flcomp_fastreadsupp" = 0x1, + "flcomp_fastreadfreq" = 0x1, + "flcomp_w_eraseclkfreq" = 0x0, + "flcomp_r_statclkfreq" = 0x0, + "flcomp_reserved3" = 0x0, + "flill" = 0x0, + "flbp" = 0x0, + "comp_padding"[0x24] = 0xff, + + "flreg0_base" = 0x0, + "flreg0_reserved0" = 0x0, + "flreg0_limit" = 0x0, + "flreg0_reserved1" = 0x0, + "flreg1_base" = 0x3, + "flreg1_reserved0" = 0x0, + "flreg1_limit" = 0x7ff, + "flreg1_reserved1" = 0x0, + "flreg2_base" = 0x1fff, + "flreg2_reserved0" = 0x0, + "flreg2_limit" = 0x0, + "flreg2_reserved1" = 0x0, + "flreg3_base" = 0x1, + "flreg3_reserved0" = 0x0, + "flreg3_limit" = 0x2, + "flreg3_reserved1" = 0x0, + "flreg4_base" = 0x1fff, + "flreg4_reserved0" = 0x0, + "flreg4_limit" = 0x0, + "flreg4_reserved1" = 0x0, + "flreg_padding"[12] = 0xff, + + "flmstr1_requesterid" = 0x0, + "flmstr1_r_fd" = 0x1, + "flmstr1_r_bios" = 0x1, + "flmstr1_r_me" = 0x1, + "flmstr1_r_gbe" = 0x1, + "flmstr1_r_pd" = 0x1, + "flmstr1_r_reserved" = 0x0, + "flmstr1_w_fd" = 0x1, + "flmstr1_w_bios" = 0x1, + "flmstr1_w_me" = 0x1, + "flmstr1_w_gbe" = 0x1, + "flmstr1_w_pd" = 0x1, + "flmstr1_w_reserved" = 0x0, + "flmstr2_requesterid" = 0x0, + "flmstr2_r_fd" = 0x0, + "flmstr2_r_bios" = 0x0, + "flmstr2_r_me" = 0x0, + "flmstr2_r_gbe" = 0x0, + "flmstr2_r_pd" = 0x0, + "flmstr2_r_reserved" = 0x0, + "flmstr2_w_fd" = 0x0, + "flmstr2_w_bios" = 0x0, + "flmstr2_w_me" = 0x0, + "flmstr2_w_gbe" = 0x0, + "flmstr2_w_pd" = 0x0, + "flmstr2_w_reserved" = 0x0, + "flmstr3_requesterid" = 0x218, + "flmstr3_r_fd" = 0x0, + "flmstr3_r_bios" = 0x0, + "flmstr3_r_me" = 0x0, + "flmstr3_r_gbe" = 0x1, + "flmstr3_r_pd" = 0x0, + "flmstr3_r_reserved" = 0x0, + "flmstr3_w_fd" = 0x0, + "flmstr3_w_bios" = 0x0, + "flmstr3_w_me" = 0x0, + "flmstr3_w_gbe" = 0x1, + "flmstr3_w_pd" = 0x0, + "flmstr3_w_reserved" = 0x0, + "flmstr_padding"[0x94] = 0xff, + + "ich0_medisable" = 0x1, + "ich0_reserved0" = 0x4, + "ich0_tcomode" = 0x1, + "ich0_mesmbusaddr" = 0x64, + "ich0_bmcmode" = 0x0, + "ich0_trippointsel" = 0x0, + "ich0_reserved1" = 0x0, + "ich0_integratedgbe" = 0x1, + "ich0_lanphy" = 0x1, + "ich0_reserved2" = 0x0, + "ich0_dmireqiddisable" = 0x0, + "ich0_me2smbusaddr" = 0x0, + "ich1_dynclk_nmlink" = 0x1, + "ich1_dynclk_smlink" = 0x1, + "ich1_dynclk_mesmbus" = 0x1, + "ich1_dynclk_sst" = 0x1, + "ich1_reserved0" = 0x0, + "ich1_nmlink_npostreqs" = 0x1, + "ich1_reserved1" = 0x0, + "ich1_reserved2" = 0x0, + "ichstrap_padding"[0xf8] = 0xff, + "mch0_medisable" = 0x1, + "mch0_mebootfromflash" = 0x0, + "mch0_tpmdisable" = 0x1, + "mch0_reserved0" = 0x7, + "mch0_spifingerprinton" = 0x1, + "mch0_mealtdisable" = 0x0, + "mch0_reserved1" = 0xff, + "mch0_reserved2" = 0xffff, + "mchstrap_padding"[0xcdc] = 0xff, + + "mevscc_jid0" = 0x1720c2, + "mevscc_vscc0" = 0x20052005, + "mevscc_jid1" = 0x1730ef, + "mevscc_vscc1" = 0x20052005, + "mevscc_jid2" = 0x481f, + "mevscc_vscc2" = 0x20152015, + "mevscc_padding"[4] = 0xff, + "mevscc_tablebase" = 0xee, + "mevscc_tablelength" = 0x6, + "mevscc_reserved" = 0x0, + + "oem_magic0" = 0x4c, + "oem_magic1" = 0x49, + "oem_magic2" = 0x42, + "oem_magic3" = 0x45, + "oem_magic4" = 0x52, + "oem_magic5" = 0x41, + "oem_magic6" = 0x54, + "oem_magic7" = 0x45, + "oem_padding"[0xf8] = 0xff +} diff --git a/util/blobtool/ifd-x200.spec b/util/blobtool/ifd-x200.spec new file mode 100644 index 0000000..0cdbb9d --- /dev/null +++ b/util/blobtool/ifd-x200.spec @@ -0,0 +1,187 @@ +# +# Copyright (C) 2014 Steve Shenton <sgsit(a)libreboot.org> +# Copyright (C) 2014, 2015 Leah Rowe <info(a)minifree.org> +# Copyright (C) 2017 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# +# Info on flash descriptor (page 845 onwards): +# +# http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datash… + +# Flash Descriptor SPEC for GM45/ICH9M +{ + # Signature for descriptor mode + "fd_signature" : 32, + + # Flash map registers + "flmap0_fcba" : 8, + "flmap0_nc" : 2, + "flmap0_reserved0" : 6, + "flmap0_frba" : 8, + "flmap0_nr" : 3, + "flmap0_reserved1" : 5, + "flmap1_fmba" : 8, + "flmap1_nm" : 3, + "flmap1_reserved" : 5, + "flmap1_fisba" : 8, + "flmap1_isl" : 8, + "flmap2_fmsba" : 8, + "flmap2_msl" : 8, + "flmap2_reserved" : 16, + + # Component section + "flcomp_density1" : 3, + "flcomp_density2" : 3, + "flcomp_reserved0" : 2, + "flcomp_reserved1" : 8, + "flcomp_reserved2" : 1, + "flcomp_readclockfreq" : 3, + "flcomp_fastreadsupp" : 1, + "flcomp_fastreadfreq" : 3, + "flcomp_w_eraseclkfreq" : 3, + "flcomp_r_statclkfreq" : 3, + "flcomp_reserved3" : 2, + "flill" : 32, + "flbp" : 32, + "comp_padding"[36] : 8, + + # Region section + "flreg0_base" : 13, + "flreg0_reserved0" : 3, + "flreg0_limit" : 13, + "flreg0_reserved1" : 3, + "flreg1_base" : 13, + "flreg1_reserved0" : 3, + "flreg1_limit" : 13, + "flreg1_reserved1" : 3, + "flreg2_base" : 13, + "flreg2_reserved0" : 3, + "flreg2_limit" : 13, + "flreg2_reserved1" : 3, + "flreg3_base" : 13, + "flreg3_reserved0" : 3, + "flreg3_limit" : 13, + "flreg3_reserved1" : 3, + "flreg4_base" : 13, + "flreg4_reserved0" : 3, + "flreg4_limit" : 13, + "flreg4_reserved1" : 3, + "flreg_padding"[12] : 8, + + # Master access section + + # 1: Host CPU/BIOS + "flmstr1_requesterid" : 16, + "flmstr1_r_fd" : 1, + "flmstr1_r_bios" : 1, + "flmstr1_r_me" : 1, + "flmstr1_r_gbe" : 1, + "flmstr1_r_pd" : 1, + "flmstr1_r_reserved" : 3, + "flmstr1_w_fd" : 1, + "flmstr1_w_bios" : 1, + "flmstr1_w_me" : 1, + "flmstr1_w_gbe" : 1, + "flmstr1_w_pd" : 1, + "flmstr1_w_reserved" : 3, + + # 2: ME + "flmstr2_requesterid" : 16, + "flmstr2_r_fd" : 1, + "flmstr2_r_bios" : 1, + "flmstr2_r_me" : 1, + "flmstr2_r_gbe" : 1, + "flmstr2_r_pd" : 1, + "flmstr2_r_reserved" : 3, + "flmstr2_w_fd" : 1, + "flmstr2_w_bios" : 1, + "flmstr2_w_me" : 1, + "flmstr2_w_gbe" : 1, + "flmstr2_w_pd" : 1, + "flmstr2_w_reserved" : 3, + + # 3: GbE + "flmstr3_requesterid" : 16, + "flmstr3_r_fd" : 1, + "flmstr3_r_bios" : 1, + "flmstr3_r_me" : 1, + "flmstr3_r_gbe" : 1, + "flmstr3_r_pd" : 1, + "flmstr3_r_reserved" : 3, + "flmstr3_w_fd" : 1, + "flmstr3_w_bios" : 1, + "flmstr3_w_me" : 1, + "flmstr3_w_gbe" : 1, + "flmstr3_w_pd" : 1, + "flmstr3_w_reserved" : 3, + + "flmstr_padding"[148] : 8, + + # ICHSTRAP0 + "ich0_medisable" : 1, + "ich0_reserved0" : 6, + "ich0_tcomode" : 1, + "ich0_mesmbusaddr" : 7, + "ich0_bmcmode" : 1, + "ich0_trippointsel" : 1, + "ich0_reserved1" : 2, + "ich0_integratedgbe" : 1, + "ich0_lanphy" : 1, + "ich0_reserved2" : 3, + "ich0_dmireqiddisable" : 1, + "ich0_me2smbusaddr" : 7, + + # ICHSTRAP1 + "ich1_dynclk_nmlink" : 1, + "ich1_dynclk_smlink" : 1, + "ich1_dynclk_mesmbus" : 1, + "ich1_dynclk_sst" : 1, + "ich1_reserved0" : 4, + "ich1_nmlink_npostreqs" : 1, + "ich1_reserved1" : 7, + "ich1_reserved2" : 16, + + "ichstrap_padding"[248] : 8, + + # MCHSTRAP0 + "mch0_medisable" : 1, + "mch0_mebootfromflash" : 1, + "mch0_tpmdisable" : 1, + "mch0_reserved0" : 3, + "mch0_spifingerprinton" : 1, + # Alternate disable - allows ME to perform chipset + # init functions but disables FW apps such as AMT + "mch0_mealtdisable" : 1, + "mch0_reserved1" : 8, + "mch0_reserved2" : 16, + + "mchstrap_padding"[3292]: 8, + + # ME VSCC Table + "mevscc_jid0" : 32, + "mevscc_vscc0" : 32, + "mevscc_jid1" : 32, + "mevscc_vscc1" : 32, + "mevscc_jid2" : 32, + "mevscc_vscc2" : 32, + "mevscc_padding"[4] : 8, + + # Descriptor Map 2 Record + "mevscc_tablebase" : 8, + "mevscc_tablelength" : 8, + "mevscc_reserved" : 16, + + # OEM section + "oem_magic"[8] : 8, + "oem_padding"[248] : 8 +}

1 0

Patch set updated for coreboot: mb/intel/d510mo: Add cmos.layout and cmos.default
by Arthur Heymans 21 Jan '17

21 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18143 -gerrit commit 27356666f95a8cb7b8d3f0aa06a72568fcc80c52 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 17:40:18 2017 +0100 mb/intel/d510mo: Add cmos.layout and cmos.default Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/intel/d510mo/Kconfig | 2 + src/mainboard/intel/d510mo/cmos.default | 6 ++ src/mainboard/intel/d510mo/cmos.layout | 98 +++++++++++++++++++++++++++++++++ 3 files changed, 106 insertions(+) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 7184665..7131b3a 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -25,6 +25,8 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_1024 select MAINBOARD_HAS_NATIVE_VGA_INIT select INTEL_INT15 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/cmos.default b/src/mainboard/intel/d510mo/cmos.default new file mode 100644 index 0000000..488aa37 --- /dev/null +++ b/src/mainboard/intel/d510mo/cmos.default @@ -0,0 +1,6 @@ +boot_option=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +gfx_uma_size=8M diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout new file mode 100644 index 0000000..3e96412 --- /dev/null +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -0,0 +1,98 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: bootloader +416 512 s 0 boot_devices + +# coreboot config options: cpu +944 1 e 2 hyper_threading +#945 7 r 0 unused + +# coreboot config options: northbridge +952 3 e 11 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M + +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984

1 0

Patch set updated for coreboot: nb/intel/pineview: Make preallocated igd memory a cmos parameter
by Arthur Heymans 21 Jan '17

21 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18142 -gerrit commit 1c7ac6f2d3f8ef9e1ac993062add032cfb62c85a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 17:32:20 2017 +0100 nb/intel/pineview: Make preallocated igd memory a cmos parameter Change-Id: Ia7fa2c290e540ff779cf8dc16147db5a248021e2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/pineview/early_init.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 842ffa1..46e78bb 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -25,6 +25,7 @@ #include <string.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> +#include <pc80/mc146818rtc.h> #define LPC PCI_DEV(0, 0x1f, 0) #define D0F0 PCI_DEV(0, 0, 0) @@ -45,7 +46,16 @@ static void early_graphics_setup(void) const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); - pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */ + + /* vram size from cmos option */ + if (get_option(&reg8, "gfx_uma_size") != CB_SUCCESS) + reg8 = 0; /* 0 for 8MB */ + /* make sure no invalid setting is used */ + if (reg8 > 8) + reg8 = 0; + /* Select 1M GTT */ + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) + | ((reg8 + 3) << 4)); printk(BIOS_SPEW, "Set GFX clocks..."); reg16 = MCHBAR16(MCH_GCFGC);

1 0

Patch set updated for coreboot: nb/intel/x4x: Implement resume from S3 suspend
by Arthur Heymans 21 Jan '17

21 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17998 -gerrit commit 4766fd046ef5f29befd09a38963b4eaedfd2ffb9 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Dec 30 21:07:18 2016 +0100 nb/intel/x4x: Implement resume from S3 suspend It rewrites the results of receive enable stored in the upper nvram region, to avoid running receive enable again. Some debug info is also printed about the self-refresh registers. (Not enforcing a reset here, since 0 does not necessarily mean it's not in self-refresh). Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 ++-- src/northbridge/intel/x4x/pcie.c | 15 +++++++-- src/northbridge/intel/x4x/raminit_ddr2.c | 44 ++++++++++++++++++-------- src/northbridge/intel/x4x/x4x.h | 2 +- 5 files changed, 51 insertions(+), 18 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 3d2a892..ae57e5b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -33,6 +33,7 @@ config BOARD_SPECIFIC_OPTIONS select REALTEK_8168_RESET select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index d76fbb2..0a1470b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -132,6 +132,7 @@ void mainboard_romstage_entry(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; u8 boot_path = 0; + u8 s3_resume; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -151,16 +152,18 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + s3_resume = southbridge_detect_s3_resume(); + if (s3_resume) + boot_path = BOOT_PATH_RESUME; if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); - cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); - x4x_late_init(); + x4x_late_init(s3_resume); printk(BIOS_DEBUG, "x4x late init complete\n"); diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c index f03869e..648f10d 100644 --- a/src/northbridge/intel/x4x/pcie.c +++ b/src/northbridge/intel/x4x/pcie.c @@ -18,10 +18,11 @@ #include <stddef.h> #include <string.h> #include <arch/io.h> +#include <cbmem.h> #include <device/pci_def.h> #include <device/pnp_def.h> #include <console/console.h> - +#include <romstage_handoff.h> #include "iomap.h" #include "x4x.h" @@ -184,8 +185,18 @@ static void init_dmi(void) reg16 = DMIBAR16(0x88); } -void x4x_late_init(void) +static void x4x_prepare_resume(int s3resume) +{ + int cbmem_was_initted; + + cbmem_was_initted = !cbmem_recovery(s3resume); + + romstage_handoff_init(cbmem_was_initted && s3resume); +} + +void x4x_late_init(int s3resume) { init_egress(); init_dmi(); + x4x_prepare_resume(s3resume); } diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 4de29cf..30831ac 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -262,6 +262,16 @@ static void clkcross_ddr2(struct sysinfo *s) static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; + u32 pmsts = MCHBAR32(PMSTS_MCHBAR); + + if (s->boot_path >= 1) { + if (!(pmsts & 1)) + printk(BIOS_DEBUG, + "Channel 0 possibly not in self refresh\n"); + if (!(pmsts & 2)) + printk(BIOS_DEBUG, + "Channel 1 possibly not in self refresh\n"); + } pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); @@ -1476,7 +1486,6 @@ static void rcven_ddr2(struct sysinfo *s) readdelay[ch] = MCHBAR16(0x400*ch + 0x588); } // END EACH POPULATED CHANNEL - /* TODO: Resume support using this */ FOR_EACH_CHANNEL(ch) { for (lane = 0; lane < 8; lane++) { MCHBAR8(0x400*ch + 0x560 + (lane*4)) = @@ -1556,7 +1565,8 @@ static void sdram_program_receive_enable(struct sysinfo *s) RCBA32(0x3400) = (1 << 2); /* Program Receive Enable Timings */ - if (s->boot_path == BOOT_PATH_WARM_RESET) { + if ((s->boot_path == BOOT_PATH_WARM_RESET) + || (s->boot_path == BOOT_PATH_RESUME)) { sdram_recover_receive_enable(); } else { rcven_ddr2(s); @@ -2044,7 +2054,8 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - jedec_ddr2(s); + if (s->boot_path == BOOT_PATH_NORMAL) + jedec_ddr2(s); printk(BIOS_DEBUG, "Done jedec steps\n"); @@ -2091,16 +2102,23 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; // Dummy writes / reads - volatile u32 data; - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - for (bank = 0; bank < 4; bank++) { - reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); - write32((u32 *)reg32, 0xffffffff); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); - write32((u32 *)reg32, 0x00000000); - data = read32((u32 *)reg32); - printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + if (s->boot_path == BOOT_PATH_NORMAL) { + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | + (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote ones"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + printk(BIOS_DEBUG, "Wrote zeros"); + printk(BIOS_DEBUG, "Read: [0x%08x]=0x%08x\n", + reg32, data); + } } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 66d765a..faae775 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -322,7 +322,7 @@ enum ddr2_signals { #ifndef __BOOTBLOCK__ void x4x_early_init(void); -void x4x_late_init(void); +void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u8 decode_pciebar(u32 *const base, u32 *const len);

1 0

← Newer
1
...
25
26
27
28
29
30
31
...
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2017