coreboot-gerrit January 2017

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Patch merged into coreboot/master: google/eve: Enable separate recovery MRC cache
by gerrit＠coreboot.org 22 Jan '17

22 Jan '17

the following patch was just integrated into master: commit e00365217cf30c7b8510fca0e7e60d0905b73752 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:57:57 2017 -0800 google/eve: Enable separate recovery MRC cache In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18199 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Include I2C code in romstage
by gerrit＠coreboot.org 22 Jan '17

22 Jan '17

the following patch was just integrated into master: commit 4234ca276419314a0df598c7375c683def67ab1a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:55:03 2017 -0800 soc/intel/skylake: Include I2C code in romstage The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/18198 for details. -gerrit

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Patch merged into coreboot/master: google/eve: Enable keyboard backlight in bootblock
by gerrit＠coreboot.org 22 Jan '17

22 Jan '17

the following patch was just integrated into master: commit 367c9b328fd084509f8ed41ecf3c64ebc2e02e17 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 15:42:26 2017 -0800 google/eve: Enable keyboard backlight in bootblock Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18197 for details. -gerrit

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Patch set updated for coreboot: soc/intel/skylake: Include I2C code in romstage
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18198 -gerrit commit 8ad1b37b3a67ca9bf125b9728190f7a672453ab7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:55:03 2017 -0800 soc/intel/skylake: Include I2C code in romstage The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3a474e7..4b6fcfc 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -38,6 +38,7 @@ verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c +romstage-y += bootblock/i2c.c romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c

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New patch to review for coreboot: google/eve: Fixes for devicetree settings
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18200 -gerrit commit 6d30cc0a085b9935a3beed9e9185708d6ec7fcb6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 19:11:37 2017 -0800 google/eve: Fixes for devicetree settings The devicetree settings were incorrect in a few places with respect to the SOC and board design: - IMVP8 VR workaround is for MP2939 and not MP2949 on Eve - IccMax values are incorrect according to KBL-Y EDS - USB2[6] is incorrectly labeled - I2C touch devices do not need probed as they are not optional - PCIe Root Port 5 should be enabled - I2C5 device should not be enabled as it is unused BUG=chrome-os-partner:58666 TEST=manually tested on Eve board Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/devicetree.cb | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 6e709b7..d619d60 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -51,7 +51,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "SendVrMbxCmd" = "1" # IMVP8 workaround register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -73,7 +72,7 @@ chip soc/intel/skylake #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| IccMax | 4A | 24A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | #+----------------+-------+-------+-------------+-------------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ @@ -85,7 +84,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .icc_max = VR_CFG_AMP(4), .voltage_limit = 1520, }" @@ -98,7 +97,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" @@ -111,7 +110,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" @@ -124,7 +123,7 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" @@ -137,28 +136,31 @@ chip soc/intel/skylake .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, }" - # Enable Root port 1. + # Enable Root port 1 with SRCCLKREQ1# register "PcieRpEnable[0]" = "1" - # Enable CLKREQ# register "PcieRpClkReqSupport[0]" = "1" - # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" + # Enable Root port 5 with SRCCLKREQ4# + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # H1 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Empty register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2 - register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty - register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # TPM @@ -204,7 +206,6 @@ chip soc/intel/skylake register "generic.cid" = "PNP0C50_CID" register "generic.desc" = "WCOM_DT_DESC" register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x1" device i2c 0a on end end @@ -221,7 +222,6 @@ chip soc/intel/skylake register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""Touchpad"" register "generic.irq" = "IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x0" device i2c 49 on end end @@ -234,7 +234,7 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 off end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi @@ -245,7 +245,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8

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Patch set updated for coreboot: google/eve: Enable separate recovery MRC cache
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18199 -gerrit commit ddaba2ddbe73b6497c0a24f7a43a733a3a22ea78 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:57:57 2017 -0800 google/eve: Enable separate recovery MRC cache In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 2 ++ src/mainboard/google/eve/chromeos.fmd | 31 ++++++++++++++++++------------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 32c029d..e83e7d9 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -18,7 +18,9 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES + select HAS_RECOVERY_MRC_CACHE select LID_SWITCH + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config DRIVERS_I2C_GENERIC def_bool y diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 58b6127..bdadcf7 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -4,24 +4,29 @@ FLASH@0xff000000 0x1000000 { SI_ME@0x1000 0x1ff000 } SI_BIOS@0x200000 0xe00000 { - RW_SECTION_A@0x0 0x3f0000 { + RW_SECTION_A@0x0 0x3e8000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 + RW_FWID_A@0x3e7fc0 0x40 } - RW_SECTION_B@0x3f0000 0x3f0000 { + RW_SECTION_B@0x3e8000 0x3e8000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 + RW_FWID_B@0x3e7fc0 0x40 } - RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG@0x7f0000 0x4000 - RW_SHARED@0x7f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_MISC@0x7d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - RW_VPD@0x7f8000 0x2000 - RW_NVRAM@0x7fa000 0x6000 RW_LEGACY(CBFS)@0x800000 0x200000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000

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Patch set updated for coreboot: soc/intel/skylake: Include I2C code in romstage
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18198 -gerrit commit 029c12001071eaa9a04e4d1e70fffc233c8806ad Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:55:03 2017 -0800 soc/intel/skylake: Include I2C code in romstage The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compile in normal use, but when I was adding some I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3a474e7..4b6fcfc 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -38,6 +38,7 @@ verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c +romstage-y += bootblock/i2c.c romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c

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Patch set updated for coreboot: google/eve: Enable keyboard backlight in bootblock
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18197 -gerrit commit 2f7cefaa30246099710bb572eba20072dc1501fd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 15:42:26 2017 -0800 google/eve: Enable keyboard backlight in bootblock Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/bootblock.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c index 2c524f4..baca9c8 100644 --- a/src/mainboard/google/eve/bootblock.c +++ b/src/mainboard/google/eve/bootblock.c @@ -14,9 +14,13 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <bootblock_common.h> +#include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/pm.h> #include "gpio.h" static void early_config_gpio(void) @@ -26,5 +30,12 @@ static void early_config_gpio(void) void bootblock_mainboard_init(void) { + uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS); + + /* Turn on keyboard backlight to indicate we are booting */ + if ((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) != ACPI_S3)) + google_chromeec_kbbacklight(75); + early_config_gpio(); }

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New patch to review for coreboot: google/eve: Enable separate recovery MRC cache
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18199 -gerrit commit a6f759eecf1ff7b8c21beba207d9f06b7570033b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:57:57 2017 -0800 google/eve: Enable separate recovery MRC cache In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 2 ++ src/mainboard/google/eve/chromeos.fmd | 31 ++++++++++++++++++------------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 32c029d..e83e7d9 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -18,7 +18,9 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES + select HAS_RECOVERY_MRC_CACHE select LID_SWITCH + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config DRIVERS_I2C_GENERIC def_bool y diff --git a/src/mainboard/google/eve/chromeos.fmd b/src/mainboard/google/eve/chromeos.fmd index 58b6127..bdadcf7 100644 --- a/src/mainboard/google/eve/chromeos.fmd +++ b/src/mainboard/google/eve/chromeos.fmd @@ -4,24 +4,29 @@ FLASH@0xff000000 0x1000000 { SI_ME@0x1000 0x1ff000 } SI_BIOS@0x200000 0xe00000 { - RW_SECTION_A@0x0 0x3f0000 { + RW_SECTION_A@0x0 0x3e8000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x3dffc0 - RW_FWID_A@0x3effc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x3d7fc0 + RW_FWID_A@0x3e7fc0 0x40 } - RW_SECTION_B@0x3f0000 0x3f0000 { + RW_SECTION_B@0x3e8000 0x3e8000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x3dffc0 - RW_FWID_B@0x3effc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x3d7fc0 + RW_FWID_B@0x3e7fc0 0x40 } - RW_MRC_CACHE@0x7e0000 0x10000 - RW_ELOG@0x7f0000 0x4000 - RW_SHARED@0x7f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_MISC@0x7d0000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 } - RW_VPD@0x7f8000 0x2000 - RW_NVRAM@0x7fa000 0x6000 RW_LEGACY(CBFS)@0x800000 0x200000 WP_RO@0xa00000 0x400000 { RO_VPD@0x0 0x4000

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New patch to review for coreboot: soc/intel/skylake: Include I2C code in romstage
by Duncan Laurie 22 Jan '17

22 Jan '17

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18198 -gerrit commit 5283cc366e7cbf2eda6e95aa022f7bb86aa28c48 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jan 21 16:55:03 2017 -0800 soc/intel/skylake: Include I2C code in romstage The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compile in normal use, but when I was adding some I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 3a474e7..4b6fcfc 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -38,6 +38,7 @@ verstage-y += spi.c romstage-y += flash_controller.c romstage-y += gpio.c +romstage-y += bootblock/i2c.c romstage-y += memmap.c romstage-y += monotonic_timer.c romstage-y += me.c

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coreboot-gerrit January 2017