coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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1340 discussions

New patch to review for coreboot: lenovo/t60: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16405 -gerrit commit 821f1e75b8782039ad22f302531cafb4ac101eca Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:12:20 2016 +0200 lenovo/t60: transition away from device_t Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/lenovo/t60/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3ed6afd..d3cd90c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -95,7 +95,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0);

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New patch to review for coreboot: arch/acpi.h: add #if guard to handle the absence of device_t type
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16404 -gerrit commit b51c0392c91c50dae5332b706ba56d09d637fc0d Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:08:01 2016 +0200 arch/acpi.h: add #if guard to handle the absence of device_t type Avoid the inclusion of a function declaration if the argument type device_t is not defined. This was not a problem until now because the old declaration of device_t and the new one overlapped. Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/arch/x86/include/arch/acpi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 21dae08..a30c5f1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -606,7 +606,7 @@ void acpi_create_slit(acpi_slit_t *slit, void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);

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New patch to review for coreboot: southbridge/intel/i82801ix: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16403 -gerrit commit 610d9d29fc5b7c2f83edd71c21f18228a6075b99 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Sep 1 17:04:14 2016 +0200 southbridge/intel/i82801ix: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801ix. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ibf20e6c08994b09d2a2e68a1a1d38a7a477493aa Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801ix/early_init.c | 2 +- src/southbridge/intel/i82801ix/early_smbus.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 3d94b56..c40f9b7 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -19,7 +19,7 @@ void i82801ix_early_init(void) { - const device_t d31f0 = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); /* Set up RCBA. */ pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1); diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 3cac32f..31b33e9 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -24,7 +24,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3);

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New patch to review for coreboot: northbridge/intel/gm45: transation away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16402 -gerrit commit f8914b36e15500bf80a1536361261bf9aca35eb2 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Aug 29 22:51:41 2016 -0700 northbridge/intel/gm45: transation away from device_t Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/gm45/early_init.c | 2 +- src/northbridge/intel/gm45/gm45.h | 2 +- src/northbridge/intel/gm45/igd.c | 12 ++++++------ src/northbridge/intel/gm45/iommu.c | 4 ++-- src/northbridge/intel/gm45/pcie.c | 8 ++++---- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index ee2a6ec..c2e4aea 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -19,7 +19,7 @@ void gm45_early_init(void) { - const device_t d0f0 = PCI_DEV(0, 0, 0); + const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index c018321..5a30f87 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -434,7 +434,7 @@ u32 decode_igd_gtt_size(u32 gsm); void init_iommu(void); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp; diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c index dc0cc91..73f7651 100644 --- a/src/northbridge/intel/gm45/igd.c +++ b/src/northbridge/intel/gm45/igd.c @@ -30,9 +30,9 @@ /* The PEG settings have to be set before ASPM is setup on DMI. */ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) { - const device_t mch_dev = PCI_DEV(0, 0, 0); - const device_t peg_dev = PCI_DEV(0, 1, 0); - const device_t igd_dev = PCI_DEV(0, 2, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0); + const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0); u16 reg16; u32 reg32; @@ -110,7 +110,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) static void disable_igd(const sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); printk(BIOS_DEBUG, "Disabling IGD.\n"); @@ -131,7 +131,7 @@ static void disable_igd(const sysinfo_t *const sysinfo) void init_igd(const sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) @@ -142,7 +142,7 @@ void init_igd(const sysinfo_t *const sysinfo) void igd_compute_ggc(sysinfo_t *const sysinfo) { - const device_t mch_dev = PCI_DEV(0, 0, 0); + const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0); const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 10548f4..98e488c 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,7 +46,7 @@ void init_iommu() /* clear GTT */ u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); if (gtt & 0x400) { /* VT mode */ - device_t igd = PCI_DEV(0, 2, 0); + pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */ u8 cmd = pci_read_config8(igd, PCI_COMMAND); @@ -65,7 +65,7 @@ void init_iommu() if (stepping == STEPPING_B3) { MCHBAR8(0xffc) |= 1 << 4; - device_t peg = PCI_DEV(0, 1, 0); + pci_devfn_t peg = PCI_DEV(0, 1, 0); /* FIXME: proper test? */ if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { int val = pci_read_config32(peg, 0xfc) | (1 << 15); diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index cc1fde7..3f56b94 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -112,8 +112,8 @@ static void init_pcie(const int peg_enabled, u8 tmp8; u16 tmp16; u32 tmp; - const device_t mch = PCI_DEV(0, 0, 0); - const device_t pciex = PCI_DEV(0, 1, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t pciex = PCI_DEV(0, 1, 0); printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, peg_enabled?"enabled":"disabled", @@ -162,7 +162,7 @@ static void init_pcie(const int peg_enabled, static void setup_aspm(const stepping_t stepping, const int peg_enabled) { u32 tmp32; - const device_t pciex = PCI_DEV(0, 1, 0); + const pci_devfn_t pciex = PCI_DEV(0, 1, 0); /* Prerequisites for ASPM: */ if (peg_enabled) { @@ -327,7 +327,7 @@ static void setup_rcrb(const int peg_enabled) void gm45_late_init(const stepping_t stepping) { - const device_t mch = PCI_DEV(0, 0, 0); + const pci_devfn_t mch = PCI_DEV(0, 0, 0); const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled);

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New patch to review for coreboot: southbridge/amd/agesa/hudson: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16401 -gerrit commit 6fdb034cbd8ee406d008c20ff25b705272000c11 Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Sep 1 16:50:42 2016 +0200 southbridge/amd/agesa/hudson: transition away from device_t Replace the use of the old device_t definition inside southbridge/amd/agesa/hudson. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/agesa/hudson/hudson.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 57119f9..1cdaa05 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -28,7 +28,7 @@ void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -73,7 +73,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 92058c6..d870845 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -70,7 +70,7 @@ u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void);

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Patch set updated for coreboot: southbridge/intel/i82801gx: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16370 -gerrit commit 8938e9fd763f1ea1bb3d9fee8be771ab083d7012 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:05:32 2016 +0200 southbridge/intel/i82801gx: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 2 ++ src/southbridge/intel/i82801gx/smihandler.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 2f9cdeb..47fe5f6 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d4adc18..48b9d3b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -43,7 +43,9 @@ #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" +#if !defined(__SIMPLE_DEVICE__) extern void i82801gx_enable(device_t dev); +#endif void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index d3867a5..c6425db 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -276,7 +276,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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New patch to review for coreboot: google/reef: Set up GPIO_TIER1_SCI_EN properly
by Shaunak Saha 02 Sep '16

02 Sep '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16400 -gerrit commit 142dc5a3eb64aa944d5afbc0a95bbcbf2bc2e09c Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Thu Sep 1 22:27:15 2016 -0700 google/reef: Set up GPIO_TIER1_SCI_EN properly Previously we were setting the gpio_tier1_sci in smihandler before going to S3. But this won't work for S0iX as it happens from kernel and smi handler is not involved in that flow. We need to set this bit i.e. bit 15 in acpi gpe0a register at 0x430h. Kernel before going to sleep checks what values are passed through asl as wake events(through _PRW) ,keeps those enabled only and clears other bits in gpe0 enable registers. So we need to inform kernel to keep gpio_tier_sci also set as these is needed for any wake. This patch adds a _PRW method to powerbutton asl code. We can use the _PRW method of powerbutton. The reason of choosing powerbutton is its the default wake source and does not need any _PRW method defined and we cannot define more than one _PRW for any other wake source. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen,powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: Ia9a96f2923bb1720b2fa6eab66832551134c6bea Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/acpi/mainboard.asl | 1 + src/mainboard/google/reef/gpio.h | 6 ++++++ src/mainboard/google/reef/smihandler.c | 3 --- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 9665bb2..4111635 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -31,6 +31,7 @@ Scope (\_SB) Device (PWRB) { Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package() { GPIO_TIER_1_SCI_EN, 0x3 }) } } diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index dbe7062..44bdca4 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -21,6 +21,12 @@ /* Input device interrupt configuration */ #define TOUCHPAD_INT GPIO_18_IRQ +/* + * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event + * and/or an SCI or SMI#. + */ +#define GPIO_TIER_1_SCI_EN 15 + #define BOARD_HP_MIC_CODEC_IRQ GPIO_116_IRQ #define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c index d33222b..d3d6b2b 100644 --- a/src/mainboard/google/reef/smihandler.c +++ b/src/mainboard/google/reef/smihandler.c @@ -33,9 +33,6 @@ void mainboard_smi_sleep(u8 slp_typ) { gpio_configure_pads(sleep_gpio_table, ARRAY_SIZE(sleep_gpio_table)); - if (slp_typ == ACPI_S3) - enable_gpe(GPIO_TIER_1_SCI); - if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);

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Patch set updated for coreboot: soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL
by Vaibhav Shankar 02 Sep '16

02 Sep '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16349 -gerrit commit 7eaf702fa6c92dff4dbf97e4f1ef095782799766 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 29 14:03:38 2016 -0700 soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL Implement a macro to calculate DW0 register address. Added GPIO methods to configure DW0 and DW1 registers. Added GNVS variable for PERST_0. BUG=chrome-os-partner:55877 Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/globalnvs.asl | 1 + src/soc/intel/apollolake/acpi/gpiolib.asl | 73 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 5 ++ src/soc/intel/apollolake/include/soc/nvs.h | 3 +- 4 files changed, 81 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 404f36c..faff8df 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -38,6 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GPEI, 64, // 0x11 - 0x18 - GPE Wake Source NHLA, 64, // 0x19 - 0x20 - NHLT Address NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRAD, 32, // 0x25 - 0x28 - PERST_0 Address /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl new file mode 100644 index 0000000..f31f83e --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) +{ + + /* Get Pad Configuration DW0 register value */ + Method (GPC0, 0x1, Serialized) + { + /* Arg0 - GpioCommunity_Address + PadCfgBase_Address + PadCommunityPin_Address */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, + Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Pad Configuration DW0 register value */ + Method (SPC0, 0x2, Serialized) + { + /* Arg0 - GpioCommunity_Address + PadCfgBase_Address + PadCommunityPin_Address */ + /* Arg1 - Value for DW0 register */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, + Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } + + /* Get Pad Configuration DW1 register value */ + Method (GPC1, 0x1, Serialized) + { + /* Arg0 = GpioCommunity_Address + PadCfgBase_Address + PadCommunityPin_Address + 0x4 */ + Store ( Add ( Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, + Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field (PDW1, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + + /* Set Pad Configuration DW1 register value */ + Method (SPC1, 0x2, Serialized) + { + /* Arg0 - GpioCommunity_Address + PadCfgBase_Address + PadCommunityPin_Address + 0x4 */ + /* Arg1 - Value for DW1 register */ + Store ( Add ( Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, + Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } +} diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 70f86ca..89530fd 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -426,6 +426,11 @@ #define PAD_W(pad) (pad - W_OFFSET) #define PAD_SW(pad) (pad - SW_OFFSET) +/* calculate GPIO DW0 register address */ +#define PAD_IOSF_MMIO(community, pin) \ + ((GPIO_##community << 16) | \ + (PAD_CFG_BASE | PAD_##community(pin) * 8)) + /* Linux names of the GPIO devices. */ #define GPIO_COMM_N_NAME "INT3452:00" #define GPIO_COMM_NW_NAME "INT3452:01" diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index bff949e..26e1c49 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -38,7 +38,8 @@ typedef struct global_nvs_t { uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint8_t unused[219]; + uint32_t prad; /* 0x25 - 0x28 - PERST_0 Address */ + uint8_t unused[215]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: mainboard/intel/amenia: Configure PERST_0 pin and GNVS
by Vaibhav Shankar 02 Sep '16

02 Sep '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16350 -gerrit commit 2e40d4fa7cc583d67685e4f516b1dc17b656ca3a Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Fri Aug 26 19:10:21 2016 -0700 mainboard/intel/amenia: Configure PERST_0 pin and GNVS Configured PERST_0 and assigned its address to GNVS varibale. BUG=chrome-os-partner:55877 Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/mainboard/intel/amenia/gpio.h | 2 +- src/mainboard/intel/amenia/mainboard.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 4a4d08f..3eb4103 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -223,7 +223,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPIO_119, DN_20K), /* GP_SSP_2_FS0 */ PAD_NC(GPIO_120, DN_20K), /* GP_SSP_2_FS1 */ PAD_NC(GPIO_121, DN_20K), /* GP_SSP_2_FS2 */ - PAD_NC(GPIO_122, DN_20K), /* GP_SSP_2_RXD */ + PAD_CFG_GPO(GPIO_122, 0, DEEP), /* WIFI PERST_0 */ PAD_NC(GPIO_123, DN_20K), /* GP_SSP_2_TXD */ /** end of North West Community */ /** North Community */ diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 6ec5b98..bbf6381 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -19,9 +19,14 @@ #include <console/console.h> #include <device/device.h> #include <soc/nhlt.h> +#include <soc/nvs.h> +#include <cbmem.h> #include "ec.h" #include "gpio.h" +#define PERST_0 GPIO_122 + + static void mainboard_init(void *chip_info) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); @@ -67,7 +72,26 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { + global_nvs_t *gnvs; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + /* assign PERST_0 address to GNVS */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (!gnvs) { + printk(BIOS_ERR, "PERST GNVS not located \n"); + return; + } + + if (!gnvs) { + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); + printk(BIOS_ERR, "Created GNVS for PERST \n"); + } + + if(gnvs) { + gnvs->prad = PAD_IOSF_MMIO(NW, PERST_0 ); + printk(BIOS_ERR, "Assigned PERST address to GNVS \n"); + } } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: soc/intel/apollolake: Add PM methods to power gate PCIe
by Vaibhav Shankar 02 Sep '16

02 Sep '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16351 -gerrit commit d3edc1573ab98067187b368ff13eacd344c86df1 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Tue Aug 23 17:56:17 2016 -0700 soc/intel/apollolake: Add PM methods to power gate PCIe Implement _ON/_OFF methods to power gate PCIe during S0ix entry.Added PERST_0 assertion/de-assertion methods. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 25 ++++++ src/soc/intel/apollolake/acpi/pcie.asl | 112 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 3 files changed, 140 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 03b8edd..c514ec2 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ #include <soc/gpio_defs.h> +#include "gpiolib.asl" scope (\_SB) { @@ -141,6 +142,30 @@ scope (\_SB) { Return(0xf) } } + + /* PERST Assertion */ + Method (PRAS, 0x0, Serialized) + { + /* + * Assert PERST + * local1 - to toggle Tx pin of Dw0 + */ + Store (\_SB.GPC0(\PRAD), Local1) + Or (Local1, 0x1 , Local1) + \_SB.SPC0 (\PRAD, Local1) + } + + /* PERST DE-Assertion */ + Method (PRDA, 0x0, Serialized) + { + /* + * De-assert PERST + * local1 - to toggle Tx pin of Dw0 + */ + Store (\_SB.GPC0 (\PRAD), Local1) + And (Local1, 0xFFFFFFFE , Local1) + \_SB.SPC0 (\PRAD, Local1) + } } Scope(\_GPE) diff --git a/src/soc/intel/apollolake/acpi/pcie.asl b/src/soc/intel/apollolake/acpi/pcie.asl new file mode 100644 index 0000000..f5384be --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pcie.asl @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (RP01) +{ + Name (_ADR, 0x00140000) + Name (_DDN, "PCIe-B 0") + Name (PDST, 0) /* present Detect status */ + + /* lowest D-state supported by + * PCIe root port during S0 state + */ + Name (_S0W, 4) + + /* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ + OperationRegion(PX02, PCI_Config, 0x0, 0x380) + Field(PX02,AnyAcc, NoLock, Preserve) + { + Offset(0x5A), /* SLSTS- SLot status Register */ + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, + Offset(0x338), + , 26, + BDQA, 1 /* BLKDQDA */ + } + + + PowerResource (PXP, 0, 0) + { + /* Define the PowerResource for PCIe slot */ + Method (_STA, 0, Serialized) + { + Store (PDS, PDST) + If (LEqual (PDS, 1)) { + Return (0xf) + } Else { + Return (0) + } + } + + Method (_ON, 0, Serialized) /* Turn on core power to PCIe Slot */ + { + If (LEqual (PDST, 1)) { + /* enter this condition if device is connected */ + /* De-assert PERST */ + \_SB.PRDA() + + Store (0, BDQA) /* Set BLKDQDA to 0 */ + Store (0, BPLL) /* Set BLKPLLEN to 0 */ + /* Set L23_Rdy to Detect Transition (L23R2DT) */ + Store (1, L23R) + Sleep (16) + Store (0, Local0) + /* Delay for transition Detect and link to train */ + While (L23R) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + } /* End PDS condition check */ + } + + Method (_OFF, 0, Serialized) /* Turn off core power to PCIe Slot */ + { + /* Set L23_Rdy Entry Request (L23ER) */ + If (LEqual (PDST, 1)) { + /* enter this condition if device is connected */ + Store (1, L23E) + Sleep (16) /* Delay for Link to transition */ + Store (0, Local0) + While (L23E) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + Store (1, BDQA) /* Set BLKDQDA to 1 */ + Store (1, BPLL) /* Set BLKPLLEN to 1 */ + + /* Assert PERST */ + \_SB.PRAS() + } /* End PDS condition check */ + } /* End of Method_OFF */ + } /* End PXP */ + + Name(_PR0, Package() { PXP }) + Name(_PR3, Package() { PXP }) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 391a531..d7ced0f 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,9 @@ #include <soc/gpe.h> +/* PCIE device */ +#include "pcie.asl" + /* LPSS device */ #include "lpss.asl"

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coreboot-gerrit September 2016