coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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1340 discussions

New patch to review for coreboot: Makefile.inc: Use $(MAINBOARDDIR)
by Iru Cai 02 Sep '16

02 Sep '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16410 -gerrit commit 3702e9db60a27fff7bb9171becb9b5138567bdec Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Sep 2 16:37:39 2016 +0800 Makefile.inc: Use $(MAINBOARDDIR) Commit 93ef3ff makes the following only print the part number when the ROM is built. In Makefile.inc, $(MAINBOARDDIR) is the variable that has the quotes stripped off from $(CONFIG_MAINBOARD_DIR), so use it instead of $(MAINBOARD_DIR). build_complete:: coreboot printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \ $(CONFIG_MAINBOARD_PART_NUMBER) Change-Id: I729a583182937db7a926eb75aa28dfb53360046c Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- Makefile.inc | 2 +- src/soc/intel/braswell/Makefile.inc | 2 +- src/soc/intel/skylake/Makefile.inc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 6225152..0caab91 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -60,7 +60,7 @@ coreboot: build-dirs $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ # targets after the build completes by creating a Makefile.inc in the # site-local directory with a target named 'build_complete::' build_complete:: coreboot - printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \ + printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) \ $(CONFIG_MAINBOARD_PART_NUMBER) # This target can be used to run rules after all files were added to CBFS, diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index cfa5b4c..abd64a5 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -57,7 +57,7 @@ CPPFLAGS_common += -I$(src)/soc/intel/braswell/ CPPFLAGS_common += -I$(src)/soc/intel/braswell/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/braswell -CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) ifneq ($(CONFIG_GOP_SUPPORT),y) ifneq ($(CONFIG_VGA_BIOS_FILE),) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index aa3da61..d688747 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -107,7 +107,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake endif # Currently used for microcode path. -CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARDDIR) ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2

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Patch set updated for coreboot: northbridge/intel/sandybridge: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16409 -gerrit commit ca86ac5ec8ddd368a7dbf5573aa5cca3c73097a4 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:17:26 2016 +0200 northbridge/intel/sandybridge: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/sandybridge/sandybridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..972ed9f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -234,7 +234,7 @@ void mainboard_config_superio(void); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp;

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Patch set updated for coreboot: southbridge/intel/bd82x6x: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16407 -gerrit commit c3ee33200fb63f92c50850cc14f37d54e5de12ea Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:14:39 2016 +0200 southbridge/intel/bd82x6x: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/bd82x6x. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/pch.c | 10 ++++++---- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 2b174c7..9f74fdd 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index b2fbd69..a5c63b6 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -38,7 +38,7 @@ static uint16_t read16p (uintptr_t addr) which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 974abb1..51fdd2e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -30,11 +30,12 @@ int pch_silicon_revision(void) { static int pch_revision_id = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif @@ -46,11 +47,12 @@ int pch_silicon_revision(void) int pch_silicon_type(void) { static int pch_type = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f22fed5..1977c8f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,7 +66,7 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#if !defined(__SMM__) +#if !defined(__SIMPLE_DEVICE__) #include "chip.h" void pch_enable(device_t dev); #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 0478285..71ebb6e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -278,7 +278,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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Patch set updated for coreboot: device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16369 -gerrit commit f8771c3d2283e7fe0efd49e8ff790cae428a5571 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:18:06 2016 +0200 device/pci.h: change #ifdef argument to __SIMPLE_DEVICE__ Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__ in order to account for the coreboot stages that do not define device_t and are not __PRE_RAM__ (i.e. smm) device_t Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/include/device/pci.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 9ef3614..e167752 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -108,13 +108,13 @@ static inline const struct pci_operations *ops_pci(device_t dev) #endif /* ! __SIMPLE_DEVICE__ */ -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base);

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Patch set updated for coreboot: arch/acpi.h: add #if guard to handle the absence of device_t type
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16404 -gerrit commit ed991af4d17e7a5ea80a64562cc787c99df02369 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:08:01 2016 +0200 arch/acpi.h: add #if guard to handle the absence of device_t type Avoid the inclusion of a function declaration if the argument type device_t is not defined. This was not a problem until now because the old declaration of device_t and the new one overlapped. Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/arch/x86/include/arch/acpi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 21dae08..a30c5f1 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -606,7 +606,7 @@ void acpi_create_slit(acpi_slit_t *slit, void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);

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Patch set updated for coreboot: northbridge/intel/i945: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16371 -gerrit commit 5208d9ea1ecd933c4fdf2374633018f62c2bdd25 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:11:24 2016 +0200 northbridge/intel/i945: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 5b6c87a..6228d63 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) {

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New patch to review for coreboot: northbridge/intel/sandybridge: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16409 -gerrit commit 2ba34e5dc9a3e1996fda3238d8d6bbb4ff36b8cb Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:17:26 2016 +0200 northbridge/intel/sandybridge: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/sandybridge/sandybridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 7b0efd1..972ed9f 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -234,7 +234,7 @@ void mainboard_config_superio(void); int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp;

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New patch to review for coreboot: southbridge/intel/ibexpeak: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16408 -gerrit commit 659653033b74339fac65b3eb511841bebccc8b36 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:15:33 2016 +0200 southbridge/intel/ibexpeak: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/ibexpeak. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ic569aada9301b37e73196872584e191d553acd86 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/ibexpeak/early_smbus.c | 2 +- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/pch.h | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 3d4c237..f3dab8d 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index eb25328..4e4860c 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -23,7 +23,7 @@ which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6c694fd..d87f8e0 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -61,7 +61,7 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#if !defined(__SMM__) +#if !defined(__SIMPLE_DEVICE__) #include "chip.h" void pch_enable(device_t dev); #endif diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 0ad7e65..c3db159 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -280,7 +280,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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New patch to review for coreboot: southbridge/intel/bd82x6x: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16407 -gerrit commit b73f0e19504ec4dbbab083f9450491c2de72ac3e Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:14:39 2016 +0200 southbridge/intel/bd82x6x: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/bd82x6x. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/pch.c | 10 ++++++---- src/southbridge/intel/bd82x6x/pch.h | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 2b174c7..9f74fdd 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index b2fbd69..a5c63b6 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -38,7 +38,7 @@ static uint16_t read16p (uintptr_t addr) which is done at the end of raminit. */ void early_thermal_init(void) { - device_t dev; + pci_devfn_t dev; msr_t msr; dev = PCI_DEV(0x0, 0x1f, 0x6); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 974abb1..51fdd2e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -30,11 +30,12 @@ int pch_silicon_revision(void) { static int pch_revision_id = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif @@ -46,11 +47,12 @@ int pch_silicon_revision(void) int pch_silicon_type(void) { static int pch_type = -1; - device_t dev; -#ifdef __SMM__ +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; dev = PCI_DEV(0, 0x1f, 0); #else + device_t dev; dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); #endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index f22fed5..1977c8f 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -66,7 +66,7 @@ void intel_pch_finalize_smm(void); #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) -#if !defined(__SMM__) +#if !defined(__SIMPLE_DEVICE__) #include "chip.h" void pch_enable(device_t dev); #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 0478285..71ebb6e 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -278,7 +278,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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New patch to review for coreboot: northbridge/intel/nehalem: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16406 -gerrit commit e92400b9cc893bf60077e7d5a0d8f2da43486146 Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:13:10 2016 +0200 northbridge/intel/nehalem: transition away from device_t Replace the use of the old device_t definition inside northbridge/intel/nehalem. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/nehalem/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 42761fa..3471282 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -130,7 +130,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion) /* Initialize IGD OpRegion, called from ACPI code */ int init_igd_opregion(igd_opregion_t * opregion) { - device_t igd; + pci_devfn_t igd; u16 reg16; memset((void *)opregion, 0, sizeof(igd_opregion_t));

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coreboot-gerrit September 2016