coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: commonlib: update fsp_relocate to make it compatible with UEFI 2.6
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 51a0f7cee47a9e460f56932fba55d4b571e77f9d Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Tue Aug 23 14:55:13 2016 -0700 commonlib: update fsp_relocate to make it compatible with UEFI 2.6 UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32 which cannot be read using read_le32(&returnval). Add in a cast in order to safeguard for any non x86 architecture that may use this relocate. The proper change will be to get the UEFI header files changed to not cast this return value. Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://review.coreboot.org/16309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16309 for details. -gerrit

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Patch merged into coreboot/master: lenovo/x60: transition away from device_t
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 4bf48e8c3377e3d4b4284f7f84f3e338bbce6665 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:15:49 2016 +0200 lenovo/x60: transition away from device_t Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev(a)dettori.io> Reviewed-on: https://review.coreboot.org/16372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16372 for details. -gerrit

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Patch merged into coreboot/master: southbridge/amd/cs553x: Fix whitespace early_setup.c
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 7aded784c1bbf8ed4fc67a33753a2e539c101be5 Author: Martin Roth <martinroth(a)google.com> Date: Wed Aug 31 13:44:08 2016 -0600 southbridge/amd/cs553x: Fix whitespace early_setup.c Commit ba28e8d7 (src/southbridge: Code formating) incorrectly inserted some whitespace in these files. Change-Id: Ifdcc3580aaba224a396c6efec319e22610c6c81d Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16385 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16385 for details. -gerrit

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Patch set updated for coreboot: southbridge/amd/cs553x: Fix whitespace early_setup.c
by Martin Roth 02 Sep '16

02 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16385 -gerrit commit 1cb15dd4d8a9293b8f5c15afa295a2385475aeee Author: Martin Roth <martinroth(a)google.com> Date: Wed Aug 31 13:44:08 2016 -0600 southbridge/amd/cs553x: Fix whitespace early_setup.c Commit ba28e8d7 (src/southbridge: Code formating) incorrectly inserted some whitespace in these files. Change-Id: Ifdcc3580aaba224a396c6efec319e22610c6c81d Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/southbridge/amd/cs5535/early_setup.c | 4 ++-- src/southbridge/amd/cs5536/early_setup.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c index 935153f..1030aa0 100644 --- a/src/southbridge/amd/cs5535/early_setup.c +++ b/src/southbridge/amd/cs5535/early_setup.c @@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void) outl(0x1 << (CS5535_DEV_NUM + 10), 0); } -static void cs5535_usb_swapsif (void) +static void cs5535_usb_swapsif(void) { msr_t msr; @@ -133,7 +133,7 @@ static void cs5535_early_setup(void) printk(BIOS_DEBUG, "Setup idsel\n"); cs5535_setup_idsel(); printk(BIOS_DEBUG, "Setup iobase\n"); - cs5535_usb_swapsif (); + cs5535_usb_swapsif(); cs5535_setup_iobase(); printk(BIOS_DEBUG, "Setup gpio\n"); cs5535_setup_gpio(); diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index cc427b0..013607b 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void) outl(0x1 << (CS5536_DEV_NUM + 10), 0); } -static void cs5536_usb_swapsif (void) +static void cs5536_usb_swapsif(void) { msr_t msr; @@ -260,7 +260,7 @@ static void cs5536_early_setup(void) //printk(BIOS_DEBUG, "Setup idsel\n"); cs5536_setup_idsel(); //printk(BIOS_DEBUG, "Setup iobase\n"); - cs5536_usb_swapsif (); + cs5536_usb_swapsif(); cs5536_setup_iobase(); //printk(BIOS_DEBUG, "Setup gpio\n"); cs5536_setup_gpio();

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Patch merged into coreboot/master: lenovo/x200, t400: use gpio.h instead of gpio_setup
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 734b3d1be0773446c8d66205234a817fa10f48db Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Aug 31 12:57:08 2016 +0200 lenovo/x200,t400: use gpio.h instead of gpio_setup Uses gpio.h instead of default_southbridge_gpio_setup to configure southbridge GPIO's. This is more consistent with how GPIO's are configured on newer targets. Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/16379 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/16379 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Search the cksum command without checking OS type
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 5cf758d45b70fde40df8d2bf4925eb344b7b9b0b Author: zbao <fishbaozi(a)gmail.com> Date: Tue Sep 1 22:28:57 2015 -0400 buildgcc: Search the cksum command without checking OS type The checksum command might appear to be unpredictable only by checking the OS. Just list the candidates, sorted by possibility. Change-Id: Ia3f4f5f0f98ff47d322a4f70689cca0bd4fa79fa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/11483 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/11483 for details. -gerrit

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Patch set updated for coreboot: Update .checkpatch.conf
by Martin Roth 02 Sep '16

02 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16010 -gerrit commit 257a3a7075dc9cee38f43f26a4c03579dec0e9fc Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Aug 1 12:21:30 2016 -0700 Update .checkpatch.conf - Don't require a description of every config statement in the Kconfig changes - Don't complain about externs in .c files - Don't complain about the use of the volatile keyword. The kernel may not want it, but we definitely need it. - Disable checks that seem to be broken. Change-Id: Ic419b81cd36852a91e887e610d4a04984ab5fbd7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Martin Roth <martinroth(a)google.com> --- .checkpatch.conf | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/.checkpatch.conf b/.checkpatch.conf index f7b9b32..f194ced 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -1,9 +1,6 @@ # Not Linux, so don't expect a Linux tree. --no-tree -# Require every Kconfig symbol to have at least two lines in their description. ---min-conf-desc-length=2 - # Ignore aspects we don't follow here. --ignore C99_COMMENTS --ignore GLOBAL_INITIALISERS @@ -15,3 +12,15 @@ --ignore PREFER_PRINTF --ignore SPLIT_STRING --ignore BLOCK_COMMENT_STYLE +--ignore AVOID_EXTERNS +--ignore VOLATILE +--ignore CONFIG_DESCRIPTION + +# FILE_PATH_CHANGES seems to not be working correctly. It will +# choke on added / deleted files even if the MAINTAINERS file +# is touched. +--ignore FILE_PATH_CHANGES + +# This one has a linux path hard coded, so it would choke on +# some commits unnecessarily. +--ignore EXECUTE_PERMISSIONS

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Patch merged into coreboot/master: Fix newlines at the end of files
by gerrit＠coreboot.org 02 Sep '16

02 Sep '16

the following patch was just integrated into master: commit 26d484a237939abdc5fe47d0f8dfa879b0e07dd2 Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 29 15:55:06 2016 -0600 Fix newlines at the end of files All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev(a)dettori.io> See https://review.coreboot.org/16361 for details. -gerrit

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Patch set updated for coreboot: southbridge/intel/i82801gx: transition away from device_t
by Antonello Dettori 02 Sep '16

02 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16370 -gerrit commit 6a17c4ba6fbf06518b1694d0a544bd3b92e31e68 Author: Antonello Dettori <dev(a)dettori.io> Date: Tue Aug 30 22:05:32 2016 +0200 southbridge/intel/i82801gx: transition away from device_t Replace the use of the old device_t definition inside southbridge/intel/i82801gx. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 4 +++- src/southbridge/intel/i82801gx/smihandler.c | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 2f9cdeb..47fe5f6 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d4adc18..7e8b988 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -43,7 +43,9 @@ #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" -extern void i82801gx_enable(device_t dev); +#if !defined(__SIMPLE_DEVICE__) +void i82801gx_enable(device_t dev); +#endif void gpi_route_interrupt(u8 gpi, u8 mode); #else void enable_smbus(void); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index d3867a5..c6425db 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -276,7 +276,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID);

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Patch set updated for coreboot: nb/gm45/gma.c: enable VESA framebuffer mode on VGA output
by Arthur Heymans 02 Sep '16

02 Sep '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16338 -gerrit commit 033614f2be0bb24509b4662666f39d2d94417c3b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Aug 27 01:09:19 2016 +0200 nb/gm45/gma.c: enable VESA framebuffer mode on VGA output This implements "Keep VESA framebuffer" behavior on VGA output of gm45. This patch reuses Linux code to compute vga divisors. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 262 ++++++++++++++++++++++++++++++++------- 1 file changed, 220 insertions(+), 42 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74c9bc3..11c232f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -25,6 +25,7 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <kconfig.h> +#include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" #include "chip.h" @@ -35,6 +36,18 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) + + static struct resource *gtt_res = NULL; u32 gtt_read(u32 reg) @@ -345,14 +358,39 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - u8 *mmio) + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { int i; - u32 hactive, vactive; + u8 edid_data[128]; + struct edid edid; + struct edid_mode *mode; + u32 hactive, vactive, right_border, bottom_border; + int hpolarity, vpolarity; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 target_frequency; + u32 err_most = 0xffffffff; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00040000; + u32 refclk = 96000; + vga_gr_write(0x18, 0); + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -363,8 +401,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON - ); + | ADPA_DPMS_ON); write32(mmio + 0x7041c, 0x0); write32(mmio + DPLL_MD(0), 0x3); @@ -382,95 +419,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); + udelay(1); + + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); + intel_gmbus_stop(mmio + GMBUS0); + decode_edid(edid_data, + sizeof(edid_data), &edid); + mode = &edid.mode; + + /* Disable screen memory to prevent garbage from appearing. */ vga_sr_write(1, vga_sr_read(1) | 0x20); - hactive = 640; - vactive = 400; + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = mode->hborder; + bottom_border = mode->vborder; + hpolarity = (mode->phsync == '-'); + vpolarity = (mode->pvsync == '-'); + vsync = mode->vspw; + hsync = mode->hspw; + vblank = mode->vbl; + hblank = mode->hbl; + hfront_porch = mode->hso; + vfront_porch = mode->vso; + target_frequency = mode->pixel_clock; + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); + } else { + vga_textmode_init(); + } + + u32 candn, candm1, candm2, candp1; + for (candn = 1; candn <= 4; candn++) { + for (candm1 = 23; candm1 >= 17; candm1--) { + for (candm2 = 11; candm2 >= 5; candm2--) { + for (candp1 = 3; candp1 >= 1; candp1--) { + u32 m = 5 * (candm1 + 2) + (candm2 + 2); + u32 p = candp1 * 10; /* 10 == p2 */ + u32 vco = DIV_ROUND_CLOSEST(refclk * m, candn + 2); + u32 dot = DIV_ROUND_CLOSEST(vco, p); + u32 this_err = ABS(dot - target_frequency); + if (this_err < err_most) { + err_most = this_err; + pixel_n = candn; + pixel_m1 = candm1; + pixel_m2 = candm2; + pixel_p1 = candp1; + } + } + } + } + } + + if (err_most == 0xffffffff) { + printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; + data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) + / (link_frequency * 8 * 4); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 96000 * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) + / (pixel_p1 * 10))); mdelay(1); - write32(mmio + FP0(0), 0x31108); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + FP0(0), (pixel_n << 16) + | (pixel_m1 << 8) | pixel_m2); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); + mdelay(1); - write32(mmio + DPLL(0), - DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL - | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 - | 0x10601 - ); + write32(mmio + DPLL(0), DPLL_VCO_ENABLE + | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL + | (0x10000 << (pixel_p1 - 1)) + | (6 << 9)); write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); write32(mmio + HTOTAL(0), - ((hactive - 1) << 16) + ((hactive + right_border + hblank - 1) << 16) | (hactive - 1)); write32(mmio + HBLANK(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); write32(mmio + HSYNC(0), - ((hactive - 1) << 16) - | (hactive - 1)); + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); - write32(mmio + VTOTAL(0), ((vactive - 1) << 16) - | (vactive - 1)); - write32(mmio + VBLANK(0), ((vactive - 1) << 16) + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - ((vactive - 1) << 16) - | (vactive - 1)); + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); write32(mmio + PF_WIN_POS(0), 0); - - write32(mmio + PIPESRC(0), (639 << 16) | 399); - write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); - write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0x80000000); + } mdelay(1); + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + write32(mmio + 0x000f000c, 0x00002040); mdelay(1); write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6); + write32(mmio + 0x000f0008, 0x00000040); + write32(mmio + 0x000f000c, 0x00022050); + write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + VGACNTRL, 0x0); - write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); - mdelay(1); + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); + } else { + write32(mmio + VGACNTRL, 0xc4008e); + } write32(mmio + ADPA, ADPA_DAC_ENABLE | ADPA_PIPE_A_SELECT | ADPA_CRT_HOTPLUG_MONITOR_COLOR | ADPA_CRT_HOTPLUG_ENABLE - | ADPA_USE_VGA_HVPOLARITY | ADPA_VSYNC_CNTL_ENABLE | ADPA_HSYNC_CNTL_ENABLE | ADPA_DPMS_ON - ); + | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : + ADPA_VSYNC_ACTIVE_HIGH) + | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : + ADPA_HSYNC_ACTIVE_HIGH)); - vga_textmode_init(); + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - /* Enable screen memory. */ + /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); /* Clear interrupts. */ write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { + memset((void *) lfb, 0, + edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); + } + + } /* compare the header of the vga edid header */ @@ -480,6 +656,7 @@ static u8 vga_connected(u8 *mmio) u8 vga_edid[128]; u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + intel_gmbus_stop(mmio + GMBUS0); for (int i = 0; i < 8; i++) { if (vga_edid[i] != header[i]) { printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); @@ -566,7 +743,8 @@ static void gma_func0_init(struct device *dev) "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); if (vga_connected(res2mmio(gtt_res, 0, 0))) - gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + gma_init_vga(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); else gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base);

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coreboot-gerrit September 2016