coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit c43a2ab91b52f7fa03fc33538a41cfd468308775 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 69 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 72 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..52779f1 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + OR( OR (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ + +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit 132ed1e755ee42d944b4eb9d9eff49df6cf74fc5 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 70 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 73 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..6fc1f4f --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + OR( OR (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + } + + /* SCC power gate control method, this method must be serialized as multiple + * device will control the GENR register + */ + + /* + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ + +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

1 0

Patch set updated for coreboot: gm45/gma.c: clean up some registers
by Arthur Heymans 22 Aug '16

22 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16217 -gerrit commit eaf5d8f83e23e84b15483be4241a498859561c66 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 15 00:04:34 2016 +0200 gm45/gma.c: clean up some registers According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 110 +++++++-------------------------------- 1 file changed, 18 insertions(+), 92 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index a89f9bb..b02c89b 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void power_port(u8 *mmio) -{ - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - write32(mmio + 0x00061100, 0x00010000); - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00010000 - read32(mmio + 0x00061100); // = 0x00000000 - write32(mmio + 0x00061100, 0x00000000); - read32(mmio + 0x00061100); // = 0x00000000 - read32(mmio + 0x00064200); // = 0x0000001c - write32(mmio + 0x00064210, 0x8004003e); - write32(mmio + 0x00064214, 0x80060002); - write32(mmio + 0x00064218, 0x01000000); - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - read32(mmio + 0x00064210); // = 0x0144003e - write32(mmio + 0x00064210, 0x8074003e); - read32(mmio + 0x00064210); // = 0x5144003e - read32(mmio + 0x00064210); // = 0x5144003e - write32(mmio + 0x00064210, 0x5344003e); - write32(mmio + 0x00064f00, 0x0100030c); - write32(mmio + 0x00064f04, 0x00b8230c); - write32(mmio + 0x00064f08, 0x06f8930c); - write32(mmio + 0x00064f0c, 0x09f8e38e); - write32(mmio + 0x00064f10, 0x00b8030c); - write32(mmio + 0x00064f14, 0x0b78830c); - write32(mmio + 0x00064f18, 0x0ff8d3cf); - write32(mmio + 0x00064f1c, 0x01e8030c); - write32(mmio + 0x00064f20, 0x0ff863cf); - write32(mmio + 0x00064f24, 0x0ff803cf); - write32(mmio + 0x000c4030, 0x00001000); - read32(mmio + 0x00044000); // = 0x00000000 - write32(mmio + 0x00044030, 0x00001000); - read32(mmio + 0x00061150); // = 0x0000001c - write32(mmio + 0x00061150, 0x0000089c); - write32(mmio + 0x000fcc00, 0x01986f00); - write32(mmio + 0x000fcc0c, 0x01986f00); - write32(mmio + 0x000fcc18, 0x01986f00); - write32(mmio + 0x000fcc24, 0x01986f00); - read32(mmio + 0x00044000); // = 0x00000000 - read32(mmio + LVDS); // = 0x40000002 -} - static void intel_gma_init(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, for (i = 0; i <= 0x18; i++) vga_cr_write(i, cr[i]); - power_port(mmio); - intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); decode_edid(edid_data, sizeof(edid_data), &edid); @@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_ENABLE_DITHER + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(0)); mdelay(1); write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); write32(mmio + FP0(0), ((pixel_n - 2) << 16) - | ((pixel_m1 - 2) << 8) | pixel_m2); + | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << 9)); mdelay(1); write32(mmio + DPLL(0), DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | DPLL_VGA_MODE_DIS | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 : DPLLB_LVDS_P2_CLOCK_DIV_14) | (0x10000 << (pixel_p1 - 1)) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) - | (0x1 << (pixel_p1 - 1))); + | (6 << 9)); /* Re-lock the registers. */ write32(mmio + PP_CONTROL, (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); @@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + HTOTAL(0), ((hactive + right_border + hblank - 1) << 16) @@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) | (vactive + bottom_border - 1)); write32(mmio + VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) + ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) | (vactive + bottom_border + vfront_porch - 1)); write32(mmio + PIPECONF(0), PIPECONF_DISABLE); @@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, | (vactive - 1)); write32(mmio + PF_CTL(0), 0); write32(mmio + PF_WIN_SZ(0), 0); - write32(mmio + PFIT_CONTROL, 0x20000000); + write32(mmio + PFIT_CONTROL, 0); } else { write32(mmio + PIPESRC(0), (639 << 16) | 399); write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); @@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { - write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE); + write32(mmio + VGACNTRL, VGA_DISP_DISABLE); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); mdelay(1); @@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + VGACNTRL, 0xc4008e); } - write32(mmio + TRANS_HTOTAL(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + TRANS_HBLANK(0), - ((hactive + right_border + hblank - 1) << 16) - | (hactive + right_border - 1)); - write32(mmio + TRANS_HSYNC(0), - ((hactive + right_border + hfront_porch + hsync - 1) << 16) - | (hactive + right_border + hfront_porch - 1)); - - write32(mmio + TRANS_VTOTAL(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); - write32(mmio + TRANS_VBLANK(0), - ((vactive + bottom_border + vblank - 1) << 16) - | (vactive + bottom_border - 1)); - write32(mmio + TRANS_VSYNC(0), - (vactive + bottom_border + vfront_porch + vsync - 1) - | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + 0x00060100, 0xb01c4000); - write32(mmio + 0x000f000c, 0xb01a2050); - mdelay(1); - write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC - ); - write32(mmio + LVDS, - LVDS_PORT_ENABLE + write32(mmio + LVDS, LVDS_PORT_ENABLE | (hpolarity << 20) | (vpolarity << 21) | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) - | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_ENABLE_DITHER + | LVDS_PIPE(0)); write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);

1 0

Patch set updated for coreboot: gm45/gma.c: use screen on vga connector if connected
by Arthur Heymans 22 Aug '16

22 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16295 -gerrit commit f755e3f42310cf12b90080f432010da71b5f3fac Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 22 17:58:46 2016 +0200 gm45/gma.c: use screen on vga connector if connected The intel x4x native graphic init works on gm45 to use the vga screen instead of the integrated lvds screen. This patch integrates it in gm45 in a way that the behavior is similar to vbios: If no vga display is connected the internal lvds screen is used. If an external screen is detected on the vga port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 155 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b02c89b..ad887b9 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void intel_gma_init(const struct northbridge_intel_gm45_config *info, +static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + u8 *mmio) +{ + + int i; + u32 hactive, vactive; + + vga_gr_write(0x18, 0); + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + vga_textmode_init(); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +/* compare the header of the vga edid header + if vga is not connected it should not have a correct header */ +static u8 vga_connected(u8 *mmio) +{ + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); + return 0; + } + } + printk(BIOS_SPEW, "VGA display connected\n"); + return 1; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) + gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */

1 0

Patch set updated for coreboot: gm45/gma.c: use screen on vga connector if connected
by Arthur Heymans 22 Aug '16

22 Aug '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16295 -gerrit commit 83e43cd4b834f5b08dbd442a1c3855ec3e2790b8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Aug 22 17:58:46 2016 +0200 gm45/gma.c: use screen on vga connector if connected The intel x4x native graphic init works on gm45 to use the vga screen instead of the integrated lvds screen. This patch integrates it in gm45 in a way that the behavior is similar to vbios: If no vga display is connected the internal lvds screen is used. If an external screen is detected on the vga port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/gm45/gma.c | 155 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 152 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index b02c89b..ad887b9 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) write32(res2mmio(gtt_res, reg, 0), data); } -static void intel_gma_init(const struct northbridge_intel_gm45_config *info, +static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u8 *mmio, u32 physbase, u16 piobase, u32 lfb) { @@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, } } +static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + u8 *mmio) +{ + + int i; + u32 hactive, vactive; + + vga_gr_write(0x18, 0); + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + vga_textmode_init(); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +/* compare the header of the vga edid header + if vga is not connected it should not have a correct header */ +static u8 vga_connected(u8 *mmio) +{ + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_SPEW, "VGA not connected. Using LVDS display\n"); + return 0; + } + } + printk(BIOS_SPEW, "VGA display connected\n"); + return 1; +} + static void gma_pm_init_post_vbios(struct device *const dev) { const struct northbridge_intel_gm45_config *const conf = dev->chip_info; @@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) + gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit fbe6d1a66660df933fc3bef49dd291d6aeb6a0d7 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 83 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 2 files changed, 86 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..764917a --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + OR( OR (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + Offset (0x08), + , 5, + GRR3, 1, + } + + /* SCC power gate control method, this method must be serialized as multiple + * device will control the GENR register + */ + + /* + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + Name (TMP, 0x0) + if (LEqual(Arg0, 0x1)) { + Store (^GENR, TMP) + Or (TMP, Arg1, ^GENR) + + } ElseIf (LEqual(Arg0, 0x0)){ + Store (^GENR, TMP) + And (TMP, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + /* Method for port80 debug */ + OperationRegion (POST, SystemIO, 0x80, 1) + Field (POST, ByteAcc, Lock, Preserve) + { + DBG0, 8 + } + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ + +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

1 0

Patch set updated for coreboot: arch/riscv: Delegate exceptions to supervisor mode if appropriate
by Jonathan Neuschäfer 22 Aug '16

22 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16160 -gerrit commit 0e167897fe9bef55b83a9ba5d9d3f96a585c2087 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Mon Aug 22 19:37:15 2016 +0200 arch/riscv: Delegate exceptions to supervisor mode if appropriate Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index bea552d..98b7edc 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -208,4 +208,14 @@ void mstatus_init(void) clear_csr(mip, MIP_MSIP); set_csr(mie, MIP_MSIP); + + /* Configure which exception causes are delegated to supervisor mode */ + set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) + | (1 << CAUSE_FAULT_FETCH) + | (1 << CAUSE_ILLEGAL_INSTRUCTION) + | (1 << CAUSE_BREAKPOINT) + | (1 << CAUSE_FAULT_LOAD) + | (1 << CAUSE_FAULT_STORE) + | (1 << CAUSE_USER_ECALL) + ); }

1 0

Patch set updated for coreboot: arch/riscv: Print the page table structure after construction
by Jonathan Neuschäfer 22 Aug '16

22 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16015 -gerrit commit 877ded79fe0e3cc1e76d0396f77ae2c67af66bd3 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Mon Aug 22 19:37:15 2016 +0200 arch/riscv: Print the page table structure after construction A new Kconfig option, DEBUG_PRINT_PAGE_TABLES, is added to control this behaviour. It is currently only available on RISC-V, but other architectures can use it, too, should the need arise. Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/Kconfig | 8 ++++ src/arch/riscv/include/vm.h | 2 +- src/arch/riscv/virtual_memory.c | 85 +++++++++++++++++++++++++++++++++++++---- 3 files changed, 86 insertions(+), 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 7db491f..64da061 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1127,6 +1127,14 @@ config DEBUG_BOOT_STATE Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. +config DEBUG_PRINT_PAGE_TABLES + bool "Print the page tables after construction" + default n + depends on ARCH_RISCV + help + After the page tables have been built, print them on the debug + console. + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index 5bf03c7..cc26b13 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -63,7 +63,7 @@ size_t pte_ppn(pte_t pte); pte_t ptd_create(uintptr_t ppn); pte_t pte_create(uintptr_t ppn, int prot, int user); -void walk_page_table(void); +void print_page_table(void); void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index bbbba7a..bea552d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -23,11 +23,77 @@ pte_t* root_page_table; -void walk_page_table(void) { - // TODO: implement a full walk to make sure memory was set up - //const size_t pte_per_page = RISCV_PGSIZE/sizeof(void*); - pte_t* t = root_page_table; - printk(BIOS_DEBUG, "root_page_table: %p\n", t); +/* Indent the following text by 2*level spaces */ +static void indent(int level) +{ + int i; + for (i = 0; i < level; i++) + printk(BIOS_DEBUG, " "); +} + +/* + * Convert a page table index at a given page table level to a virtual address + * offset + */ +static uintptr_t index_to_virt_addr(int index, int level) +{ + /* + * Index is at most RISCV_PGLEVEL_BITS bits wide (not considering the + * leading zeroes. If level==0, the below expression thus shifts index + * into the highest bits of a 64-bit number, and then shifts it down + * with sign extension. + * + * If level>0, then the expression should work as expected, without any + * magic. + */ + return ((intptr_t)index) + << (64 - RISCV_PGLEVEL_BITS - level * RISCV_PGLEVEL_BITS) + >> (64 - VA_BITS); +} + +/* Dump the page table structures to the console -- helper function */ +static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) +{ + int i; + + indent(level); + printk(BIOS_DEBUG, "Level %d page table at 0x%p\n", level, pt); + + for (i = 0; i < RISCV_PGSIZE / sizeof(pte_t); i++) { + char urwx[8]; + uintptr_t pointer; + intptr_t next_virt_addr; + + if (!(pt[i] & PTE_V)) + continue; + + urwx[0] = (pt[i] & PTE_U)? 'u' : '-'; + urwx[1] = (pt[i] & PTE_R)? 'r' : '-'; + urwx[2] = (pt[i] & PTE_W)? 'w' : '-'; + urwx[3] = (pt[i] & PTE_X)? 'x' : '-'; + urwx[4] = '\0'; + + next_virt_addr = virt_addr + index_to_virt_addr(i, level); + + pointer = ((uintptr_t)pt[i] >> 10) << RISCV_PGSHIFT; + + indent(level + 1); + printk(BIOS_DEBUG, "Valid PTE at index %d (0x%016zx -> 0x%zx), ", + i, (size_t) next_virt_addr, (size_t) pointer); + if (PTE_TABLE(pt[i])) + printk(BIOS_DEBUG, "page table\n"); + else + printk(BIOS_DEBUG, "protections %s\n", urwx); + + if (PTE_TABLE(pt[i])) { + print_page_table_at((pte_t *)pointer, next_virt_addr, level + 1); + } + } +} + +/* Print the page table structures to the console */ +void print_page_table(void) { + print_page_table_at(root_page_table, 0, 0); } void flush_tlb(void) @@ -124,14 +190,17 @@ void initVirtualMemory(void) { uintptr_t pageTableStart = 0x1400000; init_vm(virtualStart, physicalStart, pageTableStart); mb(); + +#if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); - walk_page_table(); + print_page_table(); +#else + printk(BIOS_DEBUG, "Finished initializing virtual memory\n"); +#endif } void mstatus_init(void) { - // supervisor support is required - uintptr_t ms = 0; ms = INSERT_FIELD(ms, MSTATUS_FS, 3); ms = INSERT_FIELD(ms, MSTATUS_XS, 3);

1 0

Patch set updated for coreboot: arch/riscv: Implement the SBI again
by Jonathan Neuschäfer 22 Aug '16

22 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16119 -gerrit commit 359d9e52e77e2f214ec6952c13c596070d842cbb Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Mon Aug 22 19:37:16 2016 +0200 arch/riscv: Implement the SBI again Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OF… Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/include/arch/sbi.h | 36 +++++++ src/arch/riscv/sbi.S | 117 +++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 43 ++++----- src/arch/riscv/virtual_memory.c | 3 +- src/mainboard/emulation/spike-riscv/spike_util.c | 22 ++--- 6 files changed, 183 insertions(+), 39 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 718aad9..4bab459 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -95,6 +95,7 @@ ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-y += sbi.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/include/arch/sbi.h b/src/arch/riscv/include/arch/sbi.h new file mode 100644 index 0000000..df7f6cc --- /dev/null +++ b/src/arch/riscv/include/arch/sbi.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _ARCH_SBI_H +#define _ARCH_SBI_H + +#define SBI_ECALL_HART_ID 0 +#define SBI_ECALL_CONSOLE_PUT 1 +#define SBI_ECALL_SEND_DEVICE_REQUEST 2 +#define SBI_ECALL_RECEIVE_DEVICE_RESPONSE 3 +#define SBI_ECALL_SEND_IPI 4 +#define SBI_ECALL_CLEAR_IPI 5 +#define SBI_ECALL_SHUTDOWN 6 +#define SBI_ECALL_SET_TIMER 7 +#define SBI_ECALL_QUERY_MEMORY 8 +#define SBI_ECALL_NUM_HARTS 9 + +#ifndef __ASSEMBLY__ +struct opaque; +extern struct opaque sbi_page; +#endif + +#endif diff --git a/src/arch/riscv/sbi.S b/src/arch/riscv/sbi.S new file mode 100644 index 0000000..f4d5411 --- /dev/null +++ b/src/arch/riscv/sbi.S @@ -0,0 +1,117 @@ +/* + * RISC-V supervisor binary interface (SBI) trampoline page + * + * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#define __ASSEMBLY__ +#include <arch/encoding.h> +#include <arch/sbi.h> + +.section ".text.sbi", "ax", %progbits + +/* align to a page boundary */ +.align RISCV_PGSHIFT + +.globl sbi_page +sbi_page: + + /* + * None of the SBI entry points is located in the first half of the + * page + */ + .skip 0x800 + + /* -2048: size_t sbi_hart_id(void); */ + li a7, SBI_ECALL_HART_ID + ecall + jr ra + .align 4 + + /* -2032: size_t sbi_num_harts(void); */ + li a7, SBI_ECALL_NUM_HARTS + ecall + jr ra + .align 4 + + /* -2016: unsigned long sbi_query_memory(unsigned long id, + memory_block_info *p); */ + li a7, SBI_ECALL_QUERY_MEMORY + ecall + jr ra + .align 4 + + /* -2000: int sbi_console_putchar(uint8_t ch); */ + li a7, SBI_ECALL_CONSOLE_PUT + ecall + jr ra + .align 4 + + /* -1984: int sbi_console_getchar(void); */ + li a0, -1 /* failure: Coreboot doesn't support console input */ + jr ra + .align 4 + + /* -1968: Not allocated */ + ebreak + .align 4 + + /* -1952: int sbi_send_ipi(size_t hart_id); */ + ebreak + .align 4 + + /* -1936: int bool sbi_clear_ipi(void); */ + ebreak + .align 4 + + /* -1920: unsigned long sbi_timebase(void); */ + li a0, 1000000000 /* I have no idea. */ + jr ra + .align 4 + + /* -1904: void sbi_shutdown(void); */ + li a7, SBI_ECALL_SHUTDOWN + ecall + jr ra + .align 4 + + /* -1888: void sbi_set_timer(unsigned long long stime_value); */ + li a7, SBI_ECALL_SET_TIMER + ecall + jr ra + .align 4 + + /* -1872: int sbi_mask_interrupt(int which); */ + ebreak + .align 4 + + /* -1856: int sbi_unmask_interrupt(int which); */ + ebreak + .align 4 + + /* -1840: void sbi_remote_sfence_vm(const uintptr_t* harts, + size_t asid); */ + ebreak + .align 4 + + /* -1824: void sbi_remote_sfence_vm_range(const uintptr_t* harts, + size_t asid, uintptr_t start, uintptr_t size); */ + ebreak + .align 4 + + /* -1808: void sbi_remote_fence_i(const uintptr_t* harts); */ + ebreak + .align 4 + +/* Fill the remainder of the page */ +.align RISCV_PGSHIFT diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index d8ac784..29d5a0b 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -15,63 +15,56 @@ */ #include <arch/exception.h> +#include <arch/sbi.h> #include <console/console.h> #include <spike_util.h> #include <string.h> #include <vm.h> -#define HART_ID 0 -#define CONSOLE_PUT 1 -#define SEND_DEVICE_REQUEST 2 -#define RECEIVE_DEVICE_RESPONSE 3 -#define SEND_IPI 4 -#define CLEAR_IPI 5 -#define SHUTDOWN 6 -#define SET_TIMER 7 -#define QUERY_MEMORY 8 - -int loopBreak2 = 1; - void handle_supervisor_call(trapframe *tf) { - uintptr_t call = tf->gpr[17]; - uintptr_t arg0 = tf->gpr[10]; - uintptr_t arg1 = tf->gpr[11]; + uintptr_t call = tf->gpr[17]; /* a7 */ + uintptr_t arg0 = tf->gpr[10]; /* a0 */ + uintptr_t arg1 = tf->gpr[11]; /* a1 */ uintptr_t returnValue; switch(call) { - case HART_ID: + case SBI_ECALL_HART_ID: printk(BIOS_DEBUG, "Getting hart id...\n"); - returnValue = mcall_hart_id(); + returnValue = read_csr(mhartid); break; - case CONSOLE_PUT: + case SBI_ECALL_NUM_HARTS: + /* TODO: parse the hardware-supplied config string and + return the correct value */ + returnValue = 1; + case SBI_ECALL_CONSOLE_PUT: returnValue = mcall_console_putchar(arg0); break; - case SEND_DEVICE_REQUEST: + case SBI_ECALL_SEND_DEVICE_REQUEST: printk(BIOS_DEBUG, "Sending device request...\n"); returnValue = mcall_dev_req((sbi_device_message*) arg0); break; - case RECEIVE_DEVICE_RESPONSE: + case SBI_ECALL_RECEIVE_DEVICE_RESPONSE: printk(BIOS_DEBUG, "Getting device response...\n"); returnValue = mcall_dev_resp(); break; - case SEND_IPI: + case SBI_ECALL_SEND_IPI: printk(BIOS_DEBUG, "Sending IPI...\n"); returnValue = mcall_send_ipi(arg0); break; - case CLEAR_IPI: + case SBI_ECALL_CLEAR_IPI: printk(BIOS_DEBUG, "Clearing IPI...\n"); returnValue = mcall_clear_ipi(); break; - case SHUTDOWN: + case SBI_ECALL_SHUTDOWN: printk(BIOS_DEBUG, "Shutting down...\n"); returnValue = mcall_shutdown(); break; - case SET_TIMER: + case SBI_ECALL_SET_TIMER: printk(BIOS_DEBUG, "Setting timer to %p (current time is %p)...\n", (void *)arg0, (void *)rdtime()); returnValue = mcall_set_timer(arg0); break; - case QUERY_MEMORY: + case SBI_ECALL_QUERY_MEMORY: printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0); returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1); break; diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index fab7d90..74b3825 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -16,6 +16,7 @@ #include <arch/barrier.h> #include <arch/encoding.h> +#include <arch/sbi.h> #include <atomic.h> #include <console/console.h> #include <stdint.h> @@ -151,7 +152,7 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable // map SBI at top of vaddr space uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface - uintptr_t sbiStartAddress = 0x2000; // the start of the sbi mapping + uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index f0f5301..7ddf16b 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -25,12 +25,13 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <spike_util.h> #include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> -#include <string.h> #include <console/console.h> +#include <spike_util.h> +#include <string.h> +#include <vm.h> uintptr_t translate_address(uintptr_t vAddr) { // TODO: implement the page table translation algorithm @@ -41,13 +42,13 @@ uintptr_t translate_address(uintptr_t vAddr) { return translationResult; } -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) { - uintptr_t physicalAddr = translate_address((uintptr_t) p); - memory_block_info *info = (memory_block_info*) physicalAddr; if (id == 0) { - info->base = 0x1000000; // hard coded for now, but we can put these values somewhere later - info->size = 0x7F000000 - info->base; + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); return 0; } @@ -79,7 +80,7 @@ uintptr_t mcall_shutdown(void) uintptr_t mcall_set_timer(unsigned long long when) { - die("mcall_set_timer is currently not implemented"); + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); return 0; } @@ -95,11 +96,6 @@ uintptr_t mcall_dev_resp(void) return 0; } -uintptr_t mcall_hart_id(void) -{ - return HLS()->hart_id; -} - void hls_init(uint32_t hart_id) { memset(HLS(), 0, sizeof(*HLS()));

1 0

Patch set updated for coreboot: arch/riscv: Map the kernel space into RAM (2GiB+)
by Jonathan Neuschäfer 22 Aug '16

22 Aug '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16263 -gerrit commit 1a8868533256efd97610bf4a6889f7febd2ab23d Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Mon Aug 22 19:37:16 2016 +0200 arch/riscv: Map the kernel space into RAM (2GiB+) Change-Id: I273e9d20e02f0333f28e0fc2adcc7940578ea93e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 74b3825..be8b488 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -186,9 +186,9 @@ void initVirtualMemory(void) { } printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x1000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff81000000; - uintptr_t pageTableStart = 0x1400000; + uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs + uintptr_t virtualStart = 0xffffffff80000000; + uintptr_t pageTableStart = 0x91400000; init_vm(virtualStart, physicalStart, pageTableStart); mb();

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2016