coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch merged into coreboot/master: src/mainboard: Remove unnecessary whitespace before "\n"
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit e53e488cf118ce4842fc31fbf38529f22053333c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 12:19:25 2016 +0200 src/mainboard: Remove unnecessary whitespace before "\n" Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16283 for details. -gerrit

1 0

Patch merged into coreboot/master: arch/arm & arm64: Remove unnecessary whitespace before "\n"
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 0638b60590731a9cf3b1200ec6a1bc185085eb6c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 12:14:11 2016 +0200 arch/arm & arm64: Remove unnecessary whitespace before "\n" Change-Id: Ibec78b25c0f330fc8517654761803e8abf203060 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16282 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16282 for details. -gerrit

1 0

Patch merged into coreboot/master: src/southbridge: Remove unnecessary whitespace before "\n" and "\t"
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 7f9df96825100059e3ee1bc78f8b7154441b2751 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 12:06:54 2016 +0200 src/southbridge: Remove unnecessary whitespace before "\n" and "\t" Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16281 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Omar Pakker See https://review.coreboot.org/16281 for details. -gerrit

1 0

Patch set updated for coreboot: src/arch: Capitalize CPU and ACPI
by Martin Roth 23 Aug '16

23 Aug '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16277 -gerrit commit c6db299de8afc4ae4c523581f386de6ab91a4fd0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 10:41:44 2016 +0200 src/arch: Capitalize CPU and ACPI Change-Id: I37dfa853c3dbe93a52f6c37941b17717e22f6430 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/arch/arm64/stage_entry.S | 4 ++-- src/arch/x86/acpigen.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 7f113fb..7aeabe6 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -74,7 +74,7 @@ ENDPROC(cpu_get_exception_stack) * any rmodules. */ ENTRY(arm64_c_environment) - /* Set the exception stack for the cpu. */ + /* Set the exception stack for the CPU. */ bl cpu_get_exception_stack msr SPSel, #1 isb @@ -84,7 +84,7 @@ ENTRY(arm64_c_environment) msr SPSel, #0 isb - /* Set the non-exception stack for the cpu. */ + /* Set the non-exception stack for the CPU. */ bl cpu_get_stack mov sp, x0 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index f35fe02..c978fe6 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -657,7 +657,7 @@ void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype) void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) { /* - * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor + * ACPI 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor * Byte 0: * Bit7 : 1 => big item * Bit6-0: 0000110 (0x6) => 32-bit fixed memory @@ -688,7 +688,7 @@ void acpigen_write_register(acpi_addr_t *addr) void acpigen_write_irq(u16 mask) { /* - * acpi 3.0b section 6.4.2.1: IRQ Descriptor + * ACPI 3.0b section 6.4.2.1: IRQ Descriptor * Byte 0: * Bit7 : 0 => small item * Bit6-3: 0100 (0x4) => IRQ port descriptor @@ -702,7 +702,7 @@ void acpigen_write_irq(u16 mask) void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) { /* - * acpi 4.0 section 6.4.2.6: I/O Port Descriptor + * ACPI 4.0 section 6.4.2.6: I/O Port Descriptor * Byte 0: * Bit7 : 0 => small item * Bit6-3: 1000 (0x8) => I/O port descriptor

1 0

Patch merged into coreboot/master: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit d6e96864c9245b82222dada6fea2b89ccb7fecfd Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 10:12:15 2016 +0200 src/cpu: Capitalize CPU, APIC and IOAPIC typo fix Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16276 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker See https://review.coreboot.org/16276 for details. -gerrit

1 0

Patch merged into coreboot/master: src/northbridge: Remove unnecessary whitespace before "\n" and "\t"
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 38424987c6d19015e4572d5371a0f9f621fc46fa Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 12:01:04 2016 +0200 src/northbridge: Remove unnecessary whitespace before "\n" and "\t" Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker See https://review.coreboot.org/16280 for details. -gerrit

1 0

Patch merged into coreboot/master: src/include: Capitalize APIC and SMM
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit ccf78f083cd2811c401db08b002b2b3c5273db26 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 10:49:19 2016 +0200 src/include: Capitalize APIC and SMM Change-Id: I9b3a2cce6c6bb85791d5cde076d5de95ef0e8790 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16278 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker See https://review.coreboot.org/16278 for details. -gerrit

1 0

Patch merged into coreboot/master: emulation/qemu-i440fx: add cmos.default file
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 7378d925a3bb374f549b51e8d21ec2de059e1cd5 Author: Antonello Dettori <dev(a)dettori.io> Date: Wed Aug 17 22:38:17 2016 +0200 emulation/qemu-i440fx: add cmos.default file Add cmos.default file in order to ease future testing and debugging of cmos related code. Change-Id: I7c6a0aa4e38bb08a520e4838fa216c81b50f2917 Signed-off-by: Antonello Dettori <dev(a)dettori.io> Reviewed-on: https://review.coreboot.org/16247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16247 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmic
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 6f2337459061f400e6ee31503baa8f5d44c49815 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Aug 18 14:08:37 2016 -0700 soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmic Update the config variable that gets set to use DMIC 2 channel blob for intel/apollolake platforms. This flag is set in mainboard. Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Reviewed-on: https://review.coreboot.org/16251 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16251 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmic
by Saurabh Satija 23 Aug '16

23 Aug '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16251 -gerrit commit 3a00420528fdc13d8a71f58c2620c606c991f3c9 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Aug 18 14:08:37 2016 -0700 soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmic Update the config variable that gets set to use DMIC 2 channel blob for intel/apollolake platforms. This flag is set in mainboard. Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 6eb9d9a..cae90b5 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -125,7 +125,7 @@ DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin -cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) +cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-type := raw

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2016