coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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1551 discussions

Patch merged into coreboot/master: nvramcui: refactor code
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit 904dd303cbe99541025cbea008855f807a5d9f5c Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Aug 18 10:32:27 2016 +0200 nvramcui: refactor code Split the main() into a couple of smaller functions in order to more easily extend the payload. Change-Id: I4c2b144e2a28c6f15e360d55c49974675e6a80d2 Signed-off-by: Antonello Dettori <dev(a)dettori.io> Reviewed-on: https://review.coreboot.org/16248 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16248 for details. -gerrit

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Patch set updated for coreboot: google/reef: Tune eMMC DLL settings for reef evt
by Chiranjeevi Rapolu 23 Aug '16

23 Aug '16

Chiranjeevi Rapolu (chiranjeevi.rapolu(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16296 -gerrit commit 26d94268d567adbe259fa66935f60b5c2a652bab Author: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Date: Mon Aug 22 10:55:10 2016 -0700 google/reef: Tune eMMC DLL settings for reef evt Apply eMMC tuned DLL settings for reef evt. Modify comments to avoid replicating info. Add EDS reference. BUG=chrome-os-partner:55648 BRANCH=none TEST=Verify that reef evt boots to OS from eMMC. Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 46 ++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index ea3b20f..a877e86 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -6,30 +6,34 @@ chip soc/intel/apollolake register "pcie_rp4_clkreq_pin" = "0" # wifi/bt - # EMMC TX DATA Delay 1# - # 0x0C[14:8] stands for 12*125 = 1500 pSec delay for HS400 - # 0x11[6:0] stands for 17*125 = 2125 pSec delay for SDR104/HS200 - register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" - # EMMC TX DATA Delay 2# - # 0x00[30:24] stands for 0*125 = no delay for SDR50 - # 0x2B[22:16] stands for 43*125 = 5375 pSec delay for DDR50 - # 0x29[14:8] stands for 41*125 = 5125 pSec delay for SDR25/HS50 - # 0x29[6:0] stands for 41*125 = 5125 pSec delay for SDR12 - register "emmc_tx_data_cntl2" = "0x002B2929" + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" - # EMMC RX CMD/DATA Delay 1# - # 0x00[30:24] stands for 0*125 = no delay for SDR50 - # 0x12[22:16] stands for 18*125 = 2250 pSec delay for DDR50 - # 0x57[14:8] stands for 87*125 = 10875 pSec delay for SDR25/HS50 - # 0x3B[6:0] stands for 59*125= 7375 pSec delay for SDR12 - register "emmc_rx_cmd_data_cntl1" = "0x0012573B" + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" - # EMMC RX CMD/DATA Delay 2# - # 0x01[17:16] stands for Rx Clock before Output Buffer - # 0x00[14:8] stands for 0 delay for Auto Tuning Mode - # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 - register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" # Enable DPTF register "dptf_enable" = "1"

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Patch merged into coreboot/master: drivers/spi: be sure to call spi_init() before spi_flash_probe()
by gerrit＠coreboot.org 23 Aug '16

23 Aug '16

the following patch was just integrated into master: commit df76f8983f001a83f00ad962e047dcb331a6d69f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Aug 22 17:41:13 2016 -0500 drivers/spi: be sure to call spi_init() before spi_flash_probe() It's necessary to call spi_init() prior to calling spi_flash_probe() such that the SPI drivers can do any work required prior to performing SPI transactions. It could be argued that the drivers should handle such situations, however the SPI API implementations seem to assume the callers ensured spi_init() was called before any SPI transactions. This fixes systems that failed to boot introduced by [1]. Issue tracked in https://ticket.coreboot.org/issues/67. [1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8 https://review.coreboot.org/16200 BUG=chrome-os-partner:56151 Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/16297 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> See https://review.coreboot.org/16297 for details. -gerrit

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Patch set updated for coreboot: drivers/spi: be sure to call spi_init() before spi_flash_probe()
by Aaron Durbin 23 Aug '16

23 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16297 -gerrit commit f37de1eb4cd3f821e5b355f02f3b17887ec4d00f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Aug 22 17:41:13 2016 -0500 drivers/spi: be sure to call spi_init() before spi_flash_probe() It's necessary to call spi_init() prior to calling spi_flash_probe() such that the SPI drivers can do any work required prior to performing SPI transactions. It could be argued that the drivers should handle such situations, however the SPI API implementations seem to assume the callers ensured spi_init() was called before any SPI transactions. This fixes systems that failed to boot introduced by [1]. Issue tracked in https://ticket.coreboot.org/issues/67. [1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8 https://review.coreboot.org/16200 BUG=chrome-os-partner:56151 Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/spi/boot_device_rw_nommap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 2a9f19f..bf15e99 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -78,6 +78,9 @@ void boot_device_init(void) if (car_get_var(sfg) != NULL) return; + /* Ensure any necessary setup is performed by the drivers. */ + spi_init(); + car_set_var(sfg, spi_flash_probe(bus, cs)); }

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New patch to review for coreboot: intel/common: Clear wake status bits before sleep
by Shaunak Saha 22 Aug '16

22 Aug '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16299 -gerrit commit 79a7e60b730397b4b7ae0fc88fe08df075cbf58a Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Aug 22 22:05:35 2016 -0700 intel/common: Clear wake status bits before sleep Call power management utility function clear_wake_sts from southbridge_smi_sleep before going to sleep. This is needed to clear the wake status bits in ACPI registers GPE0. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from inbuild keyboard. Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/common/smihandler.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/smihandler.c b/src/soc/intel/common/smihandler.c index e27752b..ceb73e0 100644 --- a/src/soc/intel/common/smihandler.c +++ b/src/soc/intel/common/smihandler.c @@ -176,7 +176,8 @@ void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops) printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } - /* Clear pending wake status bit to avoid immediate wake */ + /* Clear set wake status bit in ACPI registers */ + clear_wake_sts(); /* Tri-state specific GPIOS to avoid leakage during S3/S5 */

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New patch to review for coreboot: intel/apollolake: Power management utility function
by Shaunak Saha 22 Aug '16

22 Aug '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16298 -gerrit commit 1be4447bb05a0dc0c250f2f6ec88f42f186b5f3e Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Aug 22 21:55:23 2016 -0700 intel/apollolake: Power management utility function This patch adds a power management utility function to clear wake status bits in ACPI GPE0 registers. We need to call this function before going to sleep from common smi handler function. BUG=chrome-os-partner:55583 BRANCH=None TEST=Verified that system goes to sleep on lidclose and powerd_dbus_suspend command issued from inbuild keyboard. Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 5641e54..f3b8f00 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -173,6 +173,7 @@ uint16_t clear_pm1_status(void); uint32_t clear_tco_status(void); uint32_t clear_gpe_status(void); void clear_pmc_status(void); +void clear_wake_sts(void); uint32_t get_smi_en(void); void enable_smi(uint32_t mask); void disable_smi(uint32_t mask); diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index aaa4018..61d6ff2 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -246,6 +246,17 @@ void disable_all_gpe(void) disable_gpe(~0); } +/* Clear the wake status bits in ACPI registers */ +void clear_wake_sts(void) +{ + int i; + + for (i = 1; i < GPE0_REG_MAX; i++) { + uint32_t gpe_sts = inl(ACPI_PMIO_BASE + GPE0_STS(i)); + outl(gpe_sts, ACPI_PMIO_BASE + GPE0_STS(i)); + } +} + static uint32_t reset_gpe_status(void) {

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Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit a272298895ea5606ecb32f230ec25a690ab401eb Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 67 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 70 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..4108017 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + Or ( Or (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

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Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit e106f9787f8650af367e80b32903503c830142d2 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 68 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 71 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..485d09a --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + Or ( Or (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

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Patch set updated for coreboot: soc/intel/apollolake: Add ASL methods for eMMC
by Vaibhav Shankar 22 Aug '16

22 Aug '16

Vaibhav Shankar (vaibhav.shankar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233 -gerrit commit e9459bc87d31a5794bdfc00bffe543e3b0efebf4 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Mon Aug 15 11:32:26 2016 -0700 soc/intel/apollolake: Add ASL methods for eMMC Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/acpi/scs.asl | 69 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 72 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl new file mode 100644 index 0000000..da5ace9 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + Or ( Or (CONFIG_IOSF_BASE_ADDRESS, + ShiftLeft(0xD6, 16)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (_UID, 1) + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + } /* Device (SDHA) */ + +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 5b29abb..391a531 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,5 +31,8 @@ /* LPC */ #include "lpc.asl" +/* eMMC */ +#include "scs.asl" + /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>

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New patch to review for coreboot: drivers/spi: be sure to call spi_init() before spi_flash_probe()
by Aaron Durbin 22 Aug '16

22 Aug '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16297 -gerrit commit 151926d532410a14c76e07eb6ca5472f15e63508 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Aug 22 17:41:13 2016 -0500 drivers/spi: be sure to call spi_init() before spi_flash_probe() It's necessary to call spi_init() prior to calling spi_flash_probe() such that the SPI drivers can do any work required prior to performing SPI transactions. It could be argued that the drivers should handle such situations, however the SPI API implementations seem to assume the callers ensured spi_init() was called before any SPI transactions. BUG=chrome-os-partner:56151 Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/spi/boot_device_rw_nommap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index 2a9f19f..bf15e99 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -78,6 +78,9 @@ void boot_device_init(void) if (car_get_var(sfg) != NULL) return; + /* Ensure any necessary setup is performed by the drivers. */ + spi_init(); + car_set_var(sfg, spi_flash_probe(bus, cs)); }

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coreboot-gerrit August 2016