coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

1 participants
1551 discussions

Patch set updated for coreboot: src/southbridge: Add required space before opening parenthesis '('
by HAOUAS Elyes 22 Aug '16

22 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16290 -gerrit commit e216addd5a8de609165472985b1d6002b4589dcc Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 18:36:06 2016 +0200 src/southbridge: Add required space before opening parenthesis '(' Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8132/bridge.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/early_setup.c | 6 +++--- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_bd82x6x/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_i89xx/sata.c | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +- src/southbridge/intel/fsp_rangeley/sata.c | 2 +- src/southbridge/intel/i3100/lpc.c | 6 +++--- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801ex/i82801ex.c | 4 ++-- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/sata.c | 2 +- src/southbridge/sis/sis966/aza.c | 8 ++++---- src/southbridge/sis/sis966/ide.c | 4 ++-- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/sis/sis966/nic.c | 26 +++++++++++++------------- src/southbridge/sis/sis966/sata.c | 4 ++-- src/southbridge/sis/sis966/usb.c | 4 ++-- src/southbridge/sis/sis966/usb2.c | 8 ++++---- 24 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index ee45c65..4df33da 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -386,7 +386,7 @@ static void amd8132_ioapic_init(device_t dev) } - if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { //for b1 b2 /* Errata #73 */ dword = pci_read_config32(dev, 0x80); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 7e8d8c3..efe38ab 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -46,10 +46,10 @@ void bcm5785_enable(device_t dev) else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; - if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { - if(dev->device == 0x0036) //PCI-X Bridge + if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { + if (dev->device == 0x0036) //PCI-X Bridge { devfn += (1<<3); } - else if(dev->device == 0x0223) // USB + else if (dev->device == 0x0223) // USB { devfn -= (1<<3); } } sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index e29fab4..3ddc9ca 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -47,13 +47,13 @@ static void bcm5785_enable_wdt_port_cf9(void) dword_old = pci_read_config32(dev, 0x4c); dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x4c, dword); } dword_old = pci_read_config32(dev, 0x6c); dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } @@ -149,7 +149,7 @@ static void bcm5785_enable_msg(void) // bit 1: enable upsteam messages // bit 0: enable shutdowm message to init generation dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e4e5b81..bc19b78 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 81a5d7d..6130646 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 987d6d1..77ada10 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c index 87d5431..810847a 100644 --- a/src/southbridge/intel/fsp_i89xx/sata.c +++ b/src/southbridge/intel/fsp_i89xx/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e0d19d6..27b8166 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 4861f83..624af23 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -60,7 +60,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 4d529ca..77853a8 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -200,13 +200,13 @@ static void i3100_pirq_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; - if(config->pirq_a_d) + if (config->pirq_a_d) pci_write_config32(dev, 0x60, config->pirq_a_d); - if(config->pirq_e_h) + if (config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 326a9e5..f4ab2f6 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..e018320 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -12,10 +12,10 @@ void i82801ex_enable(device_t dev) /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { + if ((dev->path.pci.devfn &0xf8)== 0xf8) { index = dev->path.pci.devfn & 7; } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { + else if ((dev->path.pci.devfn &0xf8)== 0xe8) { index = (dev->path.pci.devfn & 7) +8; } if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 9cb6f39..2fcb83d 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -118,7 +118,7 @@ static void sata_init(struct device *dev) /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ pci_write_config8(dev, 0x09, 0x8f); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index b128280..e76087c 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC: currently unused */ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4f30865..5f1a44f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index d4fbed4..d11d531 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ffeb8a2..98cd0bc 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -91,7 +91,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index a7c3319..462670e 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -105,7 +105,7 @@ static int codec_detect(u8 *base) dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId - if(dword==0) { + if (dword==0) { printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -184,7 +184,7 @@ static u32 verb_data[] = { static unsigned find_verb(u32 viddid, u32 **verb) { - if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -268,8 +268,8 @@ static void aza_init(struct device *dev) printk(BIOS_DEBUG, "****** Azalia PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ + for (i=0;i<0xff;i+=4){ + if ((i%16)==0){ printk(BIOS_DEBUG, "\n%02x: ", i); } printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index f3fa079..6b939e7 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -148,8 +148,8 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); printk(BIOS_DEBUG, "****** IDE PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0a5adf0..ef26745 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -139,7 +139,7 @@ static void lpc_init(device_t dev) } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } - if( byte != byte_old) { + if ( byte != byte_old) { outb(byte, 0x70); } diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index cd376ab..2144350 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for(i = 0x9 ; i <=0xe ; i++) + for (i = 0x9 ; i <=0xe ; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } @@ -98,7 +98,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for(i = 0 ; i <3; i++) + for (i = 0 ; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); @@ -142,11 +142,11 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for(i=0 ; i <= LoopNum; i++) + for (i=0 ; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); - if(!(ulValue & 0x0080)) //BIT_7 + if (!(ulValue & 0x0080)) //BIT_7 break; mdelay(100); @@ -154,7 +154,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(50); - if(i==LoopNum) data=0x10000; + if (i==LoopNum) data=0x10000; else{ ulValue=read32(base + 0x3c); data = ((ulValue & 0xffff0000) >> 16); @@ -205,13 +205,13 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() // Scan all PHY address(0 ~ 31) to find a valid PHY - for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) + for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) // Found a valid PHY - if((usData != 0x0) && (usData != 0xffff)) + if ((usData != 0x0) && (usData != 0xffff)) { bFoundPhy = TRUE; break; @@ -219,7 +219,7 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() } - if(!bFoundPhy) + if (!bFoundPhy) { printk(BIOS_DEBUG, "PHY not found !!!! \n"); } @@ -260,7 +260,7 @@ static void nic_init(struct device *dev) res = find_resource(dev, 0x10); - if(!res) + if (!res) { printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; @@ -268,7 +268,7 @@ static void nic_init(struct device *dev) base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "NIC base address %p\n",base); - if(!(val=phy_detect(base,&PhyAddr))) + if (!(val=phy_detect(base,&PhyAddr))) { printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; @@ -276,7 +276,7 @@ static void nic_init(struct device *dev) ulValue=read32(base + 0x38L); // check EEPROM existing - if((ulValue & 0x0002)) + if ((ulValue & 0x0002)) { // read MAC address from EEPROM at first @@ -311,8 +311,8 @@ static void nic_init(struct device *dev) printk(BIOS_DEBUG, "****** NIC PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 197f4d2..eb69ab0 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -150,8 +150,8 @@ for (i=0;i<10;i++){ printk(BIOS_DEBUG, "****** SATA PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index 95f01d1..64398e2 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -75,8 +75,8 @@ static void usb_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 5bad6b3..8c34723 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -72,7 +72,7 @@ static void usb2_init(struct device *dev) //-------------- enable USB2.0 (SiS7002) ---------------------- i = 0; - while(SiS_SiS7002_init[i][0] != 0) + while (SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); temp8 &= SiS_SiS7002_init[i][1]; @@ -82,7 +82,7 @@ static void usb2_init(struct device *dev) }; res = find_resource(dev, 0x10); - if(!res) + if (!res) return; base = res2mmio(res, 0, 0); @@ -94,8 +94,8 @@ static void usb2_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); }

1 0

New patch to review for coreboot: i945.h: fix #include path
by Antonello Dettori 22 Aug '16

22 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16294 -gerrit commit a99ed6c514bb22cbb5ad335f3cf5f43789d49b8e Author: Antonello Dettori <dev(a)dettori.io> Date: Sun Aug 21 10:51:53 2016 +0200 i945.h: fix #include path Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/intel/i945/i945.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 0536a36..d4b7c7f 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -28,7 +28,7 @@ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__

1 0

New patch to review for coreboot: [WIP] src: replace device_t type with pnp/pci_defn_t
by Antonello Dettori 22 Aug '16

22 Aug '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16293 -gerrit commit 1f44343b0caa818c31e8952d9fc318053cd5b7dd Author: Antonello Dettori <dev(a)dettori.io> Date: Sun Aug 21 18:26:05 2016 +0200 [WIP] src: replace device_t type with pnp/pci_defn_t Replace device_t type with pnp/pci_defn_t. Change-Id: Iec2d14a5afd85c5268601c72ed31f9311dfe1982 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/device/pci_early.c | 6 +++--- src/drivers/net/ne2k.c | 2 +- src/include/device/pci.h | 6 +++--- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/kfsn4-dre/romstage.c | 4 ++-- src/mainboard/asus/kfsn4-dre_k8/romstage.c | 4 ++-- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/am1ml/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 2 +- src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 2 +- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/d510mo/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 6 +++--- src/mainboard/kontron/ktqm77/romstage.c | 6 +++--- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 8 ++++---- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++-- src/mainboard/tyan/s8226/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 8 ++++---- src/mainboard/via/vt8454c/romstage.c | 2 +- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdk8/early_ht.c | 4 ++-- src/northbridge/amd/lx/northbridge.h | 1 - src/northbridge/intel/e7505/debug.c | 6 +++--- src/northbridge/intel/e7505/raminit.h | 2 +- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_rangeley/port_access.c | 4 +--- src/northbridge/intel/i945/debug.c | 4 ++-- src/northbridge/intel/nehalem/acpi.c | 2 +- src/soc/intel/apollolake/spi.c | 2 +- src/soc/intel/broadwell/romstage/pch.c | 2 +- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/skylake/romstage/pch.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 2 +- src/southbridge/amd/agesa/hudson/early_setup.c | 4 ++-- src/southbridge/amd/cimx/sb700/early.c | 6 +++--- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 6 +++--- src/southbridge/intel/fsp_i89xx/romstage.c | 2 +- src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +- src/southbridge/intel/fsp_rangeley/early_usb.c | 2 +- src/southbridge/intel/i82371eb/early_pm.c | 2 +- src/southbridge/intel/i82371eb/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/i82801dx.h | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801gx/i82801gx.h | 5 ++++- 63 files changed, 95 insertions(+), 95 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 7107738..611b31b 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -73,7 +73,7 @@ unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) #if CONFIG_EARLY_PCI_BRIDGE -static void pci_bridge_reset_secondary(device_t p2p_bridge) +static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) { u16 reg16; @@ -90,7 +90,7 @@ static void pci_bridge_reset_secondary(device_t p2p_bridge) pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); } -static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) { /* Disable config transaction forwarding. */ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); @@ -100,7 +100,7 @@ static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); } -static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) { u16 reg16; diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index b59fe08..0b16bf0 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -394,7 +394,7 @@ static void ns8390_reset(unsigned int eth_nic_base) int ne2k_init(unsigned int eth_nic_base) { - device_t dev; + pci_devfn_t dev; unsigned char c; /* Power management controller */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 9ef3614..e167752 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -108,13 +108,13 @@ static inline const struct pci_operations *ops_pci(device_t dev) #endif /* ! __SIMPLE_DEVICE__ */ -#ifdef __PRE_RAM__ +#ifdef __SIMPLE_DEVICE__ unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(pci_devfn_t dev, unsigned cap); -#else /* !__PRE_RAM__ */ +#else /* !__SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 30a1a2a..e6b8ef5 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4d965e7..4a33f77 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -84,7 +84,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 709dbcd..0e502e7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -62,7 +62,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 14d529c..0f98062 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -82,7 +82,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 05ba1f9..0889f24 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -82,7 +82,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -133,7 +133,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index fe83ca8..b547461 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -80,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) */ unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus); @@ -131,7 +131,7 @@ static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit for (i = 0; i < 4; i++) { u32 id; - device_t dev; + pci_devfn_t dev; if (i == 0) /* SB chain */ dev = PCI_DEV(i * 0x40, bus_unit_id, 0); else diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index f9e5d46..3bf54db 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -76,7 +76,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 544873c..daf0b50 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -101,7 +101,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index bceecf8..9eacecf 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -85,7 +85,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -183,7 +183,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n"); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index f2144ff..0a3ba72 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -42,7 +42,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 12d9eee..d7da2bb 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u8 byte; - device_t dev; + pci_devfn_t dev; u32 *addr32; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 396a2ec..0447019 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -103,19 +103,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -124,7 +124,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x4e, 0x00); diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index be6043a..dd889d1 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -33,7 +33,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -static void it8728f_b75md3h_disable_reboot(device_t dev) +static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ ite_reg_write(dev, 0xEF, 0x7E); // magic diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 55a2a96..fcdac6d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -33,7 +33,7 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> -static void it8728f_b75md3v_disable_reboot(device_t dev) +static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev) { /* GPIO SIO settings */ ite_reg_write(dev, 0xEF, 0x7E); // magic diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index b6be8fb..2503db9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -41,7 +41,7 @@ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; /* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9d2b90a..4496922 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -74,7 +74,7 @@ static void ich7_enable_lpc(void) */ static void early_superio_config_w83627ehg(void) { - device_t dev; + pnp_devfn_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index 9abeaf9..d35e9e7 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -64,7 +64,7 @@ void main(unsigned long bist) console_init(); /* Enable COM3. */ - device_t dev = PNP_DEV(0x2e, 0x0b); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 998528d..ae1b36c 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -51,7 +51,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index f73bf64..bf390c9 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -38,7 +38,7 @@ /* Early mainboard specific GPIO setup */ static void mb_gpio_init(void) { - device_t dev; + pci_devfn_t dev; /* Southbridge GPIOs. */ dev = PCI_DEV(0x0, 0x1f, 0x0); diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 069b6ad..aa0eadc 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -41,7 +41,7 @@ void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 0de239c..d479072 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -46,7 +46,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 3dcf4cc..d2f6684 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -76,14 +76,14 @@ static void ich7_enable_lpc(void) } /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(device_t dev) +static void pnp_enter_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_func_mode(device_t dev) +static void pnp_exit_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -96,7 +96,7 @@ static void pnp_exit_func_mode(device_t dev) */ static void early_superio_config_w83627thg(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 973119b..ade2a78 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -63,14 +63,14 @@ void rcba_config(void) RCBA32(FD) = reg32; } -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -80,7 +80,7 @@ void mainboard_config_superio(void) { int lvds_3v = 0; // 0 (5V) or 1 (3V3) int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled - device_t dev = PNP_DEV(0x2e, 0x9); + pnp_devfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 3ed6afd..d3cd90c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -95,7 +95,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index aabbf65..c735ce2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -102,7 +102,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pnp_devfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index f3af5fa..bdb2051 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -90,19 +90,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pnp_devfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -111,7 +111,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pnp_devfn_t dev; dev=PNP_DEV(0x2e, 0x00); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..9ed71b7 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -84,7 +84,7 @@ static void default_superio_gpio_setup(void) GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + const pnp_devfn_t sio = PNP_DEV(0x2e, 0); /* Enter super-io's configuration state. */ pnp_enter_conf_state(sio); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 4661f45..c9178b8 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -113,14 +113,14 @@ static const u8 spd_addr[] = { #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index ea877b7..7460f20 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x31); /* For serial port. */ - device_t dev = PCI_DEV(0, 0x14, 3); + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index a28bf78..71f00c9 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -39,7 +39,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 83af426..26ee24f 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -50,7 +50,7 @@ */ static int acpi_is_wakeup_early_via_vx800(void) { - device_t dev; + pci_devfn_t dev; u16 tmp, result; printk(BIOS_DEBUG, "In acpi_is_wakeup_early_via_vx800\n"); @@ -76,7 +76,7 @@ static int acpi_is_wakeup_early_via_vx800(void) /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; #if 0 /* * Add and close this switch, since some line cause error, some @@ -370,8 +370,8 @@ void main(unsigned long bist) { u16 boot_mode; u8 rambits, Data8, Data; - device_t device; - /* device_t dev; */ + pci_devfn_t device; + /* pci_devfn_t dev; */ /* * Enable multifunction for northbridge. These 4 lines (until diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index d2af46c..114494b 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -33,7 +33,7 @@ static void enable_mainboard_devices(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 3e59a32..d292eb9 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -93,7 +93,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 1bc34e4..eb91371 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -13,7 +13,7 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid; - device_t dev; + pci_devfn_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; @@ -61,7 +61,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. diff --git a/src/northbridge/amd/lx/northbridge.h b/src/northbridge/amd/lx/northbridge.h index 1e0e650..9a4ff29 100644 --- a/src/northbridge/amd/lx/northbridge.h +++ b/src/northbridge/amd/lx/northbridge.h @@ -19,7 +19,6 @@ #include <cpu/amd/lxdef.h> /* northbridge.c */ -unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void); /* northbridgeinit.c */ diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index cdf6e7e..cef0f3a 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -21,7 +21,7 @@ void print_debug_pci_dev(unsigned dev) void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -54,7 +54,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -71,7 +71,7 @@ void dump_pci_devices(void) void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..979ae0a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -6,7 +6,7 @@ #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) struct mem_controller { - device_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller + pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller // SMBus addresses of DIMM slots for each channel, // in order from closest to MCH to furthest away diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 61931fd..db219c5 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -72,7 +72,7 @@ void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); void report_platform_info(void); -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) void northbridge_acpi_fill_ssdt_generator(device_t device); #endif diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c index c4730a9..1ec423e 100644 --- a/src/northbridge/intel/fsp_rangeley/port_access.c +++ b/src/northbridge/intel/fsp_rangeley/port_access.c @@ -14,9 +14,7 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +#define __SIMPLE_DEVICE__ // Use simple device model even in ramstage #include <stdint.h> #include <arch/io.h> diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index d26e84e..65189bd 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -23,7 +23,7 @@ void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -61,7 +61,7 @@ void dump_pci_device(unsigned dev) void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for(dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index 42761fa..3471282 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -130,7 +130,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion) /* Initialize IGD OpRegion, called from ACPI code */ int init_igd_opregion(igd_opregion_t * opregion) { - device_t igd; + pci_devfn_t igd; u16 reg16; memset((void *)opregion, 0, sizeof(igd_opregion_t)); diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 7b390bb..ae8c7a7 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -47,7 +47,7 @@ enum errors { /* Reduce data-passing burden by grouping transaction data in a context. */ struct spi_ctx { uintptr_t mmio_base; - device_t pci_dev; + pci_devfn_t pci_dev; uint32_t hsfsts_on_last_error; }; diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 74d3125..03a9f9b 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -131,7 +131,7 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(pci_devfn_t dev, int reg, u32 mask, u32 or) { u32 reg32; diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 1ea7cc2..ed03418 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -48,7 +48,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + pci_devfn_t dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c index 26677e8..47d0020 100644 --- a/src/soc/intel/skylake/romstage/pch.c +++ b/src/soc/intel/skylake/romstage/pch.c @@ -81,7 +81,7 @@ static void pch_enable_lpc(void) static void pch_device_init(void) { - device_t dev; + pci_devfn_t dev; u32 reg32; u16 tcobase; u16 tcocnt; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 56a5a92..9aa1457 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -241,7 +241,7 @@ void soc_after_ram_init(struct romstage_params *params) * init and MRC cache is saved. */ u32 disb_val = 0; - device_t dev = PCH_DEV_PMC; + pci_devfn_t dev = PCH_DEV_PMC; disb_val = pci_read_config32(dev, GEN_PMCON_A); disb_val |= DISB; /* Preserve bits which get cleared up if written 1 */ diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 57119f9..1cdaa05 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -28,7 +28,7 @@ void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -73,7 +73,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 5af2a5e..d706a56 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -30,7 +30,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( @@ -65,7 +65,7 @@ void sb_Poweron_Init(void) void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ @@ -79,7 +79,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base) void sb7xx_51xx_disable_wideio(u8 wio_index) { /* TODO: Now assume wio_index=0 */ - device_t dev; + pci_devfn_t dev; u8 reg8; //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 2a10c0e..c6d8393 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -28,7 +28,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index f4fcf8b..dce1620 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -60,7 +60,7 @@ void configure_hudson_uart(void) void hudson_pci_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); @@ -105,7 +105,7 @@ void hudson_pci_port80(void) void hudson_lpc_port80(void) { u8 byte; - device_t dev; + pci_devfn_t dev; /* Enable LPC controller */ outb(0xEC, 0xCD6); @@ -123,7 +123,7 @@ void hudson_lpc_port80(void) void hudson_lpc_decode(void) { - device_t dev; + pci_devfn_t dev; u32 tmp = 0; /* Enable I/O decode to LPC bus */ diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c5c1136..714796b 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -50,7 +50,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index ee8c40c..f27fa87 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c index edcd500..dfd8cc2 100644 --- a/src/southbridge/intel/fsp_rangeley/early_usb.c +++ b/src/southbridge/intel/fsp_rangeley/early_usb.c @@ -31,7 +31,7 @@ */ void enable_usb_bar(void) { - device_t usb0 = SOC_EHCI1_DEV; + pci_devfn_t usb0 = SOC_EHCI1_DEV; u32 cmd; /* USB Controller 0 */ diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 0605d10..1794393 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -23,7 +23,7 @@ void enable_pm(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16; diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 69e967a..af6b14b 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -24,7 +24,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; u8 reg8; u16 reg16; diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 3a7d2b0..5bf87d8 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -22,7 +22,7 @@ void enable_smbus(void) { - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 821ed2c..bab59df 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -30,7 +30,7 @@ #include <arch/acpi.h> #if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) +#if !defined(__PRE_RAM__) && !defined(__SIMPLE_DEVICE__) #include "chip.h" extern void i82801dx_enable(device_t dev); #else diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 326a9e5..74d5a0c 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -240,7 +240,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 2f9cdeb..47fe5f6 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -23,7 +23,7 @@ void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; /* Set the SMBus device statically. */ dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d4adc18..247ab92 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -16,7 +16,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H -#include <arch/acpi.h> +#include <device/device.h> /* * It does not matter where we put the SMBus I/O base, as long as we @@ -43,6 +43,9 @@ #if !defined(__ASSEMBLER__) #if !defined(__PRE_RAM__) #include "chip.h" +#if defined(__SIMPLE_DEVICE__) +typedef uint32_t device_t; +#endif extern void i82801gx_enable(device_t dev); void gpi_route_interrupt(u8 gpi, u8 mode); #else

1 0

Patch set updated for coreboot: src/cpu: space required before the open parenthesis '('
by HAOUAS Elyes 22 Aug '16

22 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16286 -gerrit commit c9d5b69f1d6528660e88cdc438c2b526689f7a5d Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 17:33:56 2016 +0200 src/cpu: space required before the open parenthesis '(' Change-Id: I7fb9bfcaeec0b9dfd0695d2b2d398fd01091f6bc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/dualcore/amd_sibling.c | 20 ++++++++++---------- src/cpu/amd/dualcore/dualcore.c | 6 +++--- src/cpu/amd/dualcore/dualcore_id.c | 2 +- src/cpu/amd/family_10h-family_15h/processor_name.c | 2 +- src/cpu/amd/model_fxx/powernow_acpi.c | 6 +++--- src/cpu/amd/model_fxx/processor_name.c | 8 ++++---- src/cpu/amd/mtrr/amd_mtrr.c | 6 +++--- src/cpu/amd/quadcore/amd_sibling.c | 12 ++++++------ src/cpu/amd/quadcore/quadcore_id.c | 2 +- src/cpu/intel/hyperthreading/intel_sibling.c | 2 +- src/cpu/intel/microcode/microcode.c | 2 +- src/cpu/intel/speedstep/acpi.c | 2 +- src/cpu/via/nano/nano_init.c | 8 ++++---- src/cpu/via/nano/update_ucode.c | 18 +++++++++--------- src/cpu/x86/lapic/lapic_cpu_init.c | 14 +++++++------- src/cpu/x86/pae/pgtbl.c | 4 ++-- 16 files changed, 57 insertions(+), 57 deletions(-) diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index e0723ce..8c299b0 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -37,11 +37,11 @@ static int get_max_siblings(int nodes) int siblings=0; //get max siblings from all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ int j; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3)); j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if(siblings < j) { + if (siblings < j) { siblings = j; } } @@ -55,7 +55,7 @@ static void enable_apic_ext_id(int nodes) int nodeid; //enable APIC_EXIT_ID all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ uint32_t val; dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0)); val = pci_read_config32(dev, 0x68); @@ -82,9 +82,9 @@ unsigned get_apicid_base(unsigned ioapic_num) siblings = get_max_siblings(nodes); - if(bsp_apic_id > 0) { // io apic could start from 0 + if (bsp_apic_id > 0) { // io apic could start from 0 return 0; - } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 + } else if (pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0 return 1; } @@ -92,11 +92,11 @@ unsigned get_apicid_base(unsigned ioapic_num) #if 0 //it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it. - if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) { + if (nb_cfg_54 && (!disable_siblings) && (siblings == 0)) { //we need to check if e0 single core is there int i; - for(i=0; i<nodes; i++) { - if(is_e0_later_in_bsp(i)) { + for (i=0; i<nodes; i++) { + if (is_e0_later_in_bsp(i)) { siblings = 1; break; } @@ -106,7 +106,7 @@ unsigned get_apicid_base(unsigned ioapic_num) //Construct apicid_base - if((!disable_siblings) && (siblings>0) ) { + if ((!disable_siblings) && (siblings>0) ) { /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't know when the kernel can support 256 apic id. (APIC_EXT_ID is enabled) */ @@ -120,7 +120,7 @@ unsigned get_apicid_base(unsigned ioapic_num) apicid_base = nodes; } - if((apicid_base+ioapic_num-1)>0xf) { + if ((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n"); enable_apic_ext_id(nodes); diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c index a545762..56f7dcc 100644 --- a/src/cpu/amd/dualcore/dualcore.c +++ b/src/cpu/amd/dualcore/dualcore.c @@ -18,7 +18,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid) static inline uint8_t set_apicid_cpuid_lo(void) { #if !CONFIG_K8_REV_F_SUPPORT - if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set + if (is_cpu_pre_e0()) return 0; // pre_e0 can not be set #endif // set the NB_CFG[54]=1; why the OS will be happy with that ??? @@ -55,8 +55,8 @@ static inline void start_other_cores(void) nodes = get_nodes(); - for(nodeid=0; nodeid<nodes; nodeid++) { - if( get_core_num_in_bsp(nodeid) > 0) { + for (nodeid=0; nodeid<nodes; nodeid++) { + if ( get_core_num_in_bsp(nodeid) > 0) { real_start_other_core(nodeid); } } diff --git a/src/cpu/amd/dualcore/dualcore_id.c b/src/cpu/amd/dualcore/dualcore_id.c index 4fcedae..bbfdd51 100644 --- a/src/cpu/amd/dualcore/dualcore_id.c +++ b/src/cpu/amd/dualcore/dualcore_id.c @@ -26,7 +26,7 @@ struct node_core_id get_node_core_id(unsigned nb_cfg_54) { struct node_core_id id; // get the apicid via cpuid(1) ebx[27:24] - if( nb_cfg_54) { + if ( nb_cfg_54) { // when NB_CFG[54] is set, nodeid = ebx[27:25], coreid = ebx[24] id.coreid = (cpuid_ebx(1) >> 24) & 0xf; id.nodeid = (id.coreid>>CORE_ID_BIT); diff --git a/src/cpu/amd/family_10h-family_15h/processor_name.c b/src/cpu/amd/family_10h-family_15h/processor_name.c index 3d92ee2..bda8409 100644 --- a/src/cpu/amd/family_10h-family_15h/processor_name.c +++ b/src/cpu/amd/family_10h-family_15h/processor_name.c @@ -331,7 +331,7 @@ int init_processor_name(void) processor_name_string = unknown2; /* String 2 */ - for(i = 0; str2[i].value; i++) { + for (i = 0; str2[i].value; i++) { if ((str2[i].Pg == Pg) && ((str2[i].NC == NC) || !str2_checkNC) && (str2[i].String == String2)) { diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index d64c6d9..52138a1 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -775,7 +775,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */ cpuid1 = cpuid(0x80000007); - if((cpuid1.edx & 0x6)!=0x6) { + if ((cpuid1.edx & 0x6)!=0x6) { printk(BIOS_INFO, "Processor not capable of performing P-state transitions\n"); return; } @@ -845,7 +845,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) Pstate_vid[0] = Max_vid; Pstate_power[0] = data->pwr * 100; - for(Pstate_num = 1; + for (Pstate_num = 1; (Pstate_num <= MAXP) && (data->pstates[Pstate_num - 1].freqMhz != 0); Pstate_num++) { Pstate_fid[Pstate_num] = freq_to_fid(data->pstates[Pstate_num - 1].freqMhz) & 0x3f; @@ -862,7 +862,7 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) /* Loop over all CPU's */ for (dev = 0x18; dev < 0x1c; dev++) { - if(dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL) + if (dev_find_slot(0, PCI_DEVFN(dev, 0)) == NULL) continue; for (i = 0; i < (cmp_cap + 1); i++) { diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c index 2e2ad39..60dbf6e 100644 --- a/src/cpu/amd/model_fxx/processor_name.c +++ b/src/cpu/amd/model_fxx/processor_name.c @@ -118,10 +118,10 @@ int init_processor_name(void) EightBitBrandId = cpuid_ebx(0x00000001) & 0xff; BrandId = cpuid_ebx(0x80000001) & 0xffff; - if(!EightBitBrandId && !BrandId) { + if (!EightBitBrandId && !BrandId) { BrandTableIndex = 0; NN = 0xffffff; - } else if(!EightBitBrandId) { + } else if (!EightBitBrandId) { BrandTableIndex = (BrandId >> 6) & 0x3f; // BrandId[11:6] NN = BrandId & 0x3f; // // BrandId[6:0] } else { @@ -392,7 +392,7 @@ int init_processor_name(void) */ for (i=0; i<47; i++) { // 48 -1 - if(program_string[i] == program_string[i+1]) { + if (program_string[i] == program_string[i+1]) { switch (program_string[i]) { #if !CONFIG_K8_REV_F_SUPPORT case 'X': ModelNumber = 22+ NN; break; @@ -412,7 +412,7 @@ int init_processor_name(void) #endif } - if(ModelNumber && ModelNumber < 100) { + if (ModelNumber && ModelNumber < 100) { // No idea what to do with RR=100. According // to the revision guide this is possible. // diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 6df8458..a0a5194 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -88,7 +88,7 @@ void amd_setup_mtrrs(void) (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables - if(has_tom2wb) + if (has_tom2wb) printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); /* Enable the access to AMD RdDram and WrDram extension bits */ @@ -109,7 +109,7 @@ void amd_setup_mtrrs(void) sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB); if (bsp_topmem2() > (uint64_t)1<<32) { sys_cfg.lo |= SYSCFG_MSR_TOM2En; - if(has_tom2wb) + if (has_tom2wb) sys_cfg.lo |= SYSCFG_MSR_TOM2WB; } @@ -117,7 +117,7 @@ void amd_setup_mtrrs(void) * undefined side effects. */ msr.lo = msr.hi = 0; - for(i = IORR_FIRST; i <= IORR_LAST; i++) { + for (i = IORR_FIRST; i <= IORR_LAST; i++) { wrmsr(i, msr); } diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index 397a3dd..22910f8 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -41,11 +41,11 @@ static u32 get_max_siblings(u32 nodes) u32 siblings=0; //get max siblings from all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ int j; dev = get_node_pci(nodeid, 3); j = (pci_read_config32(dev, 0xe8) >> 12) & 3; - if(siblings < j) { + if (siblings < j) { siblings = j; } } @@ -60,7 +60,7 @@ static void enable_apic_ext_id(u32 nodes) u32 nodeid; //enable APIC_EXIT_ID all the nodes - for(nodeid=0; nodeid<nodes; nodeid++){ + for (nodeid=0; nodeid<nodes; nodeid++){ u32 val; dev = get_node_pci(nodeid, 0); val = pci_read_config32(dev, 0x68); @@ -82,7 +82,7 @@ u32 get_apicid_base(u32 ioapic_num) siblings = get_max_siblings(sysconf.nodes); - if(sysconf.bsp_apicid > 0) { // io apic could start from 0 + if (sysconf.bsp_apicid > 0) { // io apic could start from 0 return 0; } else if (sysconf.enabled_apic_ext_id) { // enabled ext id but bsp = 0 return 1; @@ -93,7 +93,7 @@ u32 get_apicid_base(u32 ioapic_num) //Construct apicid_base - if((!disable_siblings) && (siblings>0) ) { + if ((!disable_siblings) && (siblings>0) ) { /* for 8 way dual core, we will used up apicid 16:16, actually 16 is not allowed by current kernel and the kernel will try to get one that is small than 16 to make io apic work. I don't @@ -108,7 +108,7 @@ u32 get_apicid_base(u32 ioapic_num) apicid_base = sysconf.nodes; } - if((apicid_base+ioapic_num-1)>0xf) { + if ((apicid_base+ioapic_num-1)>0xf) { // We need to enable APIC EXT ID printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n"); enable_apic_ext_id(sysconf.nodes); diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index b89aac7..cd83906 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -75,7 +75,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) * The apicid format varies based on processor revision */ apicid = (cpuid_ebx(1) >> 24) & 0xff; - if( nb_cfg_54) { + if ( nb_cfg_54) { if (fam15h && dual_node) { id.coreid = apicid & 0x1f; id.nodeid = (apicid & 0x60) >> 5; diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index de59c18..aeb5874 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -85,7 +85,7 @@ void intel_sibling_init(struct device *cpu) } /* I am the primary CPU start up my siblings */ - for(i = 1; i < siblings; i++) { + for (i = 1; i < siblings; i++) { struct device_path cpu_path; struct device *new; /* Build the CPU device path */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index b068141..0b0f21d 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -175,7 +175,7 @@ const void *intel_microcode_find(void) } /* Checkpoint 1: The microcode update falls within CBFS */ - if(update_size > microcode_len) { + if (update_size > microcode_len) { #if !defined(__ROMCC__) printk(BIOS_WARNING, "Microcode header corrupted!\n"); #endif diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 009d419..d85e487 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void) { struct device *cpu; int count = 0; - for(cpu = all_devices; cpu; cpu = cpu->next) { + for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { continue; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index cdf0589..2918398 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -74,7 +74,7 @@ static void nano_set_max_fid_vid(void) printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", cur_vid, min_vid, max_vid); - if( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) { /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; @@ -121,7 +121,7 @@ static void nano_power(void) wrmsr(MSR_IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; - if(stepping >= MODEL_NANO_3000_B0) { + if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(MSR_IA32_MISC_ENABLE); @@ -143,7 +143,7 @@ static void nano_init(struct device *dev) get_fms(&c, dev->device); /* We didn't test this on the Nano 1000/2000 series, so warn the user */ - if(c.x86_mask < MODEL_NANO_3000_B0) { + if (c.x86_mask < MODEL_NANO_3000_B0) { printk(BIOS_EMERG, "WARNING: This CPU has not been tested. " "Please report any issues encountered. \n"); } @@ -166,7 +166,7 @@ static void nano_init(struct device *dev) * CBFS, we'll just get back with 0 updates. User choice FTW. */ unsigned int n_updates = nano_update_ucode(); - if(n_updates != 0){ + if (n_updates != 0){ nano_power(); } else { /* Changing the frequency or voltage without first updating the diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 44b074e..fc5c9d5 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -51,10 +51,10 @@ static void nano_print_ucode_info(const nano_ucode_header *ucode) static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) { /* We must have a valid signature */ - if(ucode->signature != NANO_UCODE_SIGNATURE) + if (ucode->signature != NANO_UCODE_SIGNATURE) return NANO_UCODE_SIGNATURE_ERROR; /* The size of the head must be exactly 12 double words */ - if( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) return NANO_UCODE_WRONG_SIZE; /* How about a checksum ? Checksum must be 0 @@ -62,10 +62,10 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) int i; u32 check = 0; u32 *raw = (void*) ucode; - for(i = 0 ; i < ((ucode->total_size) >> 2); i++) { + for (i = 0 ; i < ((ucode->total_size) >> 2); i++) { check += raw[i]; } - if(check != 0) + if (check != 0) return NANO_UCODE_CHECKSUM_FAIL; /* Made it here huh? Then it looks valid to us. * If there's anything else wrong, the CPU will reject the update */ @@ -110,7 +110,7 @@ unsigned int nano_update_ucode(void) ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", CBFS_TYPE_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ - if(ucode_data == NULL) { + if (ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " "Aborting microcode updates\n"); return 0; @@ -119,11 +119,11 @@ unsigned int nano_update_ucode(void) /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ - for( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) { ucode_update_status stat; const nano_ucode_header * ucode = (void *)(&ucode_data[i]); - if(nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { + if (nano_ucode_is_valid(ucode) != NANO_UCODE_VALID) { i++; continue; } @@ -132,14 +132,14 @@ unsigned int nano_update_ucode(void) * microcode */ i += (ucode->total_size >> 2); /* Is the microcode compatible with our CPU? */ - if(ucode->applicable_fms != fms) continue; + if (ucode->applicable_fms != fms) continue; /* For our most curious users */ nano_print_ucode_info(ucode); /* The meat of the pie */ stat = nano_apply_ucode(ucode); /* The user might want to know how the update went */ nano_print_ucode_status(stat); - if(stat == UCODE_UPDATE_SUCCESS) n_updates++; + if (stat == UCODE_UPDATE_SUCCESS) n_updates++; } return n_updates; diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index aaeceef..c220425 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -284,7 +284,7 @@ int start_cpu(struct device *cpu) printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index, (void *)stack_base, (void *)stack_end); /* poison the stack */ - for(stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++) + for (stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++) stack[i/sizeof(*stack)] = 0xDEADBEEF; stacks[index] = stack; /* Record the index and which CPU structure we are using */ @@ -307,7 +307,7 @@ int start_cpu(struct device *cpu) if (result) { result = 0; /* Wait 1s or until the new CPU calls in */ - for(count = 0; count < 100000 ; count++) { + for (count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; break; @@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu) struct device *cpu; /* Loop through the cpus once getting them started */ - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -471,7 +471,7 @@ static void smm_other_cpus(struct bus *cpu_bus, device_t bsp_cpu) /* Loop through the cpus once to let them run through SMM relocator */ - for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -507,7 +507,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) /* Now loop until the other cpus have finished initializing */ old_active_count = 1; active_count = atomic_read(&active_cpus); - while(active_count > 1) { + while (active_count > 1) { if (active_count != old_active_count) { printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1); @@ -517,7 +517,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) active_count = atomic_read(&active_cpus); loopcount++; } - for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { + for (cpu = cpu_bus->children; cpu; cpu = cpu->sibling) { if (cpu->path.type != DEVICE_PATH_APIC) { continue; } @@ -531,7 +531,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus) } printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount); checkstack(_estack, 0); - for(i = 1; i <= last_cpu_index; i++) + for (i = 1; i <= last_cpu_index; i++) checkstack((void *)stacks[i] + CONFIG_STACK_SIZE, i); } diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index 9be415d..2dacc10 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -78,12 +78,12 @@ void *map_2M_page(unsigned long page) pdp[2].addr_lo = ((uint32_t)&pd[512*2])|1; pdp[3].addr_lo = ((uint32_t)&pd[512*3])|1; /* The first half of the page table is identity mapped */ - for(i = 0; i < 1024; i++) { + for (i = 0; i < 1024; i++) { pd[i].addr_lo = ((i & 0x3ff) << 21)| 0xE3; pd[i].addr_hi = 0; } /* The second half of the page table holds the mapped page */ - for(i = 1024; i < 2048; i++) { + for (i = 1024; i < 2048; i++) { pd[i].addr_lo = ((window & 1) << 31) | ((i & 0x3ff) << 21) | 0xE3; pd[i].addr_hi = (window >> 1); }

1 0

Patch set updated for coreboot: src/southbridge: space required before the open parenthesis '('
by HAOUAS Elyes 22 Aug '16

22 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16290 -gerrit commit 7baa69ed3b875c8931e57dd7c08b49b0854f2073 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Aug 21 18:36:06 2016 +0200 src/southbridge: space required before the open parenthesis '(' Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/amd8132/bridge.c | 2 +- src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++--- src/southbridge/broadcom/bcm5785/early_setup.c | 6 +++--- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_bd82x6x/sata.c | 2 +- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 2 +- src/southbridge/intel/fsp_i89xx/sata.c | 2 +- src/southbridge/intel/fsp_i89xx/smihandler.c | 2 +- src/southbridge/intel/fsp_rangeley/sata.c | 2 +- src/southbridge/intel/i3100/lpc.c | 6 +++--- src/southbridge/intel/i82801dx/smihandler.c | 2 +- src/southbridge/intel/i82801ex/i82801ex.c | 4 ++-- src/southbridge/intel/i82801gx/sata.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/i82801ix/smihandler.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/sata.c | 2 +- src/southbridge/sis/sis966/aza.c | 8 ++++---- src/southbridge/sis/sis966/ide.c | 4 ++-- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/sis/sis966/nic.c | 26 +++++++++++++------------- src/southbridge/sis/sis966/sata.c | 4 ++-- src/southbridge/sis/sis966/usb.c | 4 ++-- src/southbridge/sis/sis966/usb2.c | 8 ++++---- 24 files changed, 52 insertions(+), 52 deletions(-) diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index ee45c65..4df33da 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -386,7 +386,7 @@ static void amd8132_ioapic_init(device_t dev) } - if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { //for b1 b2 /* Errata #73 */ dword = pci_read_config32(dev, 0x80); diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c index 7e8d8c3..efe38ab 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785.c @@ -46,10 +46,10 @@ void bcm5785_enable(device_t dev) else { // same bus unsigned devfn; devfn = (dev->path.pci.devfn) & ~7; - if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { - if(dev->device == 0x0036) //PCI-X Bridge + if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { + if (dev->device == 0x0036) //PCI-X Bridge { devfn += (1<<3); } - else if(dev->device == 0x0223) // USB + else if (dev->device == 0x0223) // USB { devfn -= (1<<3); } } sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index e29fab4..3ddc9ca 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -47,13 +47,13 @@ static void bcm5785_enable_wdt_port_cf9(void) dword_old = pci_read_config32(dev, 0x4c); dword = dword_old | (1<<4); //enable Timer Func - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x4c, dword); } dword_old = pci_read_config32(dev, 0x6c); dword = dword_old | (1<<9); //unhide Timer Func in pci space - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } @@ -149,7 +149,7 @@ static void bcm5785_enable_msg(void) // bit 1: enable upsteam messages // bit 0: enable shutdowm message to init generation dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor - if(dword != dword_old ) { + if (dword != dword_old ) { pci_write_config32(dev, 0x6c, dword); } } diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index e4e5b81..bc19b78 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 81a5d7d..6130646 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 987d6d1..77ada10 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c index 87d5431..810847a 100644 --- a/src/southbridge/intel/fsp_i89xx/sata.c +++ b/src/southbridge/intel/fsp_i89xx/sata.c @@ -52,7 +52,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e0d19d6..27b8166 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c index 4861f83..624af23 100644 --- a/src/southbridge/intel/fsp_rangeley/sata.c +++ b/src/southbridge/intel/fsp_rangeley/sata.c @@ -60,7 +60,7 @@ static void sata_init(struct device *dev) reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); /* Set the controller mode */ diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index 4d529ca..77853a8 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -200,13 +200,13 @@ static void i3100_pirq_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; - if(config->pirq_a_d) + if (config->pirq_a_d) pci_write_config32(dev, 0x60, config->pirq_a_d); - if(config->pirq_e_h) + if (config->pirq_e_h) pci_write_config32(dev, 0x68, config->pirq_e_h); - for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { u8 int_pin=0, int_line=0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 326a9e5..f4ab2f6 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c index fc41645..e018320 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.c +++ b/src/southbridge/intel/i82801ex/i82801ex.c @@ -12,10 +12,10 @@ void i82801ex_enable(device_t dev) /* See if we are behind the i82801ex pci bridge */ lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0)); - if((dev->path.pci.devfn &0xf8)== 0xf8) { + if ((dev->path.pci.devfn &0xf8)== 0xf8) { index = dev->path.pci.devfn & 7; } - else if((dev->path.pci.devfn &0xf8)== 0xe8) { + else if ((dev->path.pci.devfn &0xf8)== 0xe8) { index = (dev->path.pci.devfn & 7) +8; } if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) { diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 9cb6f39..2fcb83d 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -118,7 +118,7 @@ static void sata_init(struct device *dev) /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ pci_write_config8(dev, 0x09, 0x8f); diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index b128280..e76087c 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st /* IOTRAP(0) SMIC: currently unused */ printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4f30865..5f1a44f 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index d4fbed4..d11d531 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void) } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); - for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); + for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index ffeb8a2..98cd0bc 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -91,7 +91,7 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + } else if (config->sata_ahci) { u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index a7c3319..462670e 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -105,7 +105,7 @@ static int codec_detect(u8 *base) dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId - if(dword==0) { + if (dword==0) { printk(BIOS_DEBUG, "No codec!\n"); return 0; } @@ -184,7 +184,7 @@ static u32 verb_data[] = { static unsigned find_verb(u32 viddid, u32 **verb) { - if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; + if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0; *verb = (u32 *)verb_data; return sizeof(verb_data)/sizeof(u32); } @@ -268,8 +268,8 @@ static void aza_init(struct device *dev) printk(BIOS_DEBUG, "****** Azalia PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0){ + for (i=0;i<0xff;i+=4){ + if ((i%16)==0){ printk(BIOS_DEBUG, "\n%02x: ", i); } printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index f3fa079..6b939e7 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -148,8 +148,8 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n"); printk(BIOS_DEBUG, "****** IDE PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 0a5adf0..ef26745 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -139,7 +139,7 @@ static void lpc_init(device_t dev) } else { byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW } - if( byte != byte_old) { + if ( byte != byte_old) { outb(byte, 0x70); } diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index cd376ab..2144350 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -73,7 +73,7 @@ static void readApcMacAddr(void) outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data printk(BIOS_DEBUG, "MAC addr in APC = "); - for(i = 0x9 ; i <=0xe ; i++) + for (i = 0x9 ; i <=0xe ; i++) { printk(BIOS_DEBUG, "%2.2x",readApcByte(i)); } @@ -98,7 +98,7 @@ static void set_apc(struct device *dev) outl(0x80001048,0xcf8); outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data - for(i = 0 ; i <3; i++) + for (i = 0 ; i <3; i++) { addr=0x9+2*i; writeApcByte(addr,(u8)(MacAddr[i]&0xFF)); @@ -142,11 +142,11 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(10); - for(i=0 ; i <= LoopNum; i++) + for (i=0 ; i <= LoopNum; i++) { ulValue=read32(base + 0x3c); - if(!(ulValue & 0x0080)) //BIT_7 + if (!(ulValue & 0x0080)) //BIT_7 break; mdelay(100); @@ -154,7 +154,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg) mdelay(50); - if(i==LoopNum) data=0x10000; + if (i==LoopNum) data=0x10000; else{ ulValue=read32(base + 0x3c); data = ((ulValue & 0xffff0000) >> 16); @@ -205,13 +205,13 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() // Scan all PHY address(0 ~ 31) to find a valid PHY - for(PhyAddress = 0; PhyAddress < 32; PhyAddress++) + for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) { usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h) // Found a valid PHY - if((usData != 0x0) && (usData != 0xffff)) + if ((usData != 0x0) && (usData != 0xffff)) { bFoundPhy = TRUE; break; @@ -219,7 +219,7 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect() } - if(!bFoundPhy) + if (!bFoundPhy) { printk(BIOS_DEBUG, "PHY not found !!!! \n"); } @@ -260,7 +260,7 @@ static void nic_init(struct device *dev) res = find_resource(dev, 0x10); - if(!res) + if (!res) { printk(BIOS_DEBUG, "NIC Cannot find resource..\n"); return; @@ -268,7 +268,7 @@ static void nic_init(struct device *dev) base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "NIC base address %p\n",base); - if(!(val=phy_detect(base,&PhyAddr))) + if (!(val=phy_detect(base,&PhyAddr))) { printk(BIOS_DEBUG, "PHY detect fail !!!!\n"); return; @@ -276,7 +276,7 @@ static void nic_init(struct device *dev) ulValue=read32(base + 0x38L); // check EEPROM existing - if((ulValue & 0x0002)) + if ((ulValue & 0x0002)) { // read MAC address from EEPROM at first @@ -311,8 +311,8 @@ static void nic_init(struct device *dev) printk(BIOS_DEBUG, "****** NIC PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 197f4d2..eb69ab0 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -150,8 +150,8 @@ for (i=0;i<10;i++){ printk(BIOS_DEBUG, "****** SATA PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index 95f01d1..64398e2 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -75,8 +75,8 @@ static void usb_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index 5bad6b3..8c34723 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -72,7 +72,7 @@ static void usb2_init(struct device *dev) //-------------- enable USB2.0 (SiS7002) ---------------------- i = 0; - while(SiS_SiS7002_init[i][0] != 0) + while (SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); temp8 &= SiS_SiS7002_init[i][1]; @@ -82,7 +82,7 @@ static void usb2_init(struct device *dev) }; res = find_resource(dev, 0x10); - if(!res) + if (!res) return; base = res2mmio(res, 0, 0); @@ -94,8 +94,8 @@ static void usb2_init(struct device *dev) printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); - for(i=0;i<0xff;i+=4){ - if((i%16)==0) + for (i=0;i<0xff;i+=4){ + if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); }

1 0

New patch to review for coreboot: soc/intel/skylake: Add monotonic_timer to verstage
by Furquan Shaikh 21 Aug '16

21 Aug '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16292 -gerrit commit 454aad05705472d40af1cca451e89644b9e11d63 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun Aug 21 20:42:48 2016 -0700 soc/intel/skylake: Add monotonic_timer to verstage Change-Id: I8a22218d36287897bf06571998bcc564ece2e49a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/skylake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index b92eab3..716c3d5 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -28,6 +28,7 @@ bootblock-y += pmutil.c bootblock-y += tsc_freq.c verstage-y += flash_controller.c +verstage-y += monotonic_timer.c verstage-y += pch.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c

1 0

Patch merged into coreboot/master: util/scripts: Support cygwin in ucode conversion tool
by gerrit＠coreboot.org 21 Aug '16

21 Aug '16

the following patch was just integrated into master: commit 1bc2b0bed0f75c81153ace65679e761a4cb1438c Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Jun 25 10:17:07 2016 -0600 util/scripts: Support cygwin in ucode conversion tool Check for the existence of TMPFILE with a .exe extension and if found rename it with no extension. This allows the program to be run and removed properly. Change-Id: I26928f9b8bf82d1c07fa456a88d624f7a8838bd3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/15437 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15437 for details. -gerrit

1 0

Patch set updated for coreboot: pcengines/apu2: Add IVRS table generation
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15165 -gerrit commit 796e7da30582866cb07c9393175c364327fc08ac Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:49:36 2016 -0500 pcengines/apu2: Add IVRS table generation The resultant IVRS tables have been tested and work with PCI passthrough under Xen. Change-Id: I81b5b421098f29163d6ae98527de152c8046b1d9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/pcengines/apu2/acpi_tables.c | 35 +++++++++++++++++++++++++++--- src/mainboard/pcengines/apu2/devicetree.cb | 2 +- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 17995ce..c3e24c9 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,9 +58,37 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) { - /* TODO - * Add IVRS entries - */ + uint8_t *p; + + uint32_t apicid_sb800; + uint32_t apicid_northbridge; + + apicid_sb800 = CONFIG_MAX_CPUS; + apicid_northbridge = CONFIG_MAX_CPUS + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_northbridge; /* IOAPIC ID */ + p[5] = 0x0; /* Device 0 Function 0 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sb800; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; return current; } diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..f402167 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU + device pci 0.2 on end # IOMMU device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge

1 0

Patch set updated for coreboot: nb/amd/pi/00730F01: Add initial native IVRS support
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15164 -gerrit commit 084ecffa1d96375e0e27e9cd8eb699b06c100ef2 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:48:58 2016 -0500 nb/amd/pi/00730F01: Add initial native IVRS support Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/amd/db-ft3b-lc/acpi_tables.c | 9 ++ src/mainboard/amd/olivehillplus/acpi_tables.c | 9 ++ src/mainboard/bap/ode_e21XX/acpi_tables.c | 9 ++ src/mainboard/pcengines/apu2/acpi_tables.c | 9 ++ src/northbridge/amd/pi/00730F01/northbridge.c | 208 ++++++++++++++++++++++++-- 5 files changed, 232 insertions(+), 12 deletions(-) diff --git a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c +++ b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/mainboard/amd/olivehillplus/acpi_tables.c b/src/mainboard/amd/olivehillplus/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/amd/olivehillplus/acpi_tables.c +++ b/src/mainboard/amd/olivehillplus/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/mainboard/bap/ode_e21XX/acpi_tables.c b/src/mainboard/bap/ode_e21XX/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/bap/ode_e21XX/acpi_tables.c +++ b/src/mainboard/bap/ode_e21XX/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index d5ebad4..17995ce 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -54,3 +54,12 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + /* TODO + * Add IVRS entries + */ + + return current; +} diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 9b1c1b1..44b1501 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -478,6 +479,193 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } +static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) +{ + uint8_t *p; + struct device *sibling; + struct bus *link; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if (*root_level != -1) { + if (depth >= *root_level) { + if (dev->enabled) { + if (depth == *root_level) { + if (dev->path.pci.devfn == 0x2) { + /* IOMMU */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else if (dev->path.pci.devfn < (0x2 << 3)) { + /* FCH control device */ + } else if ((dev->path.pci.devfn >= (0x2 << 3)) && (dev->path.pci.devfn < (0x3 << 3))) { + /* FCH PCIe bridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + if (dev->path.pci.devfn == (0x14 << 3)) { + /* SMBUS controller */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x97; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Other southbridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } else { + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { + /* Device behind bridge */ + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Device is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Device is legacy PCI or PCI-X */ + p = (uint8_t *) *current; + p[0] = 0x42; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Reserved */ + p[5] = parent->path.pci.devfn; /* Device */ + p[6] = parent->bus->secondary; /* Bus */ + p[7] = 0x0; /* Reserved */ + *length += 8; + *current += 8; + } + } else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) { + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Bridge is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } + } + } + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = sibling->sibling) + add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); + + free(root_level); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate G-series northbridge device! IVRS table not generated...\n"); + return (unsigned long)ivrs; + } + + ivrs->iv_info = 0x0; + ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ + ivrs->iv_info |= (0x30 << 8); /* Maximum supported physical address size */ + ivrs->iv_info |= (0x2 << 5); /* Guest virtual address width */ + + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + ivrs->ivhd.flags |= 0x10; /* Enable ATS support */ + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = 0xfeb00000; + ivrs->ivhd.iommu_base_high = 0x0; + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x13 << 8); + ivrs->ivhd.efr = 0x0; + + /* Describe HPET */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = 0x0; /* HPET number */ + p[5] = 0x14 << 3; /* HPET device */ + p[6] = nb_dev->bus->secondary; /* HPET bus */ + p[7] = 0x2; /* Variety */ + ivrs->ivhd.length += 8; + current += 8; + + /* Describe PCI devices */ + add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + + /* Describe IOAPICs */ + unsigned long prev_current = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - prev_current); + + return current; +} + static void northbridge_fill_ssdt_generator(device_t device) { msr_t msr; @@ -507,7 +695,7 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_slit_t *slit; acpi_header_t *ssdt; acpi_header_t *alib; - acpi_header_t *ivrs; + acpi_ivrs_t *ivrs; acpi_hest_t *hest; /* HEST */ @@ -517,17 +705,13 @@ static unsigned long agesa_write_acpi_tables(device_t device, acpi_add_table(rsdp, (void *)current); current += ((acpi_header_t *)current)->length; - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } + /* IVRS */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); /* SRAT */ current = ALIGN(current, 8);

1 0

Patch set updated for coreboot: pcengines/apu2: Add IVRS table generation
by Philipp Deppenwiese 21 Aug '16

21 Aug '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15165 -gerrit commit 8d2d6bb364074cb37957b0d4c68e71a9c25378c5 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Mon Jun 13 13:49:36 2016 -0500 pcengines/apu2: Add IVRS table generation The resultant IVRS tables have been tested and work with PCI passthrough under Xen. Change-Id: I81b5b421098f29163d6ae98527de152c8046b1d9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> --- src/mainboard/pcengines/apu2/acpi_tables.c | 35 +++++++++++++++++++++++++++--- src/mainboard/pcengines/apu2/devicetree.cb | 2 +- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/mainboard/pcengines/apu2/acpi_tables.c b/src/mainboard/pcengines/apu2/acpi_tables.c index 17995ce..c3e24c9 100644 --- a/src/mainboard/pcengines/apu2/acpi_tables.c +++ b/src/mainboard/pcengines/apu2/acpi_tables.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -57,9 +58,37 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) { - /* TODO - * Add IVRS entries - */ + uint8_t *p; + + uint32_t apicid_sb800; + uint32_t apicid_northbridge; + + apicid_sb800 = CONFIG_MAX_CPUS; + apicid_northbridge = CONFIG_MAX_CPUS + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_northbridge; /* IOAPIC ID */ + p[5] = 0x0; /* Device 0 Function 0 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sb800; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; return current; } diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..f402167 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/pi/00730F01/root_complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU + device pci 0.2 on end # IOMMU device pci 1.0 off end # Internal Graphics P2P bridge 0x9804 device pci 1.1 off end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2016