coreboot-gerrit August 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15850 -gerrit commit 4b74fc45daf2138fade0c6af4eff7e5862f19ba4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 09:52:38 2016 -0700 drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 ++++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/debug.c | 8 +++- src/drivers/intel/fsp2_0/hand_off_block.c | 15 +++++-- src/drivers/intel/fsp2_0/hob_verify.c | 63 ++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 5 ++- src/drivers/intel/fsp2_0/memory_init.c | 4 +- 8 files changed, 99 insertions(+), 7 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 06f1a7c..4ff6116 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -73,4 +73,11 @@ config FSP_M_XIP help Select this value when FSP-M is execute-in-place. +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 2b1754e..c42c034 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -19,6 +19,7 @@ romstage-y += debug.c romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c @@ -26,6 +27,7 @@ ramstage-y += debug.c ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 52e6765..944edbd 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -44,9 +44,15 @@ void fsp_debug_memory_init(enum fsp_status status, if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); - /* Display the HOBs */ + /* Verify that the HOB list pointer was set */ + if (hob_list_ptr == NULL) + die("ERROR - HOB list pointer was not returned!\n"); + + /* Display and verify the HOBs */ if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) fsp_display_hobs(hob_list_ptr); + if (IS_ENABLED(CONFIG_VERIFY_HOBS)) + fsp_verify_hobs(hob_list_ptr); /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index d3392cd..9693cd2 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -43,7 +43,7 @@ static const char *resource_names[] = { }; /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ -static const uint8_t uuid_owner_bootloader_tolum[16] = { +const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, }; @@ -185,13 +185,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, return NULL; } -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]) { const struct hob_resource *fsp_mem; range_entry_init(re, 0, 0, 0); - fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid); if (!fsp_mem) { return; @@ -200,6 +201,14 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) range_entry_init(re, fsp_mem->addr, fsp_mem->addr + fsp_mem->length, 0); } +struct range_entry fsp_find_reserved_memory(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_fsp); + return re; +} + /* * Utilities for printing HOB information */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c new file mode 100644 index 0000000..ffe8fef --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> + +struct range_entry fsp_find_bootloader_tolum(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_bootloader_tolum); + return re; +} + +void fsp_verify_hobs(const struct hob_header *hob_list_ptr) +{ + struct range_entry fsp_mem; + struct range_entry tolum; + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + tolum = fsp_find_bootloader_tolum(hob_list_ptr); + if ((range_entry_base(&tolum) == 0) + && (range_entry_base(&tolum) == range_entry_end(&tolum))) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + if (range_entry_size(&tolum) < cbmem_overhead_size()) { + printk(BIOS_CRIT, + "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", + range_entry_size(&tolum), cbmem_overhead_size()); + die("ERROR: FSP_BOOTLOADER_TOLUM_HOB too small!\n"); + } + + /* Locate the FSP reserved memory area */ + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); + if ((range_entry_base(&fsp_mem) == 0) + && (range_entry_base(&fsp_mem) == range_entry_end(&fsp_mem))) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + /* Verify the the bootloader tolum is above the FSP reserved area */ + if (range_entry_end(&tolum) <= range_entry_base(&fsp_mem)) + die("ERROR - FSP reserved region after BIOS TOLUM!\n"); + if (range_entry_base(&tolum) < range_entry_end(&fsp_mem)) + die("ERROR - FSP reserved region overlaps BIOS TOLUM!\n"); + + /* Verify that the FSP reserved area immediately follows the BIOS + * reserved area + */ + if (range_entry_base(&tolum) != range_entry_end(&fsp_mem)) + die("ERROR - Space between FSP reserved region and BIOS TOLUM!\n"); + + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + printk(BIOS_CRIT, "0x%p: cbmem_top\n", cbmem_top()); + die("ERROR - Space between cbmem_top and BIOS TOLUM!\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index f777c33..44b84a8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -30,6 +30,7 @@ void fsp_debug_notify(enum fsp_status status); void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); void fsp_display_hobs(const struct hob_header *hob_list_ptr); +void fsp_verify_hobs(const struct hob_header *hob_list_ptr); /* Callbacks for displaying UPD parameters - place in a separate file * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. @@ -52,5 +53,6 @@ void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, const char *fsp_get_hob_type_name(const struct hob_header *hob); const char *fsp_get_guid_name(const uint8_t *guid); void fsp_print_guid_extension_hob(const struct hob_header *hob); +struct range_entry fsp_find_bootloader_tolum(const void *hob_list); #endif /* _FSP2_0_DEBUG_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index bda265a..028e865 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -57,6 +57,7 @@ enum hob_type { HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, }; +extern const uint8_t uuid_owner_bootloader_tolum[16]; extern const struct uuid_name_map uuid_names[]; extern const size_t uuid_names_entries; @@ -73,7 +74,9 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * Hand-off-block utilities which do not depend on CBMEM, but need to be passed * the HOB list explicitly. */ -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]); +struct range_entry fsp_find_reserved_memory(const void *hob_list); const struct hob_resource *fsp_hob_header_to_resource( const struct hob_header *hob); const struct hob_header *fsp_next_hob(const struct hob_header *parent); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4921e88..78e3d81 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -67,7 +67,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, struct range_entry fsp_mem; struct romstage_handoff *handoff; - fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ if (!s3wake) { @@ -188,7 +188,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, enum fsp_status status; fsp_memory_init_fn fsp_raminit; struct FSPM_UPD fspm_upd, *upd; - void *hob_list_ptr; + void *hob_list_ptr = NULL; struct FSPM_ARCH_UPD *arch_upd; post_code(0x34);

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Patch set updated for coreboot: drivers/intel/fsp2_0: FSP driver handles all FSP errors
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15853 -gerrit commit 62a6a5e36dec2fe4ff972774364363032a0f420f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:18:52 2016 -0700 drivers/intel/fsp2_0: FSP driver handles all FSP errors Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 6 +++--- src/drivers/intel/fsp2_0/memory_init.c | 29 ++++++++++++----------------- src/drivers/intel/fsp2_0/notify.c | 11 +++++++---- src/drivers/intel/fsp2_0/silicon_init.c | 27 ++++++++++++--------------- src/soc/intel/apollolake/chip.c | 10 +++------- src/soc/intel/apollolake/romstage.c | 6 +----- 6 files changed, 38 insertions(+), 51 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index bc55c50..1348ead 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -60,9 +60,9 @@ enum fsp_notify_phase { /* Main FSP stages */ -enum fsp_status fsp_memory_init(bool s3wake); -enum fsp_status fsp_silicon_init(void); -enum fsp_status fsp_notify(enum fsp_notify_phase phase); +void fsp_memory_init(bool s3wake); +void fsp_silicon_init(void); +void fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 78e3d81..0677e74 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -61,7 +61,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) */ #define MRC_DEAD_VERSION (0xdeaddead) -static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, +static void do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -85,7 +85,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) - die("Failed to accommodate FSP reserved memory request"); + die("Failed to accommodate FSP reserved memory request!\n"); /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); @@ -101,8 +101,6 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, handoff->s3_resume = s3wake; else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return FSP_SUCCESS; } static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, @@ -182,7 +180,7 @@ static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, return CB_SUCCESS; } -static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, +static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, const struct memranges *memmap) { enum fsp_status status; @@ -196,8 +194,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPM signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPM signature!\n"); } /* Copy the default values from the UPD area */ @@ -211,7 +208,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, hdr->fsp_revision, memmap) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd); @@ -229,13 +226,12 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_debug_memory_init(status, hob_list_ptr); - /* Handle any resets requested by FSPM. */ + /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); - if (status != FSP_SUCCESS) - return status; + die("FspMemoryInit returned an error!\n"); - return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); + do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); } /* Load the binary into the memory specified by the info header. */ @@ -286,7 +282,7 @@ static enum cb_err load_fspm_xip(struct fsp_header *hdr, return CB_SUCCESS; } -enum fsp_status fsp_memory_init(bool s3wake) +void fsp_memory_init(bool s3wake) { struct fsp_header hdr; enum cb_err status; @@ -298,7 +294,7 @@ enum fsp_status fsp_memory_init(bool s3wake) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPM not available!\n"); } cbfs_file_data(&file_data, &file_desc); @@ -315,12 +311,11 @@ enum fsp_status fsp_memory_init(bool s3wake) status = load_fspm_xip(&hdr, &file_data); if (status != CB_SUCCESS) { - printk(BIOS_ERR, "Loading FSPM failed.\n"); - return FSP_NOT_FOUND; + die("Loading FSPM failed!\n"); } /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); - return do_fsp_memory_init(&hdr, s3wake, &memmap); + do_fsp_memory_init(&hdr, s3wake, &memmap); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 139e172..b002cf8 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -17,14 +17,14 @@ #include <string.h> #include <timestamp.h> -enum fsp_status fsp_notify(enum fsp_notify_phase phase) +void fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; fsp_notify_fn fspnotify; struct fsp_notify_params notify_params = { .phase = phase }; - if (!fsps_hdr.silicon_init_entry_offset) - return FSP_NOT_FOUND; + if (!fsps_hdr.notify_phase_entry_offset) + die("Notify_phase_entry_offset is zero!\n"); fspnotify = (void*) (fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); @@ -49,5 +49,8 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) } fsp_debug_notify(ret); - return ret; + /* Handle any errors returned by FspNotify */ + fsp_handle_reset(ret); + if (ret != FSP_SUCCESS) + die("FspNotify returned an error!\n"); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b9fea66..c539db6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -23,7 +23,7 @@ struct fsp_header fsps_hdr; -static enum fsp_status do_silicon_init(struct fsp_header *hdr) +static void do_silicon_init(struct fsp_header *hdr) { struct FSPS_UPD upd, *supd; fsp_silicon_init_fn silicon_init; @@ -32,8 +32,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPS signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPS signature\n"); } memcpy(&upd, supd, sizeof(upd)); @@ -54,13 +53,13 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) fsp_debug_silicon_init(status); - /* Handle any resets requested by FSPS. */ + /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); - - return status; + if (status != FSP_SUCCESS) + die("FspSiliconINit returned an error!\n"); } -enum fsp_status fsp_silicon_init(void) +void fsp_silicon_init(void) { struct fsp_header *hdr = &fsps_hdr; struct cbfsf file_desc; @@ -71,7 +70,7 @@ enum fsp_status fsp_silicon_init(void) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPS not available!\n"); } cbfs_file_data(&rdev, &file_desc); @@ -81,26 +80,24 @@ enum fsp_status fsp_silicon_init(void) dest = cbmem_add(CBMEM_ID_REFCODE, size); if (dest == NULL) { - printk(BIOS_ERR, "Could not add FSPS to CBMEM.\n"); - return FSP_NOT_FOUND; + die("Could not add FSPS to CBMEM!\n"); } if (rdev_readat(&rdev, dest, 0, size) < 0) - return FSP_NOT_FOUND; + die("Failed to read FSPS!\n"); if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { - printk(BIOS_ERR, "Unable to relocate FSPS.\n"); - return FSP_NOT_FOUND; + die("Unable to relocate FSPS!\n"); } /* Create new region device in memory after relocation. */ rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)dest, size); if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("Invalid FSPS header!\n"); /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); - return do_silicon_init(hdr); + do_silicon_init(hdr); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 10b71fb..812f663 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -200,8 +200,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - if (fsp_silicon_init() != FSP_SUCCESS) - die("FSP silicon init failed. Giving up."); + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -411,12 +410,9 @@ static void fsp_notify_dummy(void *arg) { enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - enum fsp_status ret; - if ((ret = fsp_notify(ph)) != FSP_SUCCESS) { - printk(BIOS_CRIT, "FspNotify failed, ret = %x!\n", ret); - fsp_handle_reset(ret); - } + fsp_notify(ph); + /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ if (ph == READY_TO_BOOT) { fsp_notify_dummy((void *)END_OF_FIRMWARE); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da7fcf1..8f17fdd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -114,11 +114,7 @@ asmlinkage void car_stage_entry(void) console_init(); s3wake = fill_power_state(ps) == ACPI_S3; - - if (fsp_memory_init(s3wake) != FSP_SUCCESS) { - die("FSP memory init failed. Giving up."); - } - + fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n");

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Patch set updated for coreboot: drivers/intel/fsp2_0: Handle FspNotify calls
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15855 -gerrit commit 3105e39d1b55e58e9ba3fe997c05ac87ef6291f9 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:59:06 2016 -0700 drivers/intel/fsp2_0: Handle FspNotify calls Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 4 +++- src/drivers/intel/fsp2_0/notify.c | 27 ++++++++++++++++++++++++++- src/soc/intel/apollolake/chip.c | 21 +++------------------ 3 files changed, 32 insertions(+), 20 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 1348ead..a6228f2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -62,12 +62,14 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); -void fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); +/* Callback after processing FSP notify */ +void platform_fsp_notify_status(enum fsp_notify_phase phase); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index b002cf8..9edb7f1 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -11,13 +11,14 @@ */ #include <arch/cpu.h> +#include <bootstate.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> #include <string.h> #include <timestamp.h> -void fsp_notify(enum fsp_notify_phase phase) +static void fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; fsp_notify_fn fspnotify; @@ -53,4 +54,28 @@ void fsp_notify(enum fsp_notify_phase phase) fsp_handle_reset(ret); if (ret != FSP_SUCCESS) die("FspNotify returned an error!\n"); + + /* Allow the platform to run something after FspNotify */ + platform_fsp_notify_status(phase); +} + +static void fsp_notify_dummy(void *arg) +{ + enum fsp_notify_phase phase = (uint32_t)arg; + + fsp_notify(phase); + if (phase == READY_TO_BOOT) + fsp_notify(END_OF_FIRMWARE); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); + +__attribute__((weak)) void platform_fsp_notify_status( + enum fsp_notify_phase phase) +{ } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 812f663..345d7c4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -406,28 +406,13 @@ struct chip_operations soc_intel_apollolake_ops = { .final = &soc_final }; -static void fsp_notify_dummy(void *arg) +void platform_fsp_notify_status(enum fsp_notify_phase phase) { - - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - - fsp_notify(ph); - - /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) { - fsp_notify_dummy((void *)END_OF_FIRMWARE); - /* Hide the P2SB device to align with previous behavior. */ + /* Hide the P2SB device to align with previous behavior. */ + if (phase == END_OF_FIRMWARE) p2sb_hide(); - } } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, - (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, - (void *) READY_TO_BOOT); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, - (void *) READY_TO_BOOT); - /* * spi_init() needs to run unconditionally on every boot (including resume) to * allow write protect to be disabled for eventlog and nvram updates. This needs

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add UPD display support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15847 -gerrit commit 3f24b7e791ba314da98679547466cc7084122b5d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:48:49 2016 -0700 drivers/intel/fsp2_0: Add UPD display support Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/debug.c | 8 +++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 14 +++++ src/drivers/intel/fsp2_0/upd_display.c | 76 ++++++++++++++++++++++++++++ 5 files changed, 107 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7f4bbee..32dbb59 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,13 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_UPD_DATA + bool "Display UPD data" + default n + help + Display the user specified product data prior to memory + initialization. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 9ec5192..cc496ee 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += debug.c romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c @@ -25,6 +26,7 @@ ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-y += notify.c ramstage-y += silicon_init.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 6e28939..fc385b7 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -25,6 +25,10 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); + /* Display the UPD values */ + if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + fspm_display_upd_values(fspm_old_upd, fspm_new_upd); + /* Display the call entry point and paramters */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", @@ -53,6 +57,10 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, const struct FSPS_UPD *fsps_old_upd, const struct FSPS_UPD *fsps_new_upd) { + /* Display the UPD values */ + if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA)) + soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd); + /* Display the call to FSP SiliconInit */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 5cc1642..08c0381 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -27,5 +27,19 @@ void fsp_debug_silicon_init(enum fsp_status status); void fsp_before_debug_notify(fsp_notify_fn notify, const struct fsp_notify_params *notify_params); void fsp_debug_notify(enum fsp_status status); +void fspm_display_upd_values(const struct FSPM_UPD *old, + const struct FSPM_UPD *new); + +/* Callbacks for displaying UPD parameters - place in a separate file + * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + */ +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd); +void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd); + +/* FSP debug utility functions */ +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new); #endif /* _FSP2_0_DEBUG_H_ */ diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c new file mode 100644 index 0000000..05881f2 --- /dev/null +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new) +{ + size *= 2; + if (old == new) { + printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name); + } else { + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old, + size, new, name); + } +} + +static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, + const struct FSPM_ARCH_UPD *new) +{ + /* Display the architectural parameters for MemoryInit */ + printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", + new); + fsp_display_upd_value("Revision", sizeof(old->Revision), + old->Revision, new->Revision); + fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr), + (uint64_t)(uintptr_t)old->NvsBufferPtr, + (uint64_t)(uintptr_t)new->NvsBufferPtr); + fsp_display_upd_value("StackBase", sizeof(old->StackBase), + (uint64_t)(uintptr_t)old->StackBase, + (uint64_t)(uintptr_t)new->StackBase); + fsp_display_upd_value("StackSize", sizeof(old->StackSize), + old->StackSize, new->StackSize); + fsp_display_upd_value("BootLoaderTolumSize", + sizeof(old->BootLoaderTolumSize), + old->BootLoaderTolumSize, new->BootLoaderTolumSize); + fsp_display_upd_value("BootMode", sizeof(old->BootMode), + old->BootMode, new->BootMode); +} + +/* Display the UPD parameters for MemoryInit */ +__attribute__((weak)) void soc_display_fspm_upd_params( + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +void fspm_display_upd_values(const struct FSPM_UPD *old, + const struct FSPM_UPD *new) +{ + /* Display the UPD data */ + fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd); + soc_display_fspm_upd_params(old, new); +} + +/* Display the UPD parameters for SiliconInit */ +__attribute__((weak)) void soc_display_fsps_upd_params( + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +}

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Patch merged into coreboot/master: util/cbfstool: Increase initrd offset to 64M
by gerrit＠coreboot.org 01 Aug '16

01 Aug '16

the following patch was just integrated into master: commit c1dc9d725ec9d91af1df99bb7da16e602996ac1b Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Sun Jul 31 00:23:11 2016 -0500 util/cbfstool: Increase initrd offset to 64M Newer Linux kernels fail to detect the initramfs using the old 16M offset. Increase the offset to the minimum working value, 64M. Tested-on: qemu pc, 64-bit virtual CPU, linux 4.6 x86_64 Change-Id: I8678fc33eec23ca8f5e0d58723e04d434cd9d732 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/15999 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15999 for details. -gerrit

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New patch to review for coreboot: i2c/w83795: Fix chip type message
by Patrick Georgi 01 Aug '16

01 Aug '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16009 -gerrit commit 9bca3bfcca6691d4a03b9fd8ac3c63ce7c8e6733 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Aug 1 15:56:09 2016 +0200 i2c/w83795: Fix chip type message (val & 4) == 1 is always false. Since val & 4 is either zero or non-zero, just drop the second test (for "== 1"). Validated against the data sheet that this is really the right register, bit and value. Change-Id: I627df9a9b4fddfff486689e405f52a3b54135eef Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1241864 --- src/drivers/i2c/w83795/w83795.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/i2c/w83795/w83795.c b/src/drivers/i2c/w83795/w83795.c index 24da12c..02b7c37 100644 --- a/src/drivers/i2c/w83795/w83795.c +++ b/src/drivers/i2c/w83795/w83795.c @@ -160,7 +160,7 @@ static void w83795_init(struct device *dev, w83795_fan_mode_t mode, u8 dts_src) val = w83795_read(dev, W83795_REG_CONFIG); if ((val & W83795_REG_CONFIG_CONFIG48) == 0) printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n"); - else if ((val & W83795_REG_CONFIG_CONFIG48) == 1) + else printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n"); /* Reset */

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Patch set updated for coreboot: spi/tpm: read TPM version in larger chunks
by Vadim Bendebury 01 Aug '16

01 Aug '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16000 -gerrit commit 9aac1d3256a6407c765c2f9983178fcfdce7d4f8 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Jul 31 11:19:20 2016 -0700 spi/tpm: read TPM version in larger chunks The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's read 50 bytes at a time to reduce the SPI register read wrapper overhead, and increase the length limit to 300 bytes to accommodate longer version strings. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4de62d9..a63bc9b 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -359,8 +359,14 @@ int tpm2_init(struct spi_slave *spi_if) /* Let's report device FW version if available. */ if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - uint32_t chunk = 0; - char vstr[sizeof(chunk) + 1]; /* room for 4 chars + zero */ + size_t chunk_size; + /* + * let's read 50 bytes at a time; leave room for the trailing + * zero. + */ + char vstr[51]; + + chunk_size = sizeof(vstr) - 1; printk(BIOS_INFO, "Firmware version: "); @@ -368,21 +374,20 @@ int tpm2_init(struct spi_slave *spi_if) * Does not really matter what's written, this just makes sure * the version is reported from the beginning. */ - tpm2_write_reg(TPM_FW_VER, &chunk, sizeof(chunk)); + tpm2_write_reg(TPM_FW_VER, &chunk_size, sizeof(chunk_size)); - /* Print it out in 4 byte chunks. */ - vstr[sizeof(vstr) - 1] = 0; + /* Print it out in sizeof(vstr) - 1 byte chunks. */ + vstr[chunk_size] = 0; do { - tpm2_read_reg(TPM_FW_VER, vstr, sizeof(chunk)); + tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); printk(BIOS_INFO, "%s", vstr); /* - * While string is not over, and no more than 200 + * While string is not over, and is no longer than 300 * characters. - * This is likely result in one extra printk() - * invocation with an empty string, not a big deal. */ - } while (vstr[0] && (chunk_count++ < (200 / sizeof(chunk)))); + } while (vstr[chunk_size - 1] && + (chunk_count++ < (300 / chunk_size))); printk(BIOS_INFO, "\n"); }

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Patch set updated for coreboot: superio/fintek/f81866d: Add support for UART 3/4
by Fabian Kunkel 01 Aug '16

01 Aug '16

Fabian Kunkel (fabi(a)adv.bruhnspace.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15564 -gerrit commit 8f2ad66f8910b52620d7322b2e5d04d7967c9634 Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com> Date: Thu Jul 7 15:15:18 2016 +0200 superio/fintek/f81866d: Add support for UART 3/4 Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com> --- src/superio/fintek/f81866d/Makefile.inc | 2 +- src/superio/fintek/f81866d/f81866d_uart.c | 67 ++++++++++++++++++++++++++++ src/superio/fintek/f81866d/fintek_internal.h | 1 + src/superio/fintek/f81866d/superio.c | 16 +++++++ 4 files changed, 85 insertions(+), 1 deletion(-) diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc index 8654659..b3fd34f 100644 --- a/src/superio/fintek/f81866d/Makefile.inc +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -16,5 +16,5 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c new file mode 100644 index 0000000..9172213 --- /dev/null +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects + * (Written by Fabian Kunkel <fabi(a)adv.bruhnspace.com> for BAP) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "fintek_internal.h" +#include "f81866d.h" + +#define LDN_REG 0x07 +#define PORT_SELECT_REGISTER 0x27 +#define MULTI_FUNC_SEL3_REG 0x29 +#define IRQ_SHARE_REGISTER 0xF0 +#define FIFO_SEL_MODE 0xF6 + +/* + * f81866d_uart_init enables all necessary registers for UART 3/4 + * Fintek needs to know if pins are used as GPIO or UART pins + * Share interrupt usage needs to be enabled + */ +void f81866d_uart_init(struct device *dev) +{ + struct resource *res = find_resource(dev, PNP_IDX_IO0); + u8 tmp; + + if (!res) { + printk(BIOS_WARNING, "%s: No UART resource found.\n", __func__); + return; + } + + pnp_enter_conf_mode(dev); + + // Set Port Select Register (Bit 0) = 0 + // before accessing Multi Function Select 3 Register + tmp = pnp_read_config(dev, PORT_SELECT_REGISTER); + pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE); + + // Set UART 3 function (Bit 4/5), otherwise pin 36-46 are GPIO + // Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO + tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); + pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xF0); + + // Select UART X in LDN register + pnp_write_config(dev, LDN_REG, dev->path.pnp.device & 0xff); + // Set IRQ trigger mode from active low to high (Bit 3) + tmp = pnp_read_config(dev, FIFO_SEL_MODE); + pnp_write_config(dev, FIFO_SEL_MODE, tmp | 0x8); + // Enable share interrupt (Bit 0) + pnp_write_config(dev, IRQ_SHARE_REGISTER, 0x01); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h index 0405e3e..977a47d 100644 --- a/src/superio/fintek/f81866d/fintek_internal.h +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -23,5 +23,6 @@ #include <device/pnp.h> void f81866d_hwm_init(struct device *dev); +void f81866d_uart_init(struct device *dev); #endif /* SUPERIO_FINTEK_F81866D_INTERNAL_H */ diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index a616290..775e2e8 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -40,6 +40,22 @@ static void f81866d_init(struct device *dev) // Fixing temp sensor read out and init Fan control f81866d_hwm_init(dev); break; + case F81866D_SP1: + // Enable Uart1 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP2: + // Enable Uart2 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP3: + // Enable Uart3 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP4: + // Enable Uart4 and IRQ share register + f81866d_uart_init(dev); + break; } }

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Patch set updated for coreboot: spi/tpm: read TPM version in larger chunks
by Vadim Bendebury 01 Aug '16

01 Aug '16

Vadim Bendebury (vbendeb(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16000 -gerrit commit 7bf8f93d28e87d5011cef5bd4dd6dabd4fb753b0 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun Jul 31 11:19:20 2016 -0700 spi/tpm: read TPM version in larger chunks The TPM version string has become much longer recently, and the TPM_FW_VER register available on VID 1ae0 devices supports reading in arbitrary size quantities. Let's increase the string length limit to 300 bytes read 50 bytes at a time to reduce the SPI register read wrapper overhead. TEST=verified on the Kevin device: localhost ~ # grep cr50 /sys/firmware/log Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:* cr50_v1.1.5005-444ddb7 RW_B: cr50_v1.1.5005-5aac83c cr50_v1.1.5005-444ddb7 private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735 cryptoc:v0.0.4-5319e83 2016-07-31 10:58:05 vbendeb@kvasha Change-Id: Ifaf28c1a9a3990372a9cec108c098edbe50d3243 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/drivers/spi/tpm/tpm.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 4de62d9..a63bc9b 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -359,8 +359,14 @@ int tpm2_init(struct spi_slave *spi_if) /* Let's report device FW version if available. */ if (tpm_info.vendor_id == 0x1ae0) { int chunk_count = 0; - uint32_t chunk = 0; - char vstr[sizeof(chunk) + 1]; /* room for 4 chars + zero */ + size_t chunk_size; + /* + * let's read 50 bytes at a time; leave room for the trailing + * zero. + */ + char vstr[51]; + + chunk_size = sizeof(vstr) - 1; printk(BIOS_INFO, "Firmware version: "); @@ -368,21 +374,20 @@ int tpm2_init(struct spi_slave *spi_if) * Does not really matter what's written, this just makes sure * the version is reported from the beginning. */ - tpm2_write_reg(TPM_FW_VER, &chunk, sizeof(chunk)); + tpm2_write_reg(TPM_FW_VER, &chunk_size, sizeof(chunk_size)); - /* Print it out in 4 byte chunks. */ - vstr[sizeof(vstr) - 1] = 0; + /* Print it out in sizeof(vstr) - 1 byte chunks. */ + vstr[chunk_size] = 0; do { - tpm2_read_reg(TPM_FW_VER, vstr, sizeof(chunk)); + tpm2_read_reg(TPM_FW_VER, vstr, chunk_size); printk(BIOS_INFO, "%s", vstr); /* - * While string is not over, and no more than 200 + * While string is not over, and is no longer than 300 * characters. - * This is likely result in one extra printk() - * invocation with an empty string, not a big deal. */ - } while (vstr[0] && (chunk_count++ < (200 / sizeof(chunk)))); + } while (vstr[chunk_size - 1] && + (chunk_count++ < (300 / chunk_size))); printk(BIOS_INFO, "\n"); }

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New patch to review for coreboot: amd/amdfam10: eliminate dead code
by Patrick Georgi 01 Aug '16

01 Aug '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16008 -gerrit commit c5ff2ddf62a6fb277f5bc9823caacc9e5002162a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Aug 1 13:30:02 2016 +0200 amd/amdfam10: eliminate dead code if (gart) { foo = gart?a:b; } never evaluates to foo=b. Change-Id: Ibc7376687374065585b125a670dea5fe46bda97a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1347365 --- src/northbridge/amd/amdfam10/misc_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 775af66..7cd9bff 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -67,7 +67,7 @@ static void mcf3_read_resources(device_t dev) if (gart) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = gart?CONFIG_AGP_APERTURE_SIZE:1; + resource->size = CONFIG_AGP_APERTURE_SIZE; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */

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coreboot-gerrit August 2016