coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/quark: Initialize MTRRs in bootblock
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15861 -gerrit commit 51c811ef51af59bf53d3316fea826fb2afc28a5d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:11:05 2016 -0700 soc/intel/quark: Initialize MTRRs in bootblock Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs. TEST=Build and run on Galileo Gen2. Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/bootblock/bootblock.c | 37 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 1 + src/soc/intel/quark/reg_access.c | 1 - 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 4aa774b..959084d 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> +#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> @@ -47,8 +48,38 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; +static const struct reg_script mtrr_init[] = { + /* Use write-through caching, for FSP 2.0 the cache will be invalidated + * postchar (arch/x86/exit_car.S). + */ + + /* Enable the cache */ + REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)), + + /* Cache the SPI flash */ + REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_TYPE_WRTHROUGH)), + REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_PHYS_MASK_VALID)), + + /* Cache ESRAM */ + REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000 + | MTRR_TYPE_WRTHROUGH)), + REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff) + | MTRR_PHYS_MASK_VALID)), + + /* Enable the variable MTRRs */ + REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN + | MTRR_TYPE_UNCACHEABLE), + + REG_SCRIPT_END +}; + void bootblock_soc_early_init(void) { + /* Initialize the MTRRs */ + reg_script_run(mtrr_init); + /* Initialize the controllers */ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); @@ -60,6 +91,12 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } +void bootblock_soc_init(void) +{ + /* Display the MTRRs */ + soc_display_mtrrs(); +} + void platform_prog_run(struct prog *prog) { /* Display the program entry point */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 62b0ac0..8be7f83 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index fe4de0b..a82383d 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,7 +15,6 @@ #define __SIMPLE_DEVICE__ -#include <cpu/x86/mtrr.h> #include <console/console.h> #include <soc/pci_devs.h> #include <soc/ramstage.h>

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Patch set updated for coreboot: soc/intel/quark: Prepare for FSP2.0 support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15862 -gerrit commit 2273ae10796ba36df227db72eeb9057d4e6cbe0d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 20 08:58:58 2016 -0700 soc/intel/quark: Prepare for FSP2.0 support Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/chip.c | 14 +- src/soc/intel/quark/fsp1_1.c | 35 +++++ src/soc/intel/quark/include/soc/pm.h | 1 + src/soc/intel/quark/include/soc/ramstage.h | 1 + src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/Makefile.inc | 2 + src/soc/intel/quark/romstage/car.c | 67 +++++++++ src/soc/intel/quark/romstage/fsp1_1.c | 199 +++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 2 +- src/soc/intel/quark/romstage/romstage.c | 227 +---------------------------- 11 files changed, 318 insertions(+), 233 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f5b9746..4740ec7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 07eca13..c8c6b39 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -119,10 +119,7 @@ static void chip_init(void *chip_info) die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); + fsp_silicon_init(); } static void pci_domain_set_resources(device_t dev) @@ -152,12 +149,3 @@ struct chip_operations soc_intel_quark_ops = { .init = &chip_init, .enable_dev = chip_enable_dev, }; - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c new file mode 100644 index 0000000..ee10e38 --- /dev/null +++ b/src/soc/intel/quark/fsp1_1.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void fsp_silicon_init(void) +{ + if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) + intel_silicon_init(); + else + fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); +} + +void soc_silicon_init_params(SILICON_INIT_UPD *upd) +{ +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 30d8841..7547a53 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -24,6 +24,7 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *get_power_state(void); struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 80e2f00..9f201a0 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -23,5 +23,6 @@ #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +void fsp_silicon_init(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7e761ab..fcac3e2 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -26,6 +26,8 @@ #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); +void clear_smi_and_wake_events(void); +void disable_rom_shadow(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 16fc5ac..635da83 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,7 +13,9 @@ # GNU General Public License for more details. # +romstage-y += car.c romstage-y += car_stage_entry.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c new file mode 100644 index 0000000..781349c --- /dev/null +++ b/src/soc/intel/quark/romstage/car.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/reg_access.h> + +static const struct reg_script legacy_gpio_init[] = { + /* Temporarily enable the legacy GPIO controller */ + REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID + | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), + REG_SCRIPT_END +}; + +static const struct reg_script i2c_gpio_controller_init[] = { + /* Temporarily enable the GPIO controller */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +void car_soc_pre_console_init(void) +{ + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); +} + +void car_soc_post_console_init(void) +{ + report_platform_info(); +}; diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c new file mode 100644 index 0000000..73910a0 --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbfs.h> +#include "../chip.h" +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +asmlinkage void *car_stage_c_entry(void) +{ + FSP_INFO_HEADER *fih; + struct cache_as_ram_params car_params = {0}; + void *top_of_stack; + + post_code(0x20); + + /* Copy the FSP binary into ESRAM */ + memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, + 0x00040000); + + /* Locate the FSP header in ESRAM */ + fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + + /* Start the early verstage/romstage code */ + post_code(0x2A); + car_params.fih = fih; + top_of_stack = cache_as_ram_main(&car_params); + + /* Initialize MTRRs and switch stacks after RAM initialized */ + return top_of_stack; +} + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +} + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_CRIT, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Update the UPD data for MemoryInit */ + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); +} diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index ce5bd4a..e6bb51f 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *soc_set_mtrrs(void *top_of_stack) { diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4f9b698..9ee4135 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -17,21 +17,14 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <cbfs.h> -#include "../chip.h" -#include <device/pci_def.h> -#include <fsp/car.h> #include <fsp/util.h> #include <lib.h> -#include <soc/intel/common/util.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> -#include <string.h> -static const struct reg_script clear_smi_and_wake_events[] = { +static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), @@ -40,221 +33,20 @@ static const struct reg_script clear_smi_and_wake_events[] = { REG_SCRIPT_END }; -static const struct reg_script legacy_gpio_init[] = { - /* Temporarily enable the legacy GPIO controller */ - REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID - | LEGACY_GPIO_BASE_ADDRESS), - /* Temporarily enable the GPE controller */ - REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID - | GPE0_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), - REG_SCRIPT_END -}; - -static const struct reg_script i2c_gpio_controller_init[] = { - /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -static const struct reg_script hsuart_init[] = { - /* Enable the HSUART */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -asmlinkage void *car_stage_c_entry(void) -{ - post_code(0x20); - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; - } - - return NULL; -} - -void car_soc_pre_console_init(void) -{ - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - - /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) - reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - reg_script_run_on_dev(HSUART1_BDF, hsuart_init); -} - -void car_soc_post_console_init(void) -{ - report_platform_info(); -}; - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - - ps->prev_sleep_state = ACPI_S0; - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void clear_smi_and_wake_events(void) { - const struct device *dev; - const struct soc_intel_quark_config *config; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - char *rmu_file; - size_t rmu_file_len; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Display the ROM shadow data */ - hexdump((void *)0x000ffff0, 0x10); + struct chipset_power_state *ps; /* Clear SMI and wake events */ - if (ps->prev_sleep_state != ACPI_S3) { + ps = get_power_state(); + if (ps->prev_sleep_state != 3) { printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); - reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + reg_script_run_on_dev(LPC_BDF, + clear_smi_and_wake_events_script); } - - /* Locate the RMU data file in flash */ - rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, - &rmu_file_len); - if (!rmu_file) - die("Microcode file (rmu.bin) not found."); - - /* Update the UPD data for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_file; - upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) +void disable_rom_shadow(void) { uint32_t data; @@ -273,7 +65,4 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); - - /* Initialize the PCIe bridges */ - pcie_init(); }

1 0

Patch set updated for coreboot: soc/intel/quark: Add header files for FSP 2.0
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15863 -gerrit commit f8aa95302cab32416e878167d7c751f1c585b865 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:00:50 2016 -0700 soc/intel/quark: Add header files for FSP 2.0 Add the FSP 2.0 header files for Quark. These files were run through the drivers/intel/fsp2_0/header_util to convert the data types so that they are compatible with the coreboot build system. TEST=Build and run on Galileo Gen2. Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/fsp/FspEas.h | 42 +++++ src/soc/intel/quark/include/soc/fsp/FspUpd.h | 44 +++++ src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 223 ++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/fsp/FspsUpd.h | 52 ++++++ src/soc/intel/quark/include/soc/fsp/FsptUpd.h | 89 ++++++++++ 5 files changed, 450 insertions(+) diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h new file mode 100644 index 0000000..48d956e --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspEas.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPEAS_H__ +#define __FSPEAS_H__ + +#include <fsp/upd.h> +#include <soc/fsp/FspmUpd.h> +#include <soc/fsp/FspsUpd.h> +#include <soc/fsp/FsptUpd.h> +#include <fsp/api.h> + +#endif /* _FSPEAS_H_ */ diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/soc/intel/quark/include/soc/fsp/FspUpd.h new file mode 100644 index 0000000..d3277d9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspUpd.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h new file mode 100644 index 0000000..bb0fc51 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h @@ -0,0 +1,223 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - RmuBaseAddress + RMU microcode binary base address in SPI flash' +**/ + uint32_t RmuBaseAddress; + +/** Offset 0x0044 - RmuLength + RMU microcode binary length in bytes +**/ + uint32_t RmuLength; + +/** Offset 0x0048 - SerialPortBaseAddress + Debug serial port base address set by BIOS. Zero disables debug serial output. +**/ + uint32_t SerialPortBaseAddress; + +/** Offset 0x004C - tRAS + ACT to PRE command period in picoseconds. +**/ + uint32_t tRAS; + +/** Offset 0x0050 - tWTR + Delay from start of internal write transaction to internal read command in picoseconds. +**/ + uint32_t tWTR; + +/** Offset 0x0054 - tRRD + ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tRRD; + +/** Offset 0x0058 - tFAW + Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tFAW; + +/** Offset 0x005C - Flags + Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN + BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" + topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices + on writes. +**/ + uint32_t Flags; + +/** Offset 0x0060 - DramWidth + 0=x8, 1=x16, others=RESERVED. +**/ + uint8_t DramWidth; + +/** Offset 0x0061 - DramSpeed + 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. +**/ + uint8_t DramSpeed; + +/** Offset 0x0062 - DramType + 0=DDR3, 1=DDR3L, others=RESERVED. +**/ + uint8_t DramType; + +/** Offset 0x0063 - RankMask + bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. +**/ + uint8_t RankMask; + +/** Offset 0x0064 - ChanMask + bit[0] CHAN0_EN, others=RESERVED. +**/ + uint8_t ChanMask; + +/** Offset 0x0065 - ChanWidth + 1=x16, others=RESERVED. +**/ + uint8_t ChanWidth; + +/** Offset 0x0066 - AddrMode + 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. +**/ + uint8_t AddrMode; + +/** Offset 0x0067 - SrInt + 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. +**/ + uint8_t SrInt; + +/** Offset 0x0068 - SrTemp + 0=normal, 1=extended, others=RESERVED. +**/ + uint8_t SrTemp; + +/** Offset 0x0069 - DramRonVal + 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. +**/ + uint8_t DramRonVal; + +/** Offset 0x006A - DramRttNomVal + 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. +**/ + uint8_t DramRttNomVal; + +/** Offset 0x006B - DramRttWrVal + 0=off others=RESERVED. +**/ + uint8_t DramRttWrVal; + +/** Offset 0x006C - SocRdOdtVal + 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. +**/ + uint8_t SocRdOdtVal; + +/** Offset 0x006D - SocWrRonVal + 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. +**/ + uint8_t SocWrRonVal; + +/** Offset 0x006E - SocWrSlewRate + 0=2.5V/ns, 1=4V/ns, others=RESERVED. +**/ + uint8_t SocWrSlewRate; + +/** Offset 0x006F - DramDensity + 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. +**/ + uint8_t DramDensity; + +/** Offset 0x0070 - tCL + DRAM CAS Latency in clocks +**/ + uint8_t tCL; + +/** Offset 0x0071 - EccScrubInterval + ECC scrub interval in miliseconds 1..255 (0 works as feature disable +**/ + uint8_t EccScrubInterval; + +/** Offset 0x0072 - EccScrubBlkSize + Number of 32B blocks read for ECC scrub 2..16 +**/ + uint8_t EccScrubBlkSize; + +/** Offset 0x0073 - SmmTsegSize + Size of the SMM region in 1 MiB chunks +**/ + uint8_t SmmTsegSize; + +/** Offset 0x0074 - FspReservedMemoryLength + FSP reserved memory length in bytes +**/ + uint32_t FspReservedMemoryLength; + +/** Offset 0x0078 - MrcDataPtr + Pointer to saved MRC data +**/ + uint32_t MrcDataPtr; + +/** Offset 0x007C - MrcDataLength + Length of saved MRC data +**/ + uint32_t MrcDataLength; + +/** Offset 0x0080 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +/** Fsp M UPD Configuration +**/ +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h new file mode 100644 index 0000000..6b054e8 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + + +/** Fsp S UPD Configuration +**/ +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h new file mode 100644 index 0000000..8b1ded7 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + + +/** Fsp T Common UPD +**/ +struct FSPT_COMMON_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + uint32_t MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + uint32_t MicrocodeRegionLength; + +/** Offset 0x002C +**/ + uint32_t CodeRegionBase; + +/** Offset 0x0030 +**/ + uint32_t CodeRegionLength; + +/** Offset 0x0034 +**/ + uint8_t Reserved1[12]; +} __attribute__((packed)); + +/** Fsp T UPD Configuration +**/ +struct FSPT_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif

1 0

Patch set updated for coreboot: arch/x86: Display MTRRs after MTRR update in postcar
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15991 -gerrit commit 8982bdc43542f165877412a7b47acef201483012 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 07:34:20 2016 -0700 arch/x86: Display MTRRs after MTRR update in postcar Display the MTRRs after they have been updated during the postcar stage. TEST=Build and run on Galileo Gen2 Change-Id: I1532250cacd363c1eeaf72edc6cb9e9268a11375 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/exit_car.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index 13c2390..ca9b70e 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -113,6 +113,11 @@ _start: wrmsr #endif /* CONFIG_SOC_SETS_MSRS */ + /* Display the MTRRs */ +#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) + call soc_display_mtrrs +#endif /* CONFIG_POSTCAR_CONSOLE */ + /* Load and run ramstage. */ call copy_and_run /* Should never return. */

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add display HOB support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15851 -gerrit commit cfc7b3fdc4adce1970f2846fb5feafb497642e16 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 27 07:40:25 2016 -0700 drivers/intel/fsp2_0: Add display HOB support Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into debug.h * Move hob_type enum into debug.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 6 + src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/hand_off_block.c | 68 ++++-------- src/drivers/intel/fsp2_0/hob_display.c | 157 +++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 69 ++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 7 +- 6 files changed, 262 insertions(+), 47 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 32dbb59..06f1a7c 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + default n + help + Display the FSP HOBs which are provided for coreboot. + config DISPLAY_UPD_DATA bool "Display UPD data" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 91e86b5..5b8c663 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,12 +16,14 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index ce06a82..d3392cd 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -21,14 +21,6 @@ #define HOB_HEADER_LEN 8 -struct hob_resource { - uint8_t owner_guid[16]; - uint32_t type; - uint32_t attribute_type; - uint64_t addr; - uint64_t length; -} __attribute__((packed)); - enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, EFI_RESOURCE_MEMORY_MAPPED_IO = 1, @@ -50,21 +42,6 @@ static const char *resource_names[] = { [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", }; -enum hob_type { - HOB_TYPE_HANDOFF = 0x0001, - HOB_TYPE_MEMORY_ALLOCATION = 0x0002, - HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, - HOB_TYPE_GUID_EXTENSION = 0x0004, - HOB_TYPE_FV = 0x0005, - HOB_TYPE_CPU = 0x0006, - HOB_TYPE_MEMORY_POOL = 0x0007, - HOB_TYPE_FV2 = 0x0009, - HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, - HOB_TYPE_UCAPSULE = 0x000B, - HOB_TYPE_UNUSED = 0xFFFE, - HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, -}; - /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ static const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, @@ -90,15 +67,13 @@ static const uint8_t empty_uuid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static const struct uuid_name_map { - const void *uuid; - const char *name; -} uuid_names[] = { +const struct uuid_name_map uuid_names[] = { { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, { uuid_owner_tseg, "TSEG" }, { uuid_fsp_nv_storage, "FSP_NV_STORAGE" }, }; +const size_t uuid_names_entries = ARRAY_SIZE(uuid_names); static const char *resource_name(enum resource_type type) { @@ -111,7 +86,7 @@ static const char *resource_name(enum resource_type type) * Utilities for walking HOBs */ -static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) { return !memcmp(uuid1, uuid2, 16); } @@ -123,13 +98,13 @@ static const char *uuid_name(const uint8_t uuid[16]) for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { owner_entry = uuid_names + i; - if (uuid_compare(uuid, owner_entry->uuid)) + if (fsp_uuid_compare(uuid, owner_entry->uuid)) return owner_entry->name; } return "UNKNOWN"; } -static const struct hob_header *next_hob(const struct hob_header *parent) +const struct hob_header *fsp_next_hob(const struct hob_header *parent) { union { const struct hob_header *hob; @@ -167,8 +142,8 @@ static const void *hob_header_to_extension_hob(const struct hob_header *hob) return hob_walker.hob_descr; } -static const -struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +const +struct hob_resource *fsp_hob_header_to_resource(const struct hob_header *hob) { return hob_header_to_struct(hob); } @@ -197,13 +172,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, { const struct hob_resource *res; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) continue; - res = hob_header_to_resource(hob); - if (uuid_compare(res->owner_guid, uuid)) + res = fsp_hob_header_to_resource(hob); + if (fsp_uuid_compare(res->owner_guid, uuid)) return res; } return NULL; @@ -228,7 +204,7 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) * Utilities for printing HOB information */ -static void print_guid(const void *base) +void fsp_print_guid(const void *base) { uint32_t big; uint16_t mid[2]; @@ -243,30 +219,30 @@ static void print_guid(const void *base) id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } -static void print_resource_descriptor(const void *base) +void fsp_print_resource_descriptor(const void *base) { const struct hob_resource *res; - res = hob_header_to_resource(base); + res = fsp_hob_header_to_resource(base); printk(BIOS_DEBUG, "Resource %s, attribute %x\n", resource_name(res->type), res->attribute_type); printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); - if (!uuid_compare(res->owner_guid, empty_uuid)) { + if (!fsp_uuid_compare(res->owner_guid, empty_uuid)) { printk(BIOS_DEBUG, "\tOwner GUID: "); - print_guid(res->owner_guid); + fsp_print_guid(res->owner_guid); printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); } } - void fsp_print_memory_resource_hobs(const void *hob_list) { const struct hob_header *hob = hob_list; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) - print_resource_descriptor(hob); + fsp_print_resource_descriptor(hob); } } @@ -278,13 +254,14 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) if (!hob) return NULL; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) continue; hob_uuid = hob_header_to_struct(hob); - if (uuid_compare(hob_uuid, uuid)) { + if (fsp_uuid_compare(hob_uuid, uuid)) { *size = hob->length - (HOB_HEADER_LEN + 16); return hob_header_to_extension_hob(hob); } @@ -293,7 +270,6 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) return NULL; } - const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size); diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c new file mode 100644 index 0000000..6a49eaa --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +struct hob_type_name { + uint16_t type; + const char *name; +} __attribute__((packed)); + +static const struct hob_type_name hob_type_names [] = { + { HOB_TYPE_HANDOFF, "HOB_TYPE_HANDOFF" }, + { HOB_TYPE_MEMORY_ALLOCATION, "HOB_TYPE_MEMORY_ALLOCATION" }, + { HOB_TYPE_RESOURCE_DESCRIPTOR, "HOB_TYPE_RESOURCE_DESCRIPTOR" }, + { HOB_TYPE_GUID_EXTENSION, "HOB_TYPE_GUID_EXTENSION" }, + { HOB_TYPE_FV, "HOB_TYPE_FV" }, + { HOB_TYPE_CPU, "HOB_TYPE_CPU" }, + { HOB_TYPE_MEMORY_POOL, "HOB_TYPE_MEMORY_POOL" }, + { HOB_TYPE_FV2, "HOB_TYPE_FV2" }, + { HOB_TYPE_LOAD_PEIM_UNUSED, "HOB_TYPE_LOAD_PEIM_UNUSED" }, + { HOB_TYPE_UCAPSULE, "HOB_TYPE_UCAPSULE" }, + { HOB_TYPE_UNUSED, "HOB_TYPE_UNUSED" }, + { HOB_TYPE_END_OF_HOB_LIST, "HOB_TYPE_END_OF_HOB_LIST" } +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +static const uint8_t uuid_smbios_memory_info[16] = { + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 +}; + +static const uint8_t uuid_bootloader_temp_memory[16] = { + 0x6c, 0xf4, 0xcf, 0xbb, 0xd3, 0xc8, 0x13, 0x41, + 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e +}; + +static const uint8_t uuid_fsp_info_header[16] = { + 0xbe, 0x40, 0x27, 0x91, 0x84, 0x22, 0x34, 0x47, + 0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c +}; + +static const struct uuid_name_map guid_names[] = { + { uuid_graphics_info, "GRAPHICS INFO" }, + { uuid_smbios_memory_info, "FSP_SMBIOS_MEMORY_INFO_GUID" }, + { uuid_bootloader_temp_memory, "FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID" }, + { uuid_fsp_info_header, "FSP_INFO_HEADER_GUID" }, +}; + +const char *fsp_get_hob_type_name(const struct hob_header *hob) +{ + size_t index; + const char *name; + + for (index = 0; index < ARRAY_SIZE(hob_type_names); index++) + if (hob->type == hob_type_names[index].type) + return hob_type_names[index].name; + + /* Get name for SOC specific hob */ + name = soc_get_hob_type_name(hob); + if (name != NULL) + return name; + return "Unknown HOB type"; +} + +const char *fsp_get_guid_name(const uint8_t *guid) +{ + size_t index; + const char *name; + + /* Compare the GUID values in hand_off_block.c */ + for (index = 0; index < uuid_names_entries; index++) + if (fsp_uuid_compare(guid, uuid_names[index].uuid)) + return uuid_names[index].name; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_uuid_compare(guid, guid_names[index].uuid)) + return guid_names[index].name; + + /* Get GUID name from SOC */ + name = soc_get_guid_name(guid); + if (name != NULL) + return name; + return "Unknown GUID"; +} + +__attribute__((weak)) const char *soc_get_hob_type_name( + const struct hob_header *hob) +{ + return NULL; +} + +void fsp_print_guid_extension_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + printk(BIOS_SPEW, "\t"); + fsp_print_guid(res->owner_guid); + printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); +} + +__attribute__((weak)) const char *soc_get_guid_name(const uint8_t *guid) +{ + return NULL; +} + +void fsp_display_hobs(const struct hob_header *hob_list_ptr) +{ + const struct hob_header *hob = hob_list_ptr; + + /* Display the HOB list pointer */ + printk(BIOS_SPEW, "\n=== FSP HOBs ===\n"); + printk(BIOS_SPEW, "0x%p: hob_list_ptr\n", hob); + + /* Walk the list of HOBs */ + while (1) { + /* Display the HOB header */ + printk(BIOS_DEBUG, "0x%p, 0x%08x bytes: %s\n", hob, hob->length, + fsp_get_hob_type_name(hob)); + switch(hob->type) { + default: + soc_display_hob(hob); + break; + + case HOB_TYPE_END_OF_HOB_LIST: + printk(BIOS_DEBUG, "=== End of FSP HOBs ===\n\n"); + return; + + case HOB_TYPE_RESOURCE_DESCRIPTOR: + fsp_print_resource_descriptor(hob); + break; + + case HOB_TYPE_GUID_EXTENSION: + fsp_print_guid_extension_hob(hob); + break; + } + hob = fsp_next_hob(hob); + } +} + +__attribute__((weak)) void soc_display_hob(const struct hob_header *hob) +{ +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 7c48886..8935ce1 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -28,6 +28,66 @@ struct hob_header { uint16_t length; } __attribute__((packed)); +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +struct uuid_name_map { + const void *uuid; + const char *name; +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +extern const struct uuid_name_map uuid_names[]; +extern const size_t uuid_names_entries; + +/* + * Hand-off-block handling functions that depend on CBMEM, and thus can only + * be used after cbmem_initialize(). + */ +const void *fsp_get_hob_list(void); + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) +/* Display HOBs API */ +void fsp_display_hobs(const struct hob_header *hob_list_ptr); + +/* Callbacks for displaying HOBs - place in a separate file that is + * conditionally build with CONFIG_DISPLAY_HOBS. + */ +const char *soc_get_hob_type_name(const struct hob_header *hob); +const char *soc_get_guid_name(const uint8_t *guid); +void soc_display_hob(const struct hob_header *hob); + +/* Display HOBs utility functions */ +const char *fsp_get_hob_type_name(const struct hob_header *hob); +const char *fsp_get_guid_name(const uint8_t *guid); +void fsp_print_guid_extension_hob(const struct hob_header *hob); +#else /* CONFIG_DISPLAY_HOBS */ +/* Remove HOB display code from the image */ +static inline __attribute__((always_inline)) void fsp_display_hobs( + const struct hob_header *hob_list_ptr) +{ +} +#endif /* CONFIG_DISPLAY_HOBS */ + /*----------- * MTRRs *----------- @@ -113,6 +173,9 @@ static inline __attribute__((always_inline)) void fsp_debug_memory_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs(hob_list_ptr); + /* Display the MTRRs */ fsp_display_mtrrs(); } @@ -144,6 +207,9 @@ static inline __attribute__((always_inline)) void fsp_debug_silicon_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ fsp_display_mtrrs(); } @@ -177,6 +243,9 @@ static inline __attribute__((always_inline)) void fsp_debug_notify( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); + /* Display the HOBs */ + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ fsp_display_mtrrs(); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index cc70cc1..c84a017 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -25,7 +25,6 @@ * be used after cbmem_initialize(). */ void fsp_save_hob_list(void *hob_list_ptr); -const void *fsp_get_hob_list(void); const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); @@ -34,7 +33,13 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * the HOB list explicitly. */ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +const struct hob_resource *fsp_hob_header_to_resource( + const struct hob_header *hob); +const struct hob_header *fsp_next_hob(const struct hob_header *parent); +void fsp_print_guid(const void *guid); void fsp_print_memory_resource_hobs(const void *hob_list); +void fsp_print_resource_descriptor(const void *base); +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr,

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15850 -gerrit commit bcdd1595bacf34ad9ed4f2c5ff617b7c7e3966cf Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 09:52:38 2016 -0700 drivers/intel/fsp2_0: Verify HOBs returned by FspMemoryInit Verify that FSP is properly returning: * HOB list pointer * FSP_BOOTLOADER_TOLUM_HOB * FSP_RESERVED_MEMORY_RESOURCE_HOB TEST=Build and run on Galileo Gen2 Change-Id: I23005d10f7f3ccf06a2e29dab5fa11c7ed79f187 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 ++++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/hand_off_block.c | 15 +++++-- src/drivers/intel/fsp2_0/hob_verify.c | 63 ++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 30 ++++++++++++- src/drivers/intel/fsp2_0/include/fsp/util.h | 3 +- src/drivers/intel/fsp2_0/memory_init.c | 4 +- 7 files changed, 116 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 06f1a7c..4ff6116 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -73,4 +73,11 @@ config FSP_M_XIP help Select this value when FSP-M is execute-in-place. +config VERIFY_HOBS + bool "Verify the FSP hand-off-blocks" + default n + help + Verify that the HOBs required by coreboot are returned by FSP and + that the resource HOBs are in the correct order and position. + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 5b8c663..9982dcb 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -18,12 +18,14 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c +romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c +ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index d3392cd..9693cd2 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -43,7 +43,7 @@ static const char *resource_names[] = { }; /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ -static const uint8_t uuid_owner_bootloader_tolum[16] = { +const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, }; @@ -185,13 +185,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, return NULL; } -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]) { const struct hob_resource *fsp_mem; range_entry_init(re, 0, 0, 0); - fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid); if (!fsp_mem) { return; @@ -200,6 +201,14 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) range_entry_init(re, fsp_mem->addr, fsp_mem->addr + fsp_mem->length, 0); } +struct range_entry fsp_find_reserved_memory(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_fsp); + return re; +} + /* * Utilities for printing HOB information */ diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c new file mode 100644 index 0000000..ffe8fef --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> + +struct range_entry fsp_find_bootloader_tolum(const void *hob_list) +{ + struct range_entry re; + + fsp_find_range_hob(&re, hob_list, uuid_owner_bootloader_tolum); + return re; +} + +void fsp_verify_hobs(const struct hob_header *hob_list_ptr) +{ + struct range_entry fsp_mem; + struct range_entry tolum; + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + tolum = fsp_find_bootloader_tolum(hob_list_ptr); + if ((range_entry_base(&tolum) == 0) + && (range_entry_base(&tolum) == range_entry_end(&tolum))) + die("9.3: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + if (range_entry_size(&tolum) < cbmem_overhead_size()) { + printk(BIOS_CRIT, + "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n", + range_entry_size(&tolum), cbmem_overhead_size()); + die("ERROR: FSP_BOOTLOADER_TOLUM_HOB too small!\n"); + } + + /* Locate the FSP reserved memory area */ + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); + if ((range_entry_base(&fsp_mem) == 0) + && (range_entry_base(&fsp_mem) == range_entry_end(&fsp_mem))) + die("9.1: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + + /* Verify the the bootloader tolum is above the FSP reserved area */ + if (range_entry_end(&tolum) <= range_entry_base(&fsp_mem)) + die("ERROR - FSP reserved region after BIOS TOLUM!\n"); + if (range_entry_base(&tolum) < range_entry_end(&fsp_mem)) + die("ERROR - FSP reserved region overlaps BIOS TOLUM!\n"); + + /* Verify that the FSP reserved area immediately follows the BIOS + * reserved area + */ + if (range_entry_base(&tolum) != range_entry_end(&fsp_mem)) + die("ERROR - Space between FSP reserved region and BIOS TOLUM!\n"); + + if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { + printk(BIOS_CRIT, "0x%p: cbmem_top\n", cbmem_top()); + die("ERROR - Space between cbmem_top and BIOS TOLUM!\n"); + } +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 8935ce1..26d13ae 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -56,6 +56,7 @@ enum hob_type { HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, }; +extern const uint8_t uuid_owner_bootloader_tolum[16]; extern const struct uuid_name_map uuid_names[]; extern const size_t uuid_names_entries; @@ -65,6 +66,13 @@ extern const size_t uuid_names_entries; */ const void *fsp_get_hob_list(void); +/* + * Hand-off-block utilities which do not depend on CBMEM, but need to be passed + * the HOB list explicitly. + */ +void fsp_find_range_hob(struct range_entry *re, const void *hob_list, + const uint8_t uuid[16]); + #if IS_ENABLED(CONFIG_DISPLAY_HOBS) /* Display HOBs API */ void fsp_display_hobs(const struct hob_header *hob_list_ptr); @@ -104,6 +112,21 @@ static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) } #endif /* CONFIG_DISPLAY_MTRRS */ +#if IS_ENABLED(CONFIG_VERIFY_HOBS) +/* Verify HOBs API */ +void fsp_verify_hobs(const struct hob_header *hob_list_ptr); + +/* Verify HOBs utility functions */ +struct range_entry fsp_find_bootloader_tolum(const void *hob_list); + +#else /* CONFIG_VERIFY_HOBS */ +/* Remove HOB display code from the image */ +static inline __attribute__((always_inline)) void fsp_verify_hobs( + const struct hob_header *hob_list_ptr) +{ +} +#endif /* CONFIG_VERIFY_HOBS */ + /*----------- * UPD *----------- @@ -173,8 +196,13 @@ static inline __attribute__((always_inline)) void fsp_debug_memory_init( if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); - /* Display the HOBs */ + /* Verify that the HOB list pointer was set */ + if (hob_list_ptr == NULL) + die("ERROR - HOB list pointer was not returned!\n"); + + /* Display and verify the HOBs */ fsp_display_hobs(hob_list_ptr); + fsp_verify_hobs(hob_list_ptr); /* Display the MTRRs */ fsp_display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index c84a017..0877387 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -18,7 +18,6 @@ #include <fsp/api.h> #include <fsp/debug.h> #include <fsp/info_header.h> -#include <memrange.h> /* * Hand-off-block handling functions that depend on CBMEM, and thus can only @@ -32,7 +31,7 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * Hand-off-block utilities which do not depend on CBMEM, but need to be passed * the HOB list explicitly. */ -void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +struct range_entry fsp_find_reserved_memory(const void *hob_list); const struct hob_resource *fsp_hob_header_to_resource( const struct hob_header *hob); const struct hob_header *fsp_next_hob(const struct hob_header *parent); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4921e88..78e3d81 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -67,7 +67,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, struct range_entry fsp_mem; struct romstage_handoff *handoff; - fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + fsp_mem = fsp_find_reserved_memory(hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */ if (!s3wake) { @@ -188,7 +188,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, enum fsp_status status; fsp_memory_init_fn fsp_raminit; struct FSPM_UPD fspm_upd, *upd; - void *hob_list_ptr; + void *hob_list_ptr = NULL; struct FSPM_ARCH_UPD *arch_upd; post_code(0x34);

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: FSP driver handles all FSP errors
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15853 -gerrit commit ec714b32db3d82fde2c9dfd279be13626321f81a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:18:52 2016 -0700 drivers/intel/fsp2_0: FSP driver handles all FSP errors Move all FSP error handling into the FSP 2.0 driver. This removes the need to implement error handling within the SOC code. TEST=Build and run on Galileo Gen2 Change-Id: I4d548b4c90d369d3857c24f50f93e7db7e9d3028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 6 +++--- src/drivers/intel/fsp2_0/memory_init.c | 29 ++++++++++++----------------- src/drivers/intel/fsp2_0/notify.c | 11 +++++++---- src/drivers/intel/fsp2_0/silicon_init.c | 27 ++++++++++++--------------- src/soc/intel/apollolake/chip.c | 10 +++------- src/soc/intel/apollolake/romstage.c | 6 +----- 6 files changed, 38 insertions(+), 51 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index bc55c50..1348ead 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -60,9 +60,9 @@ enum fsp_notify_phase { /* Main FSP stages */ -enum fsp_status fsp_memory_init(bool s3wake); -enum fsp_status fsp_silicon_init(void); -enum fsp_status fsp_notify(enum fsp_notify_phase phase); +void fsp_memory_init(bool s3wake); +void fsp_silicon_init(void); +void fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 78e3d81..0677e74 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -61,7 +61,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) */ #define MRC_DEAD_VERSION (0xdeaddead) -static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, +static void do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; @@ -85,7 +85,7 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, /* make sure FSP memory is reserved in cbmem */ if (range_entry_base(&fsp_mem) != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) - die("Failed to accommodate FSP reserved memory request"); + die("Failed to accommodate FSP reserved memory request!\n"); /* Now that CBMEM is up, save the list so ramstage can use it */ fsp_save_hob_list(hob_list_ptr); @@ -101,8 +101,6 @@ static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, handoff->s3_resume = s3wake; else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return FSP_SUCCESS; } static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, @@ -182,7 +180,7 @@ static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, return CB_SUCCESS; } -static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, +static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, const struct memranges *memmap) { enum fsp_status status; @@ -196,8 +194,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPM signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPM signature!\n"); } /* Copy the default values from the UPD area */ @@ -211,7 +208,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, hdr->fsp_revision, memmap) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("FSPM_ARCH_UPD not found!\n"); /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd); @@ -229,13 +226,12 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_debug_memory_init(status, hob_list_ptr); - /* Handle any resets requested by FSPM. */ + /* Handle any errors returned by FspMemoryInit */ fsp_handle_reset(status); - if (status != FSP_SUCCESS) - return status; + die("FspMemoryInit returned an error!\n"); - return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); + do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); } /* Load the binary into the memory specified by the info header. */ @@ -286,7 +282,7 @@ static enum cb_err load_fspm_xip(struct fsp_header *hdr, return CB_SUCCESS; } -enum fsp_status fsp_memory_init(bool s3wake) +void fsp_memory_init(bool s3wake) { struct fsp_header hdr; enum cb_err status; @@ -298,7 +294,7 @@ enum fsp_status fsp_memory_init(bool s3wake) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPM not available!\n"); } cbfs_file_data(&file_data, &file_desc); @@ -315,12 +311,11 @@ enum fsp_status fsp_memory_init(bool s3wake) status = load_fspm_xip(&hdr, &file_data); if (status != CB_SUCCESS) { - printk(BIOS_ERR, "Loading FSPM failed.\n"); - return FSP_NOT_FOUND; + die("Loading FSPM failed!\n"); } /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); - return do_fsp_memory_init(&hdr, s3wake, &memmap); + do_fsp_memory_init(&hdr, s3wake, &memmap); } diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 139e172..b002cf8 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -17,14 +17,14 @@ #include <string.h> #include <timestamp.h> -enum fsp_status fsp_notify(enum fsp_notify_phase phase) +void fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; fsp_notify_fn fspnotify; struct fsp_notify_params notify_params = { .phase = phase }; - if (!fsps_hdr.silicon_init_entry_offset) - return FSP_NOT_FOUND; + if (!fsps_hdr.notify_phase_entry_offset) + die("Notify_phase_entry_offset is zero!\n"); fspnotify = (void*) (fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); @@ -49,5 +49,8 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) } fsp_debug_notify(ret); - return ret; + /* Handle any errors returned by FspNotify */ + fsp_handle_reset(ret); + if (ret != FSP_SUCCESS) + die("FspNotify returned an error!\n"); } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index b9fea66..c539db6 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -23,7 +23,7 @@ struct fsp_header fsps_hdr; -static enum fsp_status do_silicon_init(struct fsp_header *hdr) +static void do_silicon_init(struct fsp_header *hdr) { struct FSPS_UPD upd, *supd; fsp_silicon_init_fn silicon_init; @@ -32,8 +32,7 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base); if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) { - printk(BIOS_ERR, "Invalid FSPS signature\n"); - return FSP_INCOMPATIBLE_VERSION; + die("Invalid FSPS signature\n"); } memcpy(&upd, supd, sizeof(upd)); @@ -54,13 +53,13 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) fsp_debug_silicon_init(status); - /* Handle any resets requested by FSPS. */ + /* Handle any errors returned by FspSiliconInit */ fsp_handle_reset(status); - - return status; + if (status != FSP_SUCCESS) + die("FspSiliconINit returned an error!\n"); } -enum fsp_status fsp_silicon_init(void) +void fsp_silicon_init(void) { struct fsp_header *hdr = &fsps_hdr; struct cbfsf file_desc; @@ -71,7 +70,7 @@ enum fsp_status fsp_silicon_init(void) if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); - return FSP_NOT_FOUND; + die("FSPS not available!\n"); } cbfs_file_data(&rdev, &file_desc); @@ -81,26 +80,24 @@ enum fsp_status fsp_silicon_init(void) dest = cbmem_add(CBMEM_ID_REFCODE, size); if (dest == NULL) { - printk(BIOS_ERR, "Could not add FSPS to CBMEM.\n"); - return FSP_NOT_FOUND; + die("Could not add FSPS to CBMEM!\n"); } if (rdev_readat(&rdev, dest, 0, size) < 0) - return FSP_NOT_FOUND; + die("Failed to read FSPS!\n"); if (fsp_component_relocate((uintptr_t)dest, dest, size) < 0) { - printk(BIOS_ERR, "Unable to relocate FSPS.\n"); - return FSP_NOT_FOUND; + die("Unable to relocate FSPS!\n"); } /* Create new region device in memory after relocation. */ rdev_chain(&rdev, &addrspace_32bit.rdev, (uintptr_t)dest, size); if (fsp_validate_component(hdr, &rdev) != CB_SUCCESS) - return FSP_NOT_FOUND; + die("Invalid FSPS header!\n"); /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr->image_base, hdr->image_size, SEG_FINAL); - return do_silicon_init(hdr); + do_silicon_init(hdr); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 10b71fb..812f663 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -200,8 +200,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - if (fsp_silicon_init() != FSP_SUCCESS) - die("FSP silicon init failed. Giving up."); + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); @@ -411,12 +410,9 @@ static void fsp_notify_dummy(void *arg) { enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - enum fsp_status ret; - if ((ret = fsp_notify(ph)) != FSP_SUCCESS) { - printk(BIOS_CRIT, "FspNotify failed, ret = %x!\n", ret); - fsp_handle_reset(ret); - } + fsp_notify(ph); + /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ if (ph == READY_TO_BOOT) { fsp_notify_dummy((void *)END_OF_FIRMWARE); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da7fcf1..8f17fdd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -114,11 +114,7 @@ asmlinkage void car_stage_entry(void) console_init(); s3wake = fill_power_state(ps) == ACPI_S3; - - if (fsp_memory_init(s3wake) != FSP_SUCCESS) { - die("FSP memory init failed. Giving up."); - } - + fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n");

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Handle FspNotify calls
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15855 -gerrit commit 509c1466eb40a70c649419dd456cb25e50e7a653 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:59:06 2016 -0700 drivers/intel/fsp2_0: Handle FspNotify calls Other SOC platforms need to handle the FspNotify calls in the same way as Apollo Lake. Migrate the FspNotify calls into the FSP 2.0 driver. Provide a platform callback to handle anything else that needs to be done after the FspNotify call. TEST=Build and run on Galileo Gen2 Change-Id: I1ff327d77516d4ea212740c16c2514c2908758a2 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 3 +++ src/drivers/intel/fsp2_0/notify.c | 25 +++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 21 +++------------------ 3 files changed, 31 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 1348ead..5a647a2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -68,6 +68,9 @@ void fsp_notify(enum fsp_notify_phase phase); void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd); void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd); +/* Callback after processing FSP notify */ +void platform_fsp_notify_status(enum fsp_notify_phase phase); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index b002cf8..330c666 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -11,6 +11,7 @@ */ #include <arch/cpu.h> +#include <bootstate.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> @@ -53,4 +54,28 @@ void fsp_notify(enum fsp_notify_phase phase) fsp_handle_reset(ret); if (ret != FSP_SUCCESS) die("FspNotify returned an error!\n"); + + /* Allow the platform to run something after FspNotify */ + platform_fsp_notify_status(phase); +} + +static void fsp_notify_dummy(void *arg) +{ + enum fsp_notify_phase phase = (uint32_t)arg; + + fsp_notify(phase); + if (phase == READY_TO_BOOT) + fsp_notify(END_OF_FIRMWARE); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); + +__attribute__((weak)) void platform_fsp_notify_status( + enum fsp_notify_phase phase) +{ } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 812f663..345d7c4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -406,28 +406,13 @@ struct chip_operations soc_intel_apollolake_ops = { .final = &soc_final }; -static void fsp_notify_dummy(void *arg) +void platform_fsp_notify_status(enum fsp_notify_phase phase) { - - enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; - - fsp_notify(ph); - - /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) { - fsp_notify_dummy((void *)END_OF_FIRMWARE); - /* Hide the P2SB device to align with previous behavior. */ + /* Hide the P2SB device to align with previous behavior. */ + if (phase == END_OF_FIRMWARE) p2sb_hide(); - } } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, - (void *) AFTER_PCI_ENUM); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, - (void *) READY_TO_BOOT); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, - (void *) READY_TO_BOOT); - /* * spi_init() needs to run unconditionally on every boot (including resume) to * allow write protect to be disabled for eventlog and nvram updates. This needs

1 0

Patch set updated for coreboot: soc/intel/quark: Make ramstage relocatable
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15994 -gerrit commit d044861566e6d99d99858d5e892490b6dc1cb434 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 14:14:02 2016 -0700 soc/intel/quark: Make ramstage relocatable Relocate ramstage into CBMEM. TEST=Build and run on Galileo Gen2 Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b9060d5..244cc30 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET select REG_SCRIPT + select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add UPD display support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15847 -gerrit commit a2e9d67d2957b7c74ba8eb8c9b6d94f75eef5a47 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:48:49 2016 -0700 drivers/intel/fsp2_0: Add UPD display support Add UPD display support: * Add a Kconfig value to enable UPD value display * Add a routine to display a UPD value * Add a call before MemoryInit to display the UPD parameters * Add a routine to display the architectural parameters for MemoryInit * Add a weak routine to display the other UPD parameters for MemoryInit * Add a call before SiliconInit to display the UPD parameters * Add a weak routine to display the UPD parameters for SiliconInit TEST=Build and run on Galileo Gen2. Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/debug.h | 41 +++++++++++++++ src/drivers/intel/fsp2_0/upd_display.c | 76 ++++++++++++++++++++++++++++ 4 files changed, 126 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 7f4bbee..32dbb59 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,13 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_UPD_DATA + bool "Display UPD data" + default n + help + Display the user specified product data prior to memory + initialization. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 4f36664..91e86b5 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c @@ -23,6 +24,7 @@ ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-y += notify.c ramstage-y += silicon_init.c +ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 976e0fe..7c48886 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -45,6 +45,41 @@ static inline __attribute__((always_inline)) void fsp_display_mtrrs(void) #endif /* CONFIG_DISPLAY_MTRRS */ /*----------- + * UPD + *----------- + */ +#if IS_ENABLED(CONFIG_DISPLAY_UPD_DATA) + +/* Display UPD API */ +void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); + +/* Callbacks for displaying UPD parameters - place in a separate file + * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. + */ +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd); +void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd); + +/* Display UPD utility functions */ +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new); + +#else /* CONFIG_DISPLAY_UPD_DATA */ +/* Remove UPD display code from the image */ +static inline __attribute__((always_inline)) void fspm_display_upd_values( + const struct FSPM_UPD *old, const struct FSPM_UPD *new) +{ +} + +static inline __attribute__((always_inline)) void soc_display_fsps_upd_params( + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ +} +#endif /* CONFIG_DISPLAY_UPD_DATA */ + +/*----------- * MemoryInit *----------- */ @@ -60,6 +95,9 @@ static inline __attribute__((always_inline)) void fsp_debug_before_memory_init( /* Display the MTRRs */ fsp_display_mtrrs(); + /* Display the UPD values */ + fspm_display_upd_values(fspm_old_upd, fspm_new_upd); + /* Display the call entry point and paramters */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", @@ -90,6 +128,9 @@ static inline __attribute__((always_inline)) void fsp_debug_before_silicon_init( fsp_silicon_init_fn silicon_init, const struct FSPS_UPD *fsps_old_upd, const struct FSPS_UPD *fsps_new_upd) { + /* Display the UPD values */ + soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd); + /* Display the call to FSP SiliconInit */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c new file mode 100644 index 0000000..05881f2 --- /dev/null +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> + +void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new) +{ + size *= 2; + if (old == new) { + printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name); + } else { + printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old, + size, new, name); + } +} + +static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old, + const struct FSPM_ARCH_UPD *new) +{ + /* Display the architectural parameters for MemoryInit */ + printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", + new); + fsp_display_upd_value("Revision", sizeof(old->Revision), + old->Revision, new->Revision); + fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr), + (uint64_t)(uintptr_t)old->NvsBufferPtr, + (uint64_t)(uintptr_t)new->NvsBufferPtr); + fsp_display_upd_value("StackBase", sizeof(old->StackBase), + (uint64_t)(uintptr_t)old->StackBase, + (uint64_t)(uintptr_t)new->StackBase); + fsp_display_upd_value("StackSize", sizeof(old->StackSize), + old->StackSize, new->StackSize); + fsp_display_upd_value("BootLoaderTolumSize", + sizeof(old->BootLoaderTolumSize), + old->BootLoaderTolumSize, new->BootLoaderTolumSize); + fsp_display_upd_value("BootMode", sizeof(old->BootMode), + old->BootMode, new->BootMode); +} + +/* Display the UPD parameters for MemoryInit */ +__attribute__((weak)) void soc_display_fspm_upd_params( + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); + hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); +} + +void fspm_display_upd_values(const struct FSPM_UPD *old, + const struct FSPM_UPD *new) +{ + /* Display the UPD data */ + fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd); + soc_display_fspm_upd_params(old, new); +} + +/* Display the UPD parameters for SiliconInit */ +__attribute__((weak)) void soc_display_fsps_upd_params( + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); + hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); +}

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coreboot-gerrit August 2016