coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: soc/intel/quark: Support access to CPU CR registers
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16004 -gerrit commit d0097cd204b7443a214a6e99d33a44bbff28374e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 18:21:53 2016 -0700 soc/intel/quark: Support access to CPU CR registers Add support to access CR0 and CR4. TEST=Build and run on Galileo Gen2. Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 23 ++++++++++++++++ src/soc/intel/quark/reg_access.c | 39 ++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index a07bd22..62b0ac0 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -19,6 +19,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <delay.h> #include <fsp/util.h> @@ -38,6 +39,7 @@ enum { PCIE_RESET, GPE0_REGS, HOST_BRIDGE, + CPU_CR, }; enum { @@ -49,6 +51,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* CPU CRx register access macros */ +#define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + CPU_CR) +#define REG_CPU_CR_READ(reg_) \ + REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0) +#define REG_CPU_CR_WRITE(reg_, value_) \ + REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_CPU_CR_AND(reg_, value_) \ + REG_CPU_CR_RMW(reg_, value_, 0) +#define REG_CPU_CR_RMW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_CPU_CR_RXW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_CPU_CR_OR(reg_, value_) \ + REG_CPU_CR_RMW(reg_, 0xffffffff, value_) +#define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \ + REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_CPU_CR_XOR(reg_, value_) \ + REG_CPU_CR_RXW(reg_, 0xffffffff, value_) + /* GPE0 controller register access macros */ #define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 7383ddd..fe4de0b 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -144,6 +144,35 @@ void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) mcr_write(QUARK_OPCODE_WRITE, port, offset); } +static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address) +{ + /* Read the CPU CRx register */ + switch(reg_address) { + case 0: + return read_cr0(); + + case 4: + return read_cr4(); + } + die("ERROR - Unsupported CPU register!\n"); + return 0; +} + +static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value) +{ + /* Write the CPU CRx register */ + switch(reg_address) { + default: + die("ERROR - Unsupported CPU register!\n"); + + case 0: + write_cr0(value); + + case 4: + write_cr4(value); + } +} + static uint32_t reg_gpe0_read(uint32_t reg_address) { /* Read the GPE0 register */ @@ -281,6 +310,11 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + value = reg_cpu_cr_read(step->reg); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; value = reg_gpe0_read(step->reg); @@ -336,6 +370,11 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + reg_cpu_cr_write(step->reg, step->value); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; reg_gpe0_write(step->reg, (uint32_t)step->value);

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New patch to review for coreboot: drivers/intel/fsp2_0: Update the debug levels
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16003 -gerrit commit 9e2d40864f6fad1a151f8679416688d135b9231d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 16:49:28 2016 -0700 drivers/intel/fsp2_0: Update the debug levels Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 10 +++++----- src/drivers/intel/fsp2_0/memory_init.c | 6 +++--- src/drivers/intel/fsp2_0/util.c | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 9693cd2..9ecf702 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -223,7 +223,7 @@ void fsp_print_guid(const void *base) mid[0] = read16(id + 4); mid[1] = read16(id + 6); - printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + printk(BIOS_SPEW, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", big, mid[0], mid[1], id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } @@ -234,13 +234,13 @@ void fsp_print_resource_descriptor(const void *base) res = fsp_hob_header_to_resource(base); - printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + printk(BIOS_SPEW, "Resource %s, attribute %x\n", resource_name(res->type), res->attribute_type); - printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + printk(BIOS_SPEW, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); if (!fsp_uuid_compare(res->owner_guid, empty_uuid)) { - printk(BIOS_DEBUG, "\tOwner GUID: "); + printk(BIOS_SPEW, "\tOwner GUID: "); fsp_print_guid(res->owner_guid); - printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + printk(BIOS_SPEW, " (%s)\n", uuid_name(res->owner_guid)); } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0677e74..9041cbf 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -144,7 +144,7 @@ static enum cb_err check_region_overlap(const struct memranges *ranges, continue; if (begin >= range_entry_end(r)) continue; - printk(BIOS_ERR, "'%s' overlaps currently running program: " + printk(BIOS_CRIT, "'%s' overlaps currently running program: " "[%p, %p)\n", description, (void *)begin, (void *)end); return CB_ERR; } @@ -270,7 +270,7 @@ static enum cb_err load_fspm_xip(struct fsp_header *hdr, base = rdev_mmap_full(rdev); if ((uintptr_t)base != hdr->image_base) { - printk(BIOS_ERR, "FSPM XIP base does not match: %p vs %p\n", + printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", (void *)(uintptr_t)hdr->image_base, base); return CB_ERR; } @@ -293,7 +293,7 @@ void fsp_memory_init(bool s3wake) struct range_entry freeranges[2]; if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); die("FSPM not available!\n"); } diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 7f064a5..b31e571 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -68,13 +68,13 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, membase = rdev_mmap(rdev, FSP_HDR_OFFSET, FSP_HDR_LEN); if (membase == NULL) { - printk(BIOS_ERR, "Could not mmap() FSP header.\n"); + printk(BIOS_CRIT, "Could not mmap() FSP header.\n"); return CB_ERR; } if (fsp_identify(hdr, membase) != CB_SUCCESS) { rdev_munmap(rdev, membase); - printk(BIOS_ERR, "No valid FSP header\n"); + printk(BIOS_CRIT, "No valid FSP header\n"); return CB_ERR; } @@ -84,7 +84,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, /* Check if size specified in the header matches the cbfs file size */ if (region_device_sz(rdev) < hdr->image_size) { - printk(BIOS_ERR, "Component size bigger than cbfs file.\n"); + printk(BIOS_CRIT, "Component size bigger than cbfs file.\n"); return CB_ERR; }

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New patch to review for coreboot: drivers/intel/fsp2_0: Disable display of FSP header
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16002 -gerrit commit 0ff809ec2f3ad18b66523811194c0b584bcc4899 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 14:15:49 2016 -0700 drivers/intel/fsp2_0: Disable display of FSP header Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 6 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/header_display.c | 58 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 13 +++++ src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 - src/drivers/intel/fsp2_0/util.c | 43 ---------------- 6 files changed, 79 insertions(+), 45 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4ff6116..1975293 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_FSP_HEADER + bool "Display the FSP header + default n + help + Display the FSP header information when the FSP file is found. + config DISPLAY_HOBS bool "Display the hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 9982dcb..ccef72f 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c @@ -24,6 +25,7 @@ romstage-y += memory_init.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c new file mode 100644 index 0000000..543c075 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + + printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), + hdr->spec_version & 0xf); + printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", + revision.rev.major, + revision.rev.minor, + revision.rev.revision, + revision.rev.bld_num); + printk(BIOS_SPEW, "Type: %s/%s\n", + (hdr->component_attribute & 1 ) ? "release" : "debug", + (hdr->component_attribute & 2 ) ? "test" : "official"); + printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", + hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 26d13ae..1c05936 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -20,6 +20,19 @@ #include <soc/intel/common/util.h> /*----------- + * HEADER + *----------- + */ +#if IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER) +void fsp_print_header_info(const struct fsp_header *hdr); +#else /* CONFIG_DISPLAY_FSP_HEADER */ +static inline __attribute__((always_inline)) void fsp_print_header_info( + const struct fsp_header *hdr) +{ +} +#endif /* CONFIG_DISPLAY_FSP_HEADER */ + +/*----------- * HOBs *----------- */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f5db37d..6351b32 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -42,8 +42,6 @@ struct fsp_header { }; enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -void fsp_print_header_info(const struct fsp_header *hdr); -void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); #if ENV_RAMSTAGE /* diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 108457d..7f064a5 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -59,49 +59,6 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) return CB_SUCCESS; } -void fsp_print_header_info(const struct fsp_header *hdr) -{ - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; - - revision.val = hdr->fsp_revision; - - printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), - hdr->spec_version & 0xf); - printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n", - revision.rev.major, - revision.rev.minor, - revision.rev.revision, - revision.rev.bld_num); - printk(BIOS_DEBUG, "Type: %s/%s\n", - (hdr->component_attribute & 1 ) ? "release" : "debug", - (hdr->component_attribute & 2 ) ? "test" : "official"); - printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); - printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { - printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); - } - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { - printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); - printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); - } - -} - enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev) {

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New patch to review for coreboot: arch/x86: Enable postcar console
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16001 -gerrit commit bfa31649a4008d82594655976f089fbce18ba17f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 11:53:28 2016 -0700 arch/x86: Enable postcar console dd a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/exit_car.S | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index af73a58..ed32461 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -194,6 +194,13 @@ config VERSTAGE_ADDR config POSTCAR_STAGE def_bool n +config POSTCAR_CONSOLE + bool "Enable console output during postcar." + depends on POSTCAR_STAGE + default n + help + Use console during the postcar if supported + config VERSTAGE_DEBUG_SPINLOOP bool default n diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a51d662..13c2390 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -26,6 +26,11 @@ stack_top: .text .global _start _start: +#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) + /* Enable the console */ + call console_init +#endif /* CONFIG_POSTCAR_CONSOLE */ + /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car

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Patch set updated for coreboot: mainboard/intel/galileo: Add FSP 2.0 Kconfig support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15864 -gerrit commit 8de3042c6a1b2ec04f1a1c94c54b36b6b8c5c6e1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:18:13 2016 -0700 mainboard/intel/galileo: Add FSP 2.0 Kconfig support Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index b0c69e4..2acc439 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -49,5 +49,12 @@ config USE_FSP1_1 bool default n select PLATFORM_USES_FSP1_1 +# select ADD_FSP_RAW_BIN + +config USE_FSP2_0 + bool + default n + select PLATFORM_USES_FSP2_0 + select POSTCAR_STAGE endif # BOARD_INTEL_QUARK

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Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 boot block support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15865 -gerrit commit 07cb39a599d55cb60ea9ef8ddef730a3eba1836c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:41:54 2016 -0700 soc/intel/quark: Add FSP 2.0 boot block support Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Bulid and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/Makefile.inc | 3 +++ src/mainboard/intel/galileo/gpio.c | 4 ++++ src/mainboard/intel/galileo/romstage.c | 2 ++ src/soc/intel/quark/Makefile.inc | 10 +++++++++ src/soc/intel/quark/fsp2_0.c | 25 +++++++++++++++++++++ src/soc/intel/quark/include/soc/car.h | 29 ++++++++++++++++++++++++ src/soc/intel/quark/include/soc/ramstage.h | 6 +++++ src/soc/intel/quark/include/soc/romstage.h | 4 ++++ src/soc/intel/quark/memmap.c | 4 +++- src/soc/intel/quark/reset.c | 31 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 3 +++ src/soc/intel/quark/romstage/car_stage_entry.S | 2 ++ src/soc/intel/quark/romstage/fsp2_0.c | 26 +++++++++++++++++++++ 14 files changed, 149 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 2acc439..1b651d5 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -54,6 +54,7 @@ config USE_FSP1_1 config USE_FSP2_0 bool default n + select HAVE_HARD_RESET select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 5aad308..efaf007 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -23,5 +23,8 @@ bootblock-y += reg_access.c romstage-y += gpio.c romstage-y += reg_access.c +postcar-y += gpio.c +postcar-y += reg_access.c + ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 8f3c2e3..f654d19 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,7 +15,11 @@ #include <arch/io.h> #include <console/console.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index dfae772..baf9af3 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> /* All FSP specific code goes in this block */ @@ -22,3 +23,4 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Call back into chipset code with platform values updated. */ romstage_common(rp); } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 4740ec7..52d77bf 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -31,22 +31,32 @@ romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +postcar-y += fsp2_0.c +postcar-y += i2c.c +postcar-y += memmap.c +postcar-y += reg_access.c +postcar-y += tsc_freq.c +postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c new file mode 100644 index 0000000..deb9334 --- /dev/null +++ b/src/soc/intel/quark/fsp2_0.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ +} diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h new file mode 100644 index 0000000..23c6a24 --- /dev/null +++ b/src/soc/intel/quark/include/soc/car.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CAR_H_ +#define _SOC_CAR_H_ + +#include <fsp/util.h> + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); + +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + +#endif /* _SOC_CAR_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 9f201a0..b5e15ae 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,10 +19,16 @@ #include <chip.h> #include <device/device.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/ramstage.h> +#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void fsp_silicon_init(void); +#else +asmlinkage void chipset_teardown_car(void); +#endif #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fcac3e2..d6f9186 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,11 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index f880443..28f8852 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,15 +14,17 @@ */ #include <cbmem.h> +#include <soc/reg_access.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/memmap.h> #include <soc/QuarkNcSocId.h> -#include <soc/reg_access.h> size_t mmap_region_granularity(void) { /* Align to 8 MiB by default */ return 8 << 20; } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ void *cbmem_top(void) { diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c new file mode 100644 index 0000000..e898432 --- /dev/null +++ b/src/soc/intel/quark/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(enum fsp_status status) +{ + switch(status) { + case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ + hard_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 635da83..329138b 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,7 +16,10 @@ romstage-y += car.c romstage-y += car_stage_entry.S romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c + +postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d0a0db0..b820711 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,9 +29,11 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif +#endif /* The code should never reach this point */ movb $0x69, %ah diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c new file mode 100644 index 0000000..494f84a --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + post_code(0x20); + console_init(); + return NULL; +}

1 0

Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 romstage support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15866 -gerrit commit c4003c7ea0f01b64bf383846ea78c5da76be232d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 10:14:07 2016 -0700 soc/intel/quark: Add FSP 2.0 romstage support Add the pieces necessary to successfully build adn run romstage using the FSP 2.0 build. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 23 ++++- src/soc/intel/quark/Makefile.inc | 4 + src/soc/intel/quark/include/soc/pm.h | 6 +- src/soc/intel/quark/romstage/Makefile.inc | 5 +- src/soc/intel/quark/romstage/debug.c | 86 +++++++++++++++++ src/soc/intel/quark/romstage/fsp2_0.c | 152 ++++++++++++++++++++++++++++++ 6 files changed, 272 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 244cc30..c1a35b2 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -127,11 +127,20 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT config DCACHE_RAM_BASE hex + default 0x80000000 if PLATFORM_USES_FSP2_0 default 0x80070000 config DCACHE_RAM_SIZE hex - default 0x00008000 + default 0x40000 if PLATFORM_USES_FSP2_0 + default 0x8000 + +config DISPLAY_ESRAM_LAYOUT + bool "Display ESRAM layout" + default n + depends on PLATFORM_USES_FSP2_0 + help + Select this option to display coreboot's use of ESRAM. ##### # Flash layout @@ -194,8 +203,8 @@ config FSP_LOC config FSP_ESRAM_LOC hex + default 0x80040000 if PLATFORM_USES_FSP2_0 default 0x80000000 - depends on PLATFORM_USES_FSP1_1 help The location in ESRAM where a copy of the FSP binary is placed. @@ -206,6 +215,16 @@ config RELOCATE_FSP_INTO_DRAM help Relocate the FSP binary into DRAM before the call to SiliconInit. +config FSP_M_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_M.fd" + +config FSP_S_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" + ##### # RMU binary # The following options control the Quark chipset microcode file diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 52d77bf..bd297ed 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += memmap.c romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c postcar-y += fsp2_0.c postcar-y += i2c.c @@ -61,6 +62,9 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) + # Add the FSP binary to the CBFS image cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7547a53..55e5e95 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -25,6 +25,10 @@ struct chipset_power_state { } __attribute__ ((packed)); struct chipset_power_state *get_power_state(void); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); - +#else +int fill_power_state(void); #endif + +#endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 329138b..3a33f43 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,8 +15,11 @@ romstage-y += car.c romstage-y += car_stage_entry.S -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c +endif # CONFIG_PLATFORM_USES_FSP2_0 +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c new file mode 100644 index 0000000..6e85a5c --- /dev/null +++ b/src/soc/intel/quark/romstage/debug.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> + +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + const struct FSP_M_CONFIG *new; + const struct FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 494f84a..6d4267b 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,13 +14,165 @@ */ #define __SIMPLE_DEVICE__ +#include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include <cbmem.h> +#include "../chip.h" +#include <cpu/x86/cache.h> #include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void) { + struct postcar_frame pcf; + bool s3wake; + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; + post_code(0x20); console_init(); + + /* Initialize DRAM */ + s3wake = fill_power_state() == ACPI_S3; + fsp_memory_init(s3wake); + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Locate the top of RAM */ + top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); + + /* Cache postcar and ramstage */ + postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache RMU area */ + postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, + 0x10000, MTRR_TYPE_WRTHROUGH); + + /* Cache ESRAM */ + postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + + /* Cache SPI flash - Write protect not supported */ + postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE), + CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH); + + run_postcar_phase(&pcf); return NULL; } + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +int fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps->prev_sleep_state; +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) +{ + struct FSPM_ARCH_UPD *aupd; + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + struct FSP_M_CONFIG *upd; + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + die("ERROR - LPC device not found!"); + } + config = dev->chip_info; + + /* Update the architectural UPD values. */ + aupd = &fspm_upd->FspmArchUpd; + aupd->BootLoaderTolumSize = cbmem_overhead_size(); + aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); + aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + /* Display the ESRAM layout */ + if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { + printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80080000 - ESRAM end\n"); + printk(BIOS_SPEW, "| FSP binary |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", + CONFIG_FSP_ESRAM_LOC); + printk(BIOS_SPEW, "| FSP stack |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + aupd->StackBase); + printk(BIOS_SPEW, "| |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_relocatable_data_end); + printk(BIOS_SPEW, "| coreboot data |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_stack_end); + printk(BIOS_SPEW, "| coreboot stack |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80000000 - ESRAM start\n\n"); + } + + /* Update the UPD data for MemoryInit */ + upd = &fspm_upd->FspmConfig; + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +}

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Patch set updated for coreboot: soc/intel/quark: Fix car_stage_entry routine name.
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15857 -gerrit commit e0e18c6e0794a630638a89dda3610fde6a208acc Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 20 08:41:52 2016 -0700 soc/intel/quark: Fix car_stage_entry routine name. Change routine name from car_state_entry to car_stage_entry. TEST=Build and run on Galileo Gen2 Change-Id: Ifd11db3fa711f2fe52ade1c6cde94f9be1f3a652 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/romstage.h | 2 +- src/soc/intel/quark/romstage/car_stage_entry.S | 2 +- src/soc/intel/quark/romstage/romstage.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7d89c8b..7e761ab 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,7 +25,7 @@ #include <fsp/romstage.h> #include <soc/reg_access.h> -asmlinkage void *car_state_c_entry(void); +asmlinkage void *car_stage_c_entry(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index bf51061..d0a0db0 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -27,7 +27,7 @@ car_stage_entry: /* Enter the C code */ - call car_state_c_entry + call car_stage_c_entry #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 457c922..4f9b698 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -66,7 +66,7 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; -asmlinkage void *car_state_c_entry(void) +asmlinkage void *car_stage_c_entry(void) { post_code(0x20); if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {

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Patch set updated for coreboot: soc/intel/quark: Remove use of EDK-II macros and data types
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15858 -gerrit commit 1c1b027a26ff609086712057f8ce608d0aa3dc91 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:17:10 2016 -0700 soc/intel/quark: Remove use of EDK-II macros and data types Replace the use of ASSERT macro with if/die. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 15 +++++++----- src/soc/intel/quark/chip.h | 52 ++++++++++++++++++++-------------------- src/soc/intel/quark/i2c.c | 20 ++++++++++------ src/soc/intel/quark/memmap.c | 2 +- src/soc/intel/quark/reg_access.c | 12 ++++++---- 5 files changed, 57 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 30ab48a..07eca13 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -101,19 +101,22 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { /* Validate the temperature settings */ - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS - > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255\n"); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS\n"); /* Set the temperature settings */ reg_script_run(thermal_init_script); /* Verify that the thermal configuration is locked */ - ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + if((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) - == (TS_LOCK_THRM_CTRL_REGS_ENABLE - | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + != (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 66105ea..b239631 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -47,70 +47,70 @@ struct soc_intel_quark_config { * the FSP PCD field name. */ - UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */ + uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */ - UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */ - UINT32 tRAS; /* ACT to PRE command period in picoseconds */ + uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ + uint32_t tRAS; /* ACT to PRE command period in picoseconds */ /* Delay from start of internal write transaction to internal read * command in picoseconds */ - UINT32 tWTR; + uint32_t tWTR; /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tRRD; + uint32_t tRRD; /* Four activate window (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tFAW; - UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */ + uint32_t tFAW; + uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */ /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU * support 1066 memory */ - UINT8 DramSpeed; - UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ + uint8_t DramSpeed; + uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ - UINT8 RankMask; - UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ - UINT8 ChanWidth; /* 1=x16, others=RESERVED */ + uint8_t RankMask; + uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ + uint8_t ChanWidth; /* 1=x16, others=RESERVED */ /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ - UINT8 AddrMode; + uint8_t AddrMode; /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ - UINT8 SrInt; - UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */ + uint8_t SrInt; + uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */ /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver * impedance control. */ - UINT8 DramRonVal; - UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ - UINT8 DramRttWrVal; /* 0=off others=RESERVED */ + uint8_t DramRonVal; + uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ + uint8_t DramRttWrVal; /* 0=off others=RESERVED */ /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ - UINT8 SocRdOdtVal; - UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ - UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ + uint8_t SocRdOdtVal; + uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ + uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ - UINT8 DramDensity; - UINT8 tCL; /* DRAM CAS Latency in clocks */ + uint8_t DramDensity; + uint8_t tCL; /* DRAM CAS Latency in clocks */ /* ECC scrub interval in miliseconds 1..255 (0 works as feature * disable) */ - UINT8 EccScrubInterval; + uint8_t EccScrubInterval; /* Number of 32B blocks read for ECC scrub 2..16 */ - UINT8 EccScrubBlkSize; + uint8_t EccScrubBlkSize; - UINT8 SmmTsegSize; /* SMM size in MiB */ + uint8_t SmmTsegSize; /* SMM size in MiB */ }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 118cbea..9e02915 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -63,9 +63,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) i2c_disable(regs); /* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); + if (count == 0) + die("ERROR - count == 0\n"); + if (segments == NULL) + die("ERROR - segments == NULL\n"); + if (segments->read != 0) + die("ERROR - segments->read != \n"); /* Clear the start and stop detection */ status = regs->ic_clr_start_det; @@ -98,9 +101,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) while (count-- > 0) { buffer = segments->buf; length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); + if (buffer == NULL) + die("ERROR - buffer == NULL\n"); + if (length < 1) + die("ERROR - length < 1\n"); + if (segments->chip != chip) + die("ERROR - segments->chip != chip\n"); if (segments->read) { /* Place read commands into the FIFO */ @@ -166,7 +172,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Finish reading the data bytes */ while (read_length > 0) { status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; + *buffer++ = (uint8_t)regs->ic_data_cmd; read_length--; bytes_transferred++; status = regs->ic_status; diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 351fab7..f880443 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -26,7 +26,7 @@ size_t mmap_region_granularity(void) void *cbmem_top(void) { - UINT32 top_of_memory; + uint32_t top_of_memory; /* Determine the TSEG base */ top_of_memory = reg_host_bridge_unit_read(QNC_MSG_FSBIC_REG_HSMMC); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4f14173..7383ddd 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -26,7 +26,8 @@ static uint16_t get_gpe0_address(uint32_t reg_address) /* Get the GPE0 base address */ gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); - ASSERT (gpe0_base_address >= 0x80000000); + if (gpe0_base_address < 0x80000000) + die("ERROR - gpe0_base_address < 0x80000000\n"); gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; /* Return the GPE0 register address */ @@ -40,7 +41,8 @@ static uint32_t *get_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (uint32_t *)(gpio_base_address + reg_address); @@ -53,7 +55,8 @@ void *get_i2c_address(void) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (void *)gpio_base_address; @@ -65,7 +68,8 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); - ASSERT (gpio_base_address >= 0x80000000); + if (gpio_base_address < 0x80000000) + die("ERROR - gpio_base_address < 0x80000000\n"); gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; /* Return the GPIO register address */

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Remove use of EDK-II macros & data types
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15859 -gerrit commit 127175b13e6bcd26f5505e64e6b3c77f70ea7a5a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:28:56 2016 -0700 mainboard/intel/galileo: Remove use of EDK-II macros & data types Replace the use of ASSERT macro with if/die. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/reg_access.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 36345ff..8934e8a 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -45,8 +45,9 @@ static uint64_t reg_read(struct reg_script_context *ctx) case GEN2_I2C_LED_PWM: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - ret_code = i2c_readb(0, step->id, (UINT8)step->reg, &value); - ASSERT(ret_code == 2); + ret_code = i2c_readb(0, step->id, (uint8_t)step->reg, &value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } return value; @@ -76,9 +77,10 @@ static void reg_write(struct reg_script_context *ctx) case RMU_TEMP_REGS: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - value = (UINT8)step->value; - ret_code = i2c_writeb(0, step->id, (UINT8)step->reg, value); - ASSERT(ret_code == 2); + value = (uint8_t)step->value; + ret_code = i2c_writeb(0, step->id, (uint8_t)step->reg, value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } }

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coreboot-gerrit August 2016