coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/intel/galileo: Remove use of EDK-II macros & data types
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15859 -gerrit commit d0a1e48d56baad3f639db17d2e38a6467bc27467 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:28:56 2016 -0700 mainboard/intel/galileo: Remove use of EDK-II macros & data types Replace the use of ASSERT macro with if/die. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/reg_access.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c index 36345ff..8934e8a 100644 --- a/src/mainboard/intel/galileo/reg_access.c +++ b/src/mainboard/intel/galileo/reg_access.c @@ -45,8 +45,9 @@ static uint64_t reg_read(struct reg_script_context *ctx) case GEN2_I2C_LED_PWM: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - ret_code = i2c_readb(0, step->id, (UINT8)step->reg, &value); - ASSERT(ret_code == 2); + ret_code = i2c_readb(0, step->id, (uint8_t)step->reg, &value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } return value; @@ -76,9 +77,10 @@ static void reg_write(struct reg_script_context *ctx) case RMU_TEMP_REGS: if (ctx->display_features) printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id); - value = (UINT8)step->value; - ret_code = i2c_writeb(0, step->id, (UINT8)step->reg, value); - ASSERT(ret_code == 2); + value = (uint8_t)step->value; + ret_code = i2c_writeb(0, step->id, (uint8_t)step->reg, value); + if (ret_code != 2) + die("ERROR - ret_code != 2\n"); break; } }

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Patch set updated for coreboot: drivers/intel/fsp2_0: Disable display of FSP header
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16002 -gerrit commit 2f4179904ff52a47d24c2141c07bef4fbdff3cab Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 14:15:49 2016 -0700 drivers/intel/fsp2_0: Disable display of FSP header Add a Kconfig value to enable display of FSP header. Move the display code into a separate module to remove it entirely from the final image. TEST=Build and run on Galileo Gen2 Change-Id: I7047a9e58e6a6481c8453dbfebfbfe69dc8823d8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 6 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/header_display.c | 58 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 - src/drivers/intel/fsp2_0/util.c | 46 +---------------- 6 files changed, 69 insertions(+), 46 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4ff6116..1975293 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_FSP_HEADER + bool "Display the FSP header + default n + help + Display the FSP header information when the FSP file is found. + config DISPLAY_HOBS bool "Display the hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index c42c034..0a6ae43 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += debug.c romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c @@ -26,6 +27,7 @@ romstage-y += memory_init.c ramstage-y += debug.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c ramstage-y += notify.c diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c new file mode 100644 index 0000000..543c075 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + union { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; + } revision; + + revision.val = hdr->fsp_revision; + + printk(BIOS_SPEW, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), + hdr->spec_version & 0xf); + printk(BIOS_SPEW, "Revision: %u.%u.%u, Build Number %u\n", + revision.rev.major, + revision.rev.minor, + revision.rev.revision, + revision.rev.bld_num); + printk(BIOS_SPEW, "Type: %s/%s\n", + (hdr->component_attribute & 1 ) ? "release" : "debug", + (hdr->component_attribute & 2 ) ? "test" : "official"); + printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n", + hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_SPEW, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_SPEW, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_SPEW, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_SPEW, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 44b84a8..7d732a1 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -31,6 +31,7 @@ void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); void fsp_display_hobs(const struct hob_header *hob_list_ptr); void fsp_verify_hobs(const struct hob_header *hob_list_ptr); +void fsp_print_header_info(const struct fsp_header *hdr); /* Callbacks for displaying UPD parameters - place in a separate file * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f5db37d..6351b32 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -42,8 +42,6 @@ struct fsp_header { }; enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); -void fsp_print_header_info(const struct fsp_header *hdr); -void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); #if ENV_RAMSTAGE /* diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 108457d..bab0601 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -59,49 +59,6 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) return CB_SUCCESS; } -void fsp_print_header_info(const struct fsp_header *hdr) -{ - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; - - revision.val = hdr->fsp_revision; - - printk(BIOS_DEBUG, "Spec version: v%u.%u\n", (hdr->spec_version >> 4 ), - hdr->spec_version & 0xf); - printk(BIOS_DEBUG, "Revision: %u.%u.%u, Build Number %u\n", - revision.rev.major, - revision.rev.minor, - revision.rev.revision, - revision.rev.bld_num); - printk(BIOS_DEBUG, "Type: %s/%s\n", - (hdr->component_attribute & 1 ) ? "release" : "debug", - (hdr->component_attribute & 2 ) ? "test" : "official"); - printk(BIOS_DEBUG, "image ID: %s, base 0x%lx + 0x%zx\n", - hdr->image_id, hdr->image_base, hdr->image_size); - printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", - hdr->cfg_region_offset, hdr->cfg_region_size); - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) { - printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", - hdr->memory_init_entry_offset); - } - - if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) { - printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", - hdr->silicon_init_entry_offset); - printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", - hdr->notify_phase_entry_offset); - } - -} - enum cb_err fsp_validate_component(struct fsp_header *hdr, const struct region_device *rdev) { @@ -123,7 +80,8 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, rdev_munmap(rdev, membase); - fsp_print_header_info(hdr); + if (IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER)) + fsp_print_header_info(hdr); /* Check if size specified in the header matches the cbfs file size */ if (region_device_sz(rdev) < hdr->image_size) {

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Patch set updated for coreboot: soc/intel/quark: Disable FSP serial output
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16005 -gerrit commit 40d66e387127909f75a15ad5ddf67153211e7d9d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 13:40:15 2016 -0700 soc/intel/quark: Disable FSP serial output Add a Kconfig value to enable FSP serial output. By default, this Kconfig value is not selected. Use this Kconfig value to determine if the serial port address is passed to FSP instead of NULL. TEST=Build and run on Galileo Gen2. Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 6 ++++++ src/soc/intel/quark/romstage/fsp1_1.c | 3 ++- src/soc/intel/quark/romstage/fsp2_0.c | 3 ++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index c1a35b2..0a9df97 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -225,6 +225,12 @@ config FSP_S_FILE depends on PLATFORM_USES_FSP2_0 default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" +config FSP_ENABLE_SERIAL_OUTPUT + bool "Should FSP use the debug serial port?" + default n + help + When selected enables FSP to write to the debug serial port. + ##### # RMU binary # The following options control the Quark chipset microcode file diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index 73910a0..483cef9 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -112,7 +112,8 @@ void soc_memory_init_params(struct romstage_params *params, upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = IS_ENABLED(CONFIG_FSP_ENABLE_SERIAL_OUTPUT) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 6d4267b..b2ebd69 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -162,7 +162,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = IS_ENABLED(CONFIG_FSP_ENABLE_SERIAL_OUTPUT) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal;

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Patch set updated for coreboot: soc/intel/quark: Initialize MTRRs in bootblock
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15861 -gerrit commit 806d546f87a230dcd197d81f33e0512deac1b913 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:11:05 2016 -0700 soc/intel/quark: Initialize MTRRs in bootblock Initialize the MTRRs for use by bootblock and romstage. Display the MTRRs. TEST=Build and run on Galileo Gen2. Change-Id: Ib1d422c738820163f54771c65034ae77301237ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/bootblock/bootblock.c | 37 ++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/reg_access.h | 1 + src/soc/intel/quark/reg_access.c | 1 - 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 4aa774b..959084d 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <program_loading.h> #include <soc/iomap.h> +#include <soc/intel/common/util.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> @@ -47,8 +48,38 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; +static const struct reg_script mtrr_init[] = { + /* Use write-through caching, for FSP 2.0 the cache will be invalidated + * postchar (arch/x86/exit_car.S). + */ + + /* Enable the cache */ + REG_CPU_CR_AND(0, ~(CR0_CD | CR0_NW)), + + /* Cache the SPI flash */ + REG_MSR_WRITE(MTRR_PHYS_BASE(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_TYPE_WRTHROUGH)), + REG_MSR_WRITE(MTRR_PHYS_MASK(0), (uint32_t)((-CONFIG_ROM_SIZE) + | MTRR_PHYS_MASK_VALID)), + + /* Cache ESRAM */ + REG_MSR_WRITE(MTRR_PHYS_BASE(1), (uint32_t)(0x80000000 + | MTRR_TYPE_WRTHROUGH)), + REG_MSR_WRITE(MTRR_PHYS_MASK(1), (uint32_t)((~0x7ffff) + | MTRR_PHYS_MASK_VALID)), + + /* Enable the variable MTRRs */ + REG_MSR_WRITE(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_EN + | MTRR_TYPE_UNCACHEABLE), + + REG_SCRIPT_END +}; + void bootblock_soc_early_init(void) { + /* Initialize the MTRRs */ + reg_script_run(mtrr_init); + /* Initialize the controllers */ reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); @@ -60,6 +91,12 @@ void bootblock_soc_early_init(void) reg_script_run_on_dev(HSUART1_BDF, hsuart_init); } +void bootblock_soc_init(void) +{ + /* Display the MTRRs */ + soc_display_mtrrs(); +} + void platform_prog_run(struct prog *prog) { /* Display the program entry point */ diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 62b0ac0..8be7f83 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index fe4de0b..a82383d 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,7 +15,6 @@ #define __SIMPLE_DEVICE__ -#include <cpu/x86/mtrr.h> #include <console/console.h> #include <soc/pci_devs.h> #include <soc/ramstage.h>

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Patch set updated for coreboot: soc/intel/quark: Support access to CPU CR registers
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16004 -gerrit commit 138aa01b2f26d131ec9c6e2f5e7107babf9f7dd4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 18:21:53 2016 -0700 soc/intel/quark: Support access to CPU CR registers Add support to access CR0 and CR4. TEST=Build and run on Galileo Gen2. Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/reg_access.h | 23 ++++++++++++++++ src/soc/intel/quark/reg_access.c | 39 ++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index a07bd22..62b0ac0 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -19,6 +19,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <delay.h> #include <fsp/util.h> @@ -38,6 +39,7 @@ enum { PCIE_RESET, GPE0_REGS, HOST_BRIDGE, + CPU_CR, }; enum { @@ -49,6 +51,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* CPU CRx register access macros */ +#define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + CPU_CR) +#define REG_CPU_CR_READ(reg_) \ + REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0) +#define REG_CPU_CR_WRITE(reg_, value_) \ + REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_CPU_CR_AND(reg_, value_) \ + REG_CPU_CR_RMW(reg_, value_, 0) +#define REG_CPU_CR_RMW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_CPU_CR_RXW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_CPU_CR_OR(reg_, value_) \ + REG_CPU_CR_RMW(reg_, 0xffffffff, value_) +#define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \ + REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_CPU_CR_XOR(reg_, value_) \ + REG_CPU_CR_RXW(reg_, 0xffffffff, value_) + /* GPE0 controller register access macros */ #define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 7383ddd..fe4de0b 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -144,6 +144,35 @@ void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) mcr_write(QUARK_OPCODE_WRITE, port, offset); } +static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address) +{ + /* Read the CPU CRx register */ + switch(reg_address) { + case 0: + return read_cr0(); + + case 4: + return read_cr4(); + } + die("ERROR - Unsupported CPU register!\n"); + return 0; +} + +static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value) +{ + /* Write the CPU CRx register */ + switch(reg_address) { + default: + die("ERROR - Unsupported CPU register!\n"); + + case 0: + write_cr0(value); + + case 4: + write_cr4(value); + } +} + static uint32_t reg_gpe0_read(uint32_t reg_address) { /* Read the GPE0 register */ @@ -281,6 +310,11 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + value = reg_cpu_cr_read(step->reg); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; value = reg_gpe0_read(step->reg); @@ -336,6 +370,11 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + reg_cpu_cr_write(step->reg, step->value); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; reg_gpe0_write(step->reg, (uint32_t)step->value);

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Patch set updated for coreboot: soc/intel/quark: Prepare for FSP2.0 support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15862 -gerrit commit ad2087e85f30fe4b0f1b13d0766a530ef4a4ee87 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 20 08:58:58 2016 -0700 soc/intel/quark: Prepare for FSP2.0 support Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/chip.c | 14 +- src/soc/intel/quark/fsp1_1.c | 35 +++++ src/soc/intel/quark/include/soc/pm.h | 1 + src/soc/intel/quark/include/soc/ramstage.h | 1 + src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/Makefile.inc | 2 + src/soc/intel/quark/romstage/car.c | 67 +++++++++ src/soc/intel/quark/romstage/fsp1_1.c | 199 +++++++++++++++++++++++++ src/soc/intel/quark/romstage/mtrr.c | 2 +- src/soc/intel/quark/romstage/romstage.c | 227 +---------------------------- 11 files changed, 318 insertions(+), 233 deletions(-) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f5b9746..4740ec7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 07eca13..c8c6b39 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -119,10 +119,7 @@ static void chip_init(void *chip_info) die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ - if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) - intel_silicon_init(); - else - fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); + fsp_silicon_init(); } static void pci_domain_set_resources(device_t dev) @@ -152,12 +149,3 @@ struct chip_operations soc_intel_quark_ops = { .init = &chip_init, .enable_dev = chip_enable_dev, }; - -void soc_silicon_init_params(SILICON_INIT_UPD *upd) -{ -} - -void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, - SILICON_INIT_UPD *new) -{ -} diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c new file mode 100644 index 0000000..ee10e38 --- /dev/null +++ b/src/soc/intel/quark/fsp1_1.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void fsp_silicon_init(void) +{ + if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) + intel_silicon_init(); + else + fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0); +} + +void soc_silicon_init_params(SILICON_INIT_UPD *upd) +{ +} + +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new) +{ +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 30d8841..7547a53 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -24,6 +24,7 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *get_power_state(void); struct chipset_power_state *fill_power_state(void); #endif diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 80e2f00..9f201a0 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -23,5 +23,6 @@ #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +void fsp_silicon_init(void); #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 7e761ab..fcac3e2 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -26,6 +26,8 @@ #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); +void clear_smi_and_wake_events(void); +void disable_rom_shadow(void); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); void pcie_init(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 16fc5ac..635da83 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,7 +13,9 @@ # GNU General Public License for more details. # +romstage-y += car.c romstage-y += car_stage_entry.S +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/car.c b/src/soc/intel/quark/romstage/car.c new file mode 100644 index 0000000..781349c --- /dev/null +++ b/src/soc/intel/quark/romstage/car.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/reg_access.h> + +static const struct reg_script legacy_gpio_init[] = { + /* Temporarily enable the legacy GPIO controller */ + REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID + | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), + REG_SCRIPT_END +}; + +static const struct reg_script i2c_gpio_controller_init[] = { + /* Temporarily enable the GPIO controller */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +void car_soc_pre_console_init(void) +{ + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); +} + +void car_soc_post_console_init(void) +{ + report_platform_info(); +}; diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c new file mode 100644 index 0000000..73910a0 --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -0,0 +1,199 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbfs.h> +#include "../chip.h" +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +asmlinkage void *car_stage_c_entry(void) +{ + FSP_INFO_HEADER *fih; + struct cache_as_ram_params car_params = {0}; + void *top_of_stack; + + post_code(0x20); + + /* Copy the FSP binary into ESRAM */ + memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, + 0x00040000); + + /* Locate the FSP header in ESRAM */ + fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + + /* Start the early verstage/romstage code */ + post_code(0x2A); + car_params.fih = fih; + top_of_stack = cache_as_ram_main(&car_params); + + /* Initialize MTRRs and switch stacks after RAM initialized */ + return top_of_stack; +} + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +} + +/* Initialize the UPD parameters for MemoryInit */ +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd) +{ + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + printk(BIOS_CRIT, + "Error! Device (PCI:0:%02x.%01x) not found, " + "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return; + } + config = dev->chip_info; + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Update the UPD data for MemoryInit */ + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +} + +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new) +{ + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); +} diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index ce5bd4a..e6bb51f 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *soc_set_mtrrs(void *top_of_stack) { diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4f9b698..9ee4135 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -17,21 +17,14 @@ #include <arch/early_variables.h> #include <console/console.h> -#include <cbfs.h> -#include "../chip.h" -#include <device/pci_def.h> -#include <fsp/car.h> #include <fsp/util.h> #include <lib.h> -#include <soc/intel/common/util.h> -#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> -#include <string.h> -static const struct reg_script clear_smi_and_wake_events[] = { +static const struct reg_script clear_smi_and_wake_events_script[] = { /* Clear any SMI or wake events */ REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), @@ -40,221 +33,20 @@ static const struct reg_script clear_smi_and_wake_events[] = { REG_SCRIPT_END }; -static const struct reg_script legacy_gpio_init[] = { - /* Temporarily enable the legacy GPIO controller */ - REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID - | LEGACY_GPIO_BASE_ADDRESS), - /* Temporarily enable the GPE controller */ - REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID - | GPE0_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), - REG_SCRIPT_END -}; - -static const struct reg_script i2c_gpio_controller_init[] = { - /* Temporarily enable the GPIO controller */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), - REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -static const struct reg_script hsuart_init[] = { - /* Enable the HSUART */ - REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), - REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), - REG_SCRIPT_END -}; - -asmlinkage void *car_stage_c_entry(void) -{ - post_code(0x20); - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - FSP_INFO_HEADER *fih; - struct cache_as_ram_params car_params = {0}; - void *top_of_stack; - - /* Copy the FSP binary into ESRAM */ - memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, - 0x00040000); - - /* Locate the FSP header in ESRAM */ - fih = find_fsp(CONFIG_FSP_ESRAM_LOC); - - /* Start the early verstage/romstage code */ - post_code(0x2A); - car_params.fih = fih; - top_of_stack = cache_as_ram_main(&car_params); - - /* Initialize MTRRs and switch stacks after RAM initialized */ - return top_of_stack; - } - - return NULL; -} - -void car_soc_pre_console_init(void) -{ - /* Initialize the controllers */ - reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); - reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); - - /* Enable the HSUART */ - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) - reg_script_run_on_dev(HSUART0_BDF, hsuart_init); - if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) - reg_script_run_on_dev(HSUART1_BDF, hsuart_init); -} - -void car_soc_post_console_init(void) -{ - report_platform_info(); -}; - -static struct chipset_power_state power_state CAR_GLOBAL; - -struct chipset_power_state *fill_power_state(void) -{ - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - - ps->prev_sleep_state = ACPI_S0; - printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); - return ps; -} - -/* Initialize the UPD parameters for MemoryInit */ -void soc_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *upd) +void clear_smi_and_wake_events(void) { - const struct device *dev; - const struct soc_intel_quark_config *config; - struct chipset_power_state *ps = car_get_var_ptr(&power_state); - char *rmu_file; - size_t rmu_file_len; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_memory_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Display the ROM shadow data */ - hexdump((void *)0x000ffff0, 0x10); + struct chipset_power_state *ps; /* Clear SMI and wake events */ - if (ps->prev_sleep_state != ACPI_S3) { + ps = get_power_state(); + if (ps->prev_sleep_state != 3) { printk(BIOS_SPEW, "Clearing SMI interrupts and wake events\n"); - reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); + reg_script_run_on_dev(LPC_BDF, + clear_smi_and_wake_events_script); } - - /* Locate the RMU data file in flash */ - rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, - &rmu_file_len); - if (!rmu_file) - die("Microcode file (rmu.bin) not found."); - - /* Update the UPD data for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); - upd->AddrMode = config->AddrMode; - upd->ChanMask = config->ChanMask; - upd->ChanWidth = config->ChanWidth; - upd->DramDensity = config->DramDensity; - upd->DramRonVal = config->DramRonVal; - upd->DramRttNomVal = config->DramRttNomVal; - upd->DramRttWrVal = config->DramRttWrVal; - upd->DramSpeed = config->DramSpeed; - upd->DramType = config->DramType; - upd->DramWidth = config->DramWidth; - upd->EccScrubBlkSize = config->EccScrubBlkSize; - upd->EccScrubInterval = config->EccScrubInterval; - upd->Flags = config->Flags; - upd->FspReservedMemoryLength = config->FspReservedMemoryLength; - upd->RankMask = config->RankMask; - upd->RmuBaseAddress = (uintptr_t)rmu_file; - upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; - upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->SmmTsegSize : 0; - upd->SocRdOdtVal = config->SocRdOdtVal; - upd->SocWrRonVal = config->SocWrRonVal; - upd->SocWrSlewRate = config->SocWrSlewRate; - upd->SrInt = config->SrInt; - upd->SrTemp = config->SrTemp; - upd->tCL = config->tCL; - upd->tFAW = config->tFAW; - upd->tRAS = config->tRAS; - upd->tRRD = config->tRRD; - upd->tWTR = config->tWTR; } -void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, - MEMORY_INIT_UPD *new) -{ - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), - old->AddrMode, new->AddrMode); - fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), - old->ChanMask, new->ChanMask); - fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), - old->ChanWidth, new->ChanWidth); - fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), - old->DramDensity, new->DramDensity); - fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), - old->DramRonVal, new->DramRonVal); - fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), - old->DramRttNomVal, new->DramRttNomVal); - fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), - old->DramRttWrVal, new->DramRttWrVal); - fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), - old->DramSpeed, new->DramSpeed); - fsp_display_upd_value("DramType", sizeof(old->DramType), - old->DramType, new->DramType); - fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), - old->DramWidth, new->DramWidth); - fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), - old->EccScrubBlkSize, new->EccScrubBlkSize); - fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), - old->EccScrubInterval, new->EccScrubInterval); - fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, - new->Flags); - fsp_display_upd_value("FspReservedMemoryLength", - sizeof(old->FspReservedMemoryLength), - old->FspReservedMemoryLength, new->FspReservedMemoryLength); - fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, - new->RankMask); - fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), - old->RmuBaseAddress, new->RmuBaseAddress); - fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), - old->RmuLength, new->RmuLength); - fsp_display_upd_value("SerialPortBaseAddress", - sizeof(old->SerialPortBaseAddress), - old->SerialPortBaseAddress, new->SerialPortBaseAddress); - fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), - old->SmmTsegSize, new->SmmTsegSize); - fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), - old->SocRdOdtVal, new->SocRdOdtVal); - fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), - old->SocWrRonVal, new->SocWrRonVal); - fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), - old->SocWrSlewRate, new->SocWrSlewRate); - fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, - new->SrInt); - fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, - new->SrTemp); - fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); - fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); - fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); - fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); - fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); -} - -void soc_after_ram_init(struct romstage_params *params) +void disable_rom_shadow(void) { uint32_t data; @@ -273,7 +65,4 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); - - /* Initialize the PCIe bridges */ - pcie_init(); }

1 0

Patch set updated for coreboot: soc/intel/quark: Add header files for FSP 2.0
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15863 -gerrit commit 9ad11b9c038330e4f2969323bcc6365658333f80 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:00:50 2016 -0700 soc/intel/quark: Add header files for FSP 2.0 Add the FSP 2.0 header files for Quark. These files were run through the drivers/intel/fsp2_0/header_util to convert the data types so that they are compatible with the coreboot build system. TEST=Build and run on Galileo Gen2. Change-Id: I15548888215cc811fa753d30b65e3a19e3f8ff8d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/fsp/FspEas.h | 42 +++++ src/soc/intel/quark/include/soc/fsp/FspUpd.h | 44 +++++ src/soc/intel/quark/include/soc/fsp/FspmUpd.h | 223 ++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/fsp/FspsUpd.h | 52 ++++++ src/soc/intel/quark/include/soc/fsp/FsptUpd.h | 89 ++++++++++ 5 files changed, 450 insertions(+) diff --git a/src/soc/intel/quark/include/soc/fsp/FspEas.h b/src/soc/intel/quark/include/soc/fsp/FspEas.h new file mode 100644 index 0000000..48d956e --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspEas.h @@ -0,0 +1,42 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPEAS_H__ +#define __FSPEAS_H__ + +#include <fsp/upd.h> +#include <soc/fsp/FspmUpd.h> +#include <soc/fsp/FspsUpd.h> +#include <soc/fsp/FsptUpd.h> +#include <fsp/api.h> + +#endif /* _FSPEAS_H_ */ diff --git a/src/soc/intel/quark/include/soc/fsp/FspUpd.h b/src/soc/intel/quark/include/soc/fsp/FspUpd.h new file mode 100644 index 0000000..d3277d9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspUpd.h @@ -0,0 +1,44 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#define FSPT_UPD_SIGNATURE 0x545F4450554B5251 /* 'QRKUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F4450554B5251 /* 'QRKUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F4450554B5251 /* 'QRKUPD_S' */ + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspmUpd.h b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h new file mode 100644 index 0000000..bb0fc51 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspmUpd.h @@ -0,0 +1,223 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - RmuBaseAddress + RMU microcode binary base address in SPI flash' +**/ + uint32_t RmuBaseAddress; + +/** Offset 0x0044 - RmuLength + RMU microcode binary length in bytes +**/ + uint32_t RmuLength; + +/** Offset 0x0048 - SerialPortBaseAddress + Debug serial port base address set by BIOS. Zero disables debug serial output. +**/ + uint32_t SerialPortBaseAddress; + +/** Offset 0x004C - tRAS + ACT to PRE command period in picoseconds. +**/ + uint32_t tRAS; + +/** Offset 0x0050 - tWTR + Delay from start of internal write transaction to internal read command in picoseconds. +**/ + uint32_t tWTR; + +/** Offset 0x0054 - tRRD + ACT to ACT command period (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tRRD; + +/** Offset 0x0058 - tFAW + Four activate window (JESD79 specific to page size 1K/2K) in picoseconds. +**/ + uint32_t tFAW; + +/** Offset 0x005C - Flags + Bitmap of MRC_FLAG_XXX: ECC_EN BIT0, SCRAMBLE_EN BIT1, MEMTEST_EN + BIT2, TOP_TREE_EN BIT3 0b DDR "fly-by" topology else 1b DDR "tree" + topology, WR_ODT_EN BIT4 If set ODR signal is asserted to DRAM devices + on writes. +**/ + uint32_t Flags; + +/** Offset 0x0060 - DramWidth + 0=x8, 1=x16, others=RESERVED. +**/ + uint8_t DramWidth; + +/** Offset 0x0061 - DramSpeed + 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU support 1066 memory. +**/ + uint8_t DramSpeed; + +/** Offset 0x0062 - DramType + 0=DDR3, 1=DDR3L, others=RESERVED. +**/ + uint8_t DramType; + +/** Offset 0x0063 - RankMask + bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED. +**/ + uint8_t RankMask; + +/** Offset 0x0064 - ChanMask + bit[0] CHAN0_EN, others=RESERVED. +**/ + uint8_t ChanMask; + +/** Offset 0x0065 - ChanWidth + 1=x16, others=RESERVED. +**/ + uint8_t ChanWidth; + +/** Offset 0x0066 - AddrMode + 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED. +**/ + uint8_t AddrMode; + +/** Offset 0x0067 - SrInt + 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE. +**/ + uint8_t SrInt; + +/** Offset 0x0068 - SrTemp + 0=normal, 1=extended, others=RESERVED. +**/ + uint8_t SrTemp; + +/** Offset 0x0069 - DramRonVal + 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver impedance control. +**/ + uint8_t DramRonVal; + +/** Offset 0x006A - DramRttNomVal + 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED. +**/ + uint8_t DramRttNomVal; + +/** Offset 0x006B - DramRttWrVal + 0=off others=RESERVED. +**/ + uint8_t DramRttWrVal; + +/** Offset 0x006C - SocRdOdtVal + 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED. +**/ + uint8_t SocRdOdtVal; + +/** Offset 0x006D - SocWrRonVal + 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED. +**/ + uint8_t SocWrRonVal; + +/** Offset 0x006E - SocWrSlewRate + 0=2.5V/ns, 1=4V/ns, others=RESERVED. +**/ + uint8_t SocWrSlewRate; + +/** Offset 0x006F - DramDensity + 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED. +**/ + uint8_t DramDensity; + +/** Offset 0x0070 - tCL + DRAM CAS Latency in clocks +**/ + uint8_t tCL; + +/** Offset 0x0071 - EccScrubInterval + ECC scrub interval in miliseconds 1..255 (0 works as feature disable +**/ + uint8_t EccScrubInterval; + +/** Offset 0x0072 - EccScrubBlkSize + Number of 32B blocks read for ECC scrub 2..16 +**/ + uint8_t EccScrubBlkSize; + +/** Offset 0x0073 - SmmTsegSize + Size of the SMM region in 1 MiB chunks +**/ + uint8_t SmmTsegSize; + +/** Offset 0x0074 - FspReservedMemoryLength + FSP reserved memory length in bytes +**/ + uint32_t FspReservedMemoryLength; + +/** Offset 0x0078 - MrcDataPtr + Pointer to saved MRC data +**/ + uint32_t MrcDataPtr; + +/** Offset 0x007C - MrcDataLength + Length of saved MRC data +**/ + uint32_t MrcDataLength; + +/** Offset 0x0080 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +/** Fsp M UPD Configuration +**/ +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FspsUpd.h b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h new file mode 100644 index 0000000..6b054e8 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FspsUpd.h @@ -0,0 +1,52 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + + +/** Fsp S UPD Configuration +**/ +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/quark/include/soc/fsp/FsptUpd.h b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h new file mode 100644 index 0000000..8b1ded7 --- /dev/null +++ b/src/soc/intel/quark/include/soc/fsp/FsptUpd.h @@ -0,0 +1,89 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + + +/** Fsp T Common UPD +**/ +struct FSPT_COMMON_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + uint32_t MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + uint32_t MicrocodeRegionLength; + +/** Offset 0x002C +**/ + uint32_t CodeRegionBase; + +/** Offset 0x0030 +**/ + uint32_t CodeRegionLength; + +/** Offset 0x0034 +**/ + uint8_t Reserved1[12]; +} __attribute__((packed)); + +/** Fsp T UPD Configuration +**/ +struct FSPT_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif

1 0

Patch set updated for coreboot: soc/intel/quark: Clean up debug output levels
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16006 -gerrit commit 5207ba0081de1220404123656b5323d7b435bf9a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 17:20:30 2016 -0700 soc/intel/quark: Clean up debug output levels Change the debug output levels for quark: * Remove excess debug output * Change BIOS_DEBUG to BIOS_SPEW - exception in report_platform.c TEST=Build and run on Galileo Gen2 Change-Id: I37d7ed21a7fc4c92efeb5b71dd01922d7d4b9192 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/acpi.c | 8 ++++---- src/soc/intel/quark/chip.c | 2 -- src/soc/intel/quark/reg_access.c | 2 +- src/soc/intel/quark/romstage/pcie.c | 3 --- src/soc/intel/quark/romstage/romstage.c | 5 ----- 5 files changed, 5 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index 90adc34..960b53f 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -97,9 +97,9 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe0_blk.addrh = 0; /* Display the base registers */ - printk(BIOS_DEBUG, "FADT:\n"); - printk(BIOS_DEBUG, " 0x%08x: GPE0_BASE\n", gpe0_base); - printk(BIOS_DEBUG, " 0x%08x: PMBASE\n", pmbase); - printk(BIOS_DEBUG, " 0x%08x: RESET\n", fadt->reset_reg.addrl); + printk(BIOS_SPEW, "FADT:\n"); + printk(BIOS_SPEW, " 0x%08x: GPE0_BASE\n", gpe0_base); + printk(BIOS_SPEW, " 0x%08x: PMBASE\n", pmbase); + printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl); } diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index c8c6b39..2281d34 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -136,10 +136,8 @@ static struct device_operations pci_domain_ops = { static void chip_enable_dev(device_t dev) { - const char *type_name = dev_path_name(dev->path.type); /* Set the operations if it is a special bus type */ - printk(BIOS_DEBUG, "type: %s\n", type_name); if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; } diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index a82383d..b930d4c 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -96,7 +96,7 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) offset = (index - MTRR_PHYS_BASE(0)) + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; else { - printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + printk(BIOS_SPEW, "index: 0x%08lx\n", index); die("Invalid MTRR index specified!\n"); } return offset; diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c index f2adc18..24dcf23 100644 --- a/src/soc/intel/quark/romstage/pcie.c +++ b/src/soc/intel/quark/romstage/pcie.c @@ -100,10 +100,7 @@ static const struct reg_script pcie_bus_init_script[] = { void pcie_init(void) { /* Initialize the PCIe bridges */ - printk(BIOS_DEBUG, "Initializing PCIe controllers\n"); reg_script_run(pcie_init_script); - printk(BIOS_DEBUG, "Initializing PCIe bus 0\n"); reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script); - printk(BIOS_DEBUG, "Initializing PCIe bus 1\n"); reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script); } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 9ee4135..e774993 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -18,7 +18,6 @@ #include <arch/early_variables.h> #include <console/console.h> #include <fsp/util.h> -#include <lib.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> @@ -53,7 +52,6 @@ void disable_rom_shadow(void) /* Determine if the shadow ROM is enabled */ data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC); - printk(BIOS_DEBUG, "0x%08x: HMISC\n", data); if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM)) != (ESEG_RD_DRAM | FSEG_RD_DRAM)) { @@ -62,7 +60,4 @@ void disable_rom_shadow(void) port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, data); } - - /* Display the DRAM data */ - hexdump((void *)0x000ffff0, 0x10); }

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Monitor FSP setting of MTRRs
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15849 -gerrit commit 5cf6f630026338f8756d5c7dade7826b4df08e33 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 08:26:06 2016 -0700 drivers/intel/fsp2_0: Monitor FSP setting of MTRRs Display the MTRR values in the following locations: * Before the call to FspMemoryInit to document coreboot settings * After the call to FspMemoryInit * After the call to FspSiliconInit * After the call to FspNotify TEST=Build and run on Galileo Gen2 Change-Id: I8942ef4ca4677501a5c38abaff1c3489eebea53c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/debug.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index 02e9487..6e28939 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -11,6 +11,7 @@ #include <console/console.h> #include <fsp/util.h> +#include <soc/intel/common/util.h> /*----------- * MemoryInit @@ -20,6 +21,10 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, const struct FSPM_UPD *fspm_old_upd, const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr) { + /* Display the MTRRs */ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + soc_display_mtrrs(); + /* Display the call entry point and paramters */ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", @@ -34,6 +39,10 @@ void fsp_debug_memory_init(enum fsp_status status, { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + /* Display the MTRRs */ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + soc_display_mtrrs(); } /*----------- @@ -55,6 +64,10 @@ void fsp_debug_silicon_init(enum fsp_status status) { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); + + /* Display the MTRRs */ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + soc_display_mtrrs(); } /*----------- @@ -77,4 +90,8 @@ void fsp_debug_notify(enum fsp_status status) { if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); + + /* Display the MTRRs */ + if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) + soc_display_mtrrs(); }

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add display HOB support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15851 -gerrit commit a02ce1991e8bcaedce5f62bce0b8c56169ed7a87 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jul 27 07:40:25 2016 -0700 drivers/intel/fsp2_0: Add display HOB support Add support to display the HOBs returned by FSP: * Add Kconfig value to enable HOB display * Move hob_header, hob_resource and uuid_name structures into util.h * Move hob_type enum into util.h * Remove static from the debug utility functions * Add fsp_ prefix to the debug utility functions * Declare the debug utility functions in debug.h * Add HOB type name table * Add more GUID values * Add new GUID name table for additional GUIDs * Add routine to convert EDK-II GUID into a name * Add SOC specific routine to handle unknown GUID types * Add routine to convert HOB type into a name * Add SOC specific routine to handle unknown HOB types * Add routine to display the hobs TEST=Build and run on Galileo Gen2 Change-Id: I10606d752859fff0f4f08a5ac03ab129b2c96d1f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 6 + src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/debug.c | 12 ++ src/drivers/intel/fsp2_0/hand_off_block.c | 68 ++++-------- src/drivers/intel/fsp2_0/hob_display.c | 157 +++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/debug.h | 11 ++ src/drivers/intel/fsp2_0/include/fsp/util.h | 37 +++++++ 7 files changed, 247 insertions(+), 46 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 32dbb59..06f1a7c 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -34,6 +34,12 @@ config DISPLAY_FSP_CALLS_AND_STATUS Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP. +config DISPLAY_HOBS + bool "Display the hand-off-blocks" + default n + help + Display the FSP HOBs which are provided for coreboot. + config DISPLAY_UPD_DATA bool "Display UPD data" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index cc496ee..2b1754e 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -17,6 +17,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) romstage-y += debug.c romstage-y += hand_off_block.c +romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-y += util.c romstage-y += memory_init.c @@ -24,6 +25,7 @@ romstage-y += memory_init.c ramstage-y += debug.c ramstage-y += graphics.c ramstage-y += hand_off_block.c +ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c index fc385b7..52e6765 100644 --- a/src/drivers/intel/fsp2_0/debug.c +++ b/src/drivers/intel/fsp2_0/debug.c @@ -44,6 +44,10 @@ void fsp_debug_memory_init(enum fsp_status status, if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + /* Display the HOBs */ + if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + fsp_display_hobs(hob_list_ptr); + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); @@ -73,6 +77,10 @@ void fsp_debug_silicon_init(enum fsp_status status) if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); + /* Display the HOBs */ + if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); @@ -99,6 +107,10 @@ void fsp_debug_notify(enum fsp_status status) if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); + /* Display the HOBs */ + if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + fsp_display_hobs((const struct hob_header *)fsp_get_hob_list()); + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index ce06a82..d3392cd 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -21,14 +21,6 @@ #define HOB_HEADER_LEN 8 -struct hob_resource { - uint8_t owner_guid[16]; - uint32_t type; - uint32_t attribute_type; - uint64_t addr; - uint64_t length; -} __attribute__((packed)); - enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, EFI_RESOURCE_MEMORY_MAPPED_IO = 1, @@ -50,21 +42,6 @@ static const char *resource_names[] = { [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", }; -enum hob_type { - HOB_TYPE_HANDOFF = 0x0001, - HOB_TYPE_MEMORY_ALLOCATION = 0x0002, - HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, - HOB_TYPE_GUID_EXTENSION = 0x0004, - HOB_TYPE_FV = 0x0005, - HOB_TYPE_CPU = 0x0006, - HOB_TYPE_MEMORY_POOL = 0x0007, - HOB_TYPE_FV2 = 0x0009, - HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, - HOB_TYPE_UCAPSULE = 0x000B, - HOB_TYPE_UNUSED = 0xFFFE, - HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, -}; - /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ static const uint8_t uuid_owner_bootloader_tolum[16] = { 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, @@ -90,15 +67,13 @@ static const uint8_t empty_uuid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; -static const struct uuid_name_map { - const void *uuid; - const char *name; -} uuid_names[] = { +const struct uuid_name_map uuid_names[] = { { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, { uuid_owner_tseg, "TSEG" }, { uuid_fsp_nv_storage, "FSP_NV_STORAGE" }, }; +const size_t uuid_names_entries = ARRAY_SIZE(uuid_names); static const char *resource_name(enum resource_type type) { @@ -111,7 +86,7 @@ static const char *resource_name(enum resource_type type) * Utilities for walking HOBs */ -static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) { return !memcmp(uuid1, uuid2, 16); } @@ -123,13 +98,13 @@ static const char *uuid_name(const uint8_t uuid[16]) for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { owner_entry = uuid_names + i; - if (uuid_compare(uuid, owner_entry->uuid)) + if (fsp_uuid_compare(uuid, owner_entry->uuid)) return owner_entry->name; } return "UNKNOWN"; } -static const struct hob_header *next_hob(const struct hob_header *parent) +const struct hob_header *fsp_next_hob(const struct hob_header *parent) { union { const struct hob_header *hob; @@ -167,8 +142,8 @@ static const void *hob_header_to_extension_hob(const struct hob_header *hob) return hob_walker.hob_descr; } -static const -struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +const +struct hob_resource *fsp_hob_header_to_resource(const struct hob_header *hob) { return hob_header_to_struct(hob); } @@ -197,13 +172,14 @@ struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, { const struct hob_resource *res; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) continue; - res = hob_header_to_resource(hob); - if (uuid_compare(res->owner_guid, uuid)) + res = fsp_hob_header_to_resource(hob); + if (fsp_uuid_compare(res->owner_guid, uuid)) return res; } return NULL; @@ -228,7 +204,7 @@ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list) * Utilities for printing HOB information */ -static void print_guid(const void *base) +void fsp_print_guid(const void *base) { uint32_t big; uint16_t mid[2]; @@ -243,30 +219,30 @@ static void print_guid(const void *base) id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } -static void print_resource_descriptor(const void *base) +void fsp_print_resource_descriptor(const void *base) { const struct hob_resource *res; - res = hob_header_to_resource(base); + res = fsp_hob_header_to_resource(base); printk(BIOS_DEBUG, "Resource %s, attribute %x\n", resource_name(res->type), res->attribute_type); printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); - if (!uuid_compare(res->owner_guid, empty_uuid)) { + if (!fsp_uuid_compare(res->owner_guid, empty_uuid)) { printk(BIOS_DEBUG, "\tOwner GUID: "); - print_guid(res->owner_guid); + fsp_print_guid(res->owner_guid); printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); } } - void fsp_print_memory_resource_hobs(const void *hob_list) { const struct hob_header *hob = hob_list; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) - print_resource_descriptor(hob); + fsp_print_resource_descriptor(hob); } } @@ -278,13 +254,14 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) if (!hob) return NULL; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) continue; hob_uuid = hob_header_to_struct(hob); - if (uuid_compare(hob_uuid, uuid)) { + if (fsp_uuid_compare(hob_uuid, uuid)) { *size = hob->length - (HOB_HEADER_LEN + 16); return hob_header_to_extension_hob(hob); } @@ -293,7 +270,6 @@ const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) return NULL; } - const void *fsp_find_nv_storage_data(size_t *size) { return fsp_find_extension_hob_by_uuid(uuid_fsp_nv_storage, size); diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c new file mode 100644 index 0000000..6a49eaa --- /dev/null +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +struct hob_type_name { + uint16_t type; + const char *name; +} __attribute__((packed)); + +static const struct hob_type_name hob_type_names [] = { + { HOB_TYPE_HANDOFF, "HOB_TYPE_HANDOFF" }, + { HOB_TYPE_MEMORY_ALLOCATION, "HOB_TYPE_MEMORY_ALLOCATION" }, + { HOB_TYPE_RESOURCE_DESCRIPTOR, "HOB_TYPE_RESOURCE_DESCRIPTOR" }, + { HOB_TYPE_GUID_EXTENSION, "HOB_TYPE_GUID_EXTENSION" }, + { HOB_TYPE_FV, "HOB_TYPE_FV" }, + { HOB_TYPE_CPU, "HOB_TYPE_CPU" }, + { HOB_TYPE_MEMORY_POOL, "HOB_TYPE_MEMORY_POOL" }, + { HOB_TYPE_FV2, "HOB_TYPE_FV2" }, + { HOB_TYPE_LOAD_PEIM_UNUSED, "HOB_TYPE_LOAD_PEIM_UNUSED" }, + { HOB_TYPE_UCAPSULE, "HOB_TYPE_UCAPSULE" }, + { HOB_TYPE_UNUSED, "HOB_TYPE_UNUSED" }, + { HOB_TYPE_END_OF_HOB_LIST, "HOB_TYPE_END_OF_HOB_LIST" } +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +static const uint8_t uuid_smbios_memory_info[16] = { + 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49, + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89 +}; + +static const uint8_t uuid_bootloader_temp_memory[16] = { + 0x6c, 0xf4, 0xcf, 0xbb, 0xd3, 0xc8, 0x13, 0x41, + 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e +}; + +static const uint8_t uuid_fsp_info_header[16] = { + 0xbe, 0x40, 0x27, 0x91, 0x84, 0x22, 0x34, 0x47, + 0xb9, 0x71, 0x84, 0xb0, 0x27, 0x35, 0x3f, 0x0c +}; + +static const struct uuid_name_map guid_names[] = { + { uuid_graphics_info, "GRAPHICS INFO" }, + { uuid_smbios_memory_info, "FSP_SMBIOS_MEMORY_INFO_GUID" }, + { uuid_bootloader_temp_memory, "FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID" }, + { uuid_fsp_info_header, "FSP_INFO_HEADER_GUID" }, +}; + +const char *fsp_get_hob_type_name(const struct hob_header *hob) +{ + size_t index; + const char *name; + + for (index = 0; index < ARRAY_SIZE(hob_type_names); index++) + if (hob->type == hob_type_names[index].type) + return hob_type_names[index].name; + + /* Get name for SOC specific hob */ + name = soc_get_hob_type_name(hob); + if (name != NULL) + return name; + return "Unknown HOB type"; +} + +const char *fsp_get_guid_name(const uint8_t *guid) +{ + size_t index; + const char *name; + + /* Compare the GUID values in hand_off_block.c */ + for (index = 0; index < uuid_names_entries; index++) + if (fsp_uuid_compare(guid, uuid_names[index].uuid)) + return uuid_names[index].name; + + /* Compare the GUID values in this module */ + for (index = 0; index < ARRAY_SIZE(guid_names); index++) + if (fsp_uuid_compare(guid, guid_names[index].uuid)) + return guid_names[index].name; + + /* Get GUID name from SOC */ + name = soc_get_guid_name(guid); + if (name != NULL) + return name; + return "Unknown GUID"; +} + +__attribute__((weak)) const char *soc_get_hob_type_name( + const struct hob_header *hob) +{ + return NULL; +} + +void fsp_print_guid_extension_hob(const struct hob_header *hob) +{ + const struct hob_resource *res; + + res = fsp_hob_header_to_resource(hob); + printk(BIOS_SPEW, "\t"); + fsp_print_guid(res->owner_guid); + printk(BIOS_SPEW, ": %s\n", fsp_get_guid_name(res->owner_guid)); +} + +__attribute__((weak)) const char *soc_get_guid_name(const uint8_t *guid) +{ + return NULL; +} + +void fsp_display_hobs(const struct hob_header *hob_list_ptr) +{ + const struct hob_header *hob = hob_list_ptr; + + /* Display the HOB list pointer */ + printk(BIOS_SPEW, "\n=== FSP HOBs ===\n"); + printk(BIOS_SPEW, "0x%p: hob_list_ptr\n", hob); + + /* Walk the list of HOBs */ + while (1) { + /* Display the HOB header */ + printk(BIOS_DEBUG, "0x%p, 0x%08x bytes: %s\n", hob, hob->length, + fsp_get_hob_type_name(hob)); + switch(hob->type) { + default: + soc_display_hob(hob); + break; + + case HOB_TYPE_END_OF_HOB_LIST: + printk(BIOS_DEBUG, "=== End of FSP HOBs ===\n\n"); + return; + + case HOB_TYPE_RESOURCE_DESCRIPTOR: + fsp_print_resource_descriptor(hob); + break; + + case HOB_TYPE_GUID_EXTENSION: + fsp_print_guid_extension_hob(hob); + break; + } + hob = fsp_next_hob(hob); + } +} + +__attribute__((weak)) void soc_display_hob(const struct hob_header *hob) +{ +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h index 08c0381..f777c33 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/debug.h +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -29,6 +29,7 @@ void fsp_before_debug_notify(fsp_notify_fn notify, void fsp_debug_notify(enum fsp_status status); void fspm_display_upd_values(const struct FSPM_UPD *old, const struct FSPM_UPD *new); +void fsp_display_hobs(const struct hob_header *hob_list_ptr); /* Callbacks for displaying UPD parameters - place in a separate file * that is conditionally build with CONFIG_DISPLAY_UPD_DATA. @@ -38,8 +39,18 @@ void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd, const struct FSPS_UPD *fsps_new_upd); +/* Callbacks for displaying HOBs - place in a separate file that is + * conditionally build with CONFIG_DISPLAY_HOBS. + */ +const char *soc_get_hob_type_name(const struct hob_header *hob); +const char *soc_get_guid_name(const uint8_t *guid); +void soc_display_hob(const struct hob_header *hob); + /* FSP debug utility functions */ void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); +const char *fsp_get_hob_type_name(const struct hob_header *hob); +const char *fsp_get_guid_name(const uint8_t *guid); +void fsp_print_guid_extension_hob(const struct hob_header *hob); #endif /* _FSP2_0_DEBUG_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index b16a6ec..bda265a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -29,6 +29,37 @@ struct fsp_notify_params { enum fsp_notify_phase phase; }; +struct uuid_name_map { + const void *uuid; + const char *name; +}; + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +extern const struct uuid_name_map uuid_names[]; +extern const size_t uuid_names_entries; + /* * Hand-off-block handling functions that depend on CBMEM, and thus can only * be used after cbmem_initialize(). @@ -43,7 +74,13 @@ enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); * the HOB list explicitly. */ void fsp_find_reserved_memory(struct range_entry *re, const void *hob_list); +const struct hob_resource *fsp_hob_header_to_resource( + const struct hob_header *hob); +const struct hob_header *fsp_next_hob(const struct hob_header *parent); +void fsp_print_guid(const void *guid); void fsp_print_memory_resource_hobs(const void *hob_list); +void fsp_print_resource_descriptor(const void *base); +bool fsp_uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr,

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coreboot-gerrit August 2016