coreboot-gerrit August 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Display FSP calls and status
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15989 -gerrit commit 08c7538d420857b6185f31a1c63c78755fe3bbf6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:21:13 2016 -0700 drivers/intel/fsp2_0: Display FSP calls and status Disable the chatty FSP behavior for normal builds. Use a Kconfig value to enable the display of the FSP call entry points, the call parameters and the returned status for MemoryInit, SiliconInit and FspNotify. The debug code is placed into drivers/intel/fsp2_0/debug.c. TEST=Build and run on Galileo Gen2 Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +++ src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/debug.c | 80 ++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/hand_off_block.c | 5 -- src/drivers/intel/fsp2_0/include/fsp/debug.h | 31 +++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 18 +++++++ src/drivers/intel/fsp2_0/memory_init.c | 10 ++-- src/drivers/intel/fsp2_0/notify.c | 11 +--- src/drivers/intel/fsp2_0/silicon_init.c | 12 ++--- 9 files changed, 149 insertions(+), 27 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 01ce75d..7f4bbee 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -27,6 +27,13 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added. +config DISPLAY_FSP_CALLS_AND_STATUS + bool "Display the FSP calls and status" + default n + help + Display the FSP call entry point and parameters prior to calling FSP + and display the status upon return from FSP. + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 4f36664..9ec5192 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -15,10 +15,12 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-y += debug.c romstage-y += hand_off_block.c romstage-y += util.c romstage-y += memory_init.c +ramstage-y += debug.c ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-y += notify.c diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c new file mode 100644 index 0000000..02e9487 --- /dev/null +++ b/src/drivers/intel/fsp2_0/debug.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +/*----------- + * MemoryInit + *----------- + */ +void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr) +{ + /* Display the call entry point and paramters */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", + memory_init); + printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd); + printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", hob_list_ptr); + } +} + +void fsp_debug_memory_init(enum fsp_status status, + const struct hob_header *hob_list_ptr) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); +} + +/*----------- + * SiliconInit + *----------- + */ +void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd) +{ + /* Display the call to FSP SiliconInit */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init); + printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd); + } +} + +void fsp_debug_silicon_init(enum fsp_status status) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status); +} + +/*----------- + * FspNotify + *----------- + */ +void fsp_before_debug_notify(fsp_notify_fn notify, + const struct fsp_notify_params *notify_params) +{ + /* Display the call to FSP SiliconInit */ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) { + printk(BIOS_SPEW, "0x%08x: notify_params->phase\n", + notify_params->phase); + printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify); + printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params); + } +} + +void fsp_debug_notify(enum fsp_status status) +{ + if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS)) + printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status); +} diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index b7cb981..ce06a82 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -21,11 +21,6 @@ #define HOB_HEADER_LEN 8 -struct hob_header { - uint16_t type; - uint16_t length; -} __attribute__((packed)); - struct hob_resource { uint8_t owner_guid[16]; uint32_t type; diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h new file mode 100644 index 0000000..5cc1642 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_DEBUG_H_ +#define _FSP2_0_DEBUG_H_ + +#include <fsp/util.h> + +/* FSP debug API */ +void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init, + const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr); +void fsp_debug_memory_init(enum fsp_status status, + const struct hob_header *hob_list_ptr); +void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init, + const struct FSPS_UPD *fsps_old_upd, + const struct FSPS_UPD *fsps_new_upd); +void fsp_debug_silicon_init(enum fsp_status status); +void fsp_before_debug_notify(fsp_notify_fn notify, + const struct fsp_notify_params *notify_params); +void fsp_debug_notify(enum fsp_status status); + +#endif /* _FSP2_0_DEBUG_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 01186f7..b16a6ec 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -15,10 +15,20 @@ #include <boot/coreboot_tables.h> #include <commonlib/region.h> +#include <arch/cpu.h> #include <fsp/api.h> #include <fsp/info_header.h> #include <memrange.h> +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct fsp_notify_params { + enum fsp_notify_phase phase; +}; + /* * Hand-off-block handling functions that depend on CBMEM, and thus can only * be used after cbmem_initialize(). @@ -53,4 +63,12 @@ void fsp_handle_reset(enum fsp_status status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(enum fsp_status status); +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (void *raminit_upd, void **hob_list); +typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) + (void *silicon_upd); +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); +#include <fsp/debug.h> + #endif /* _FSP2_0_UTIL_H_ */ diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 8e3eb68..4921e88 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -29,9 +29,6 @@ #include <timestamp.h> #include <vboot/vboot_common.h> -typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) - (void *raminit_upd, void **hob_list); - static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -221,9 +218,8 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); - printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); - printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd); - printk(BIOS_SPEW, "\t%p: hob_list ptr\n", &hob_list_ptr); + fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd, + &hob_list_ptr); post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); @@ -231,7 +227,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, post_code(POST_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); - printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + fsp_debug_memory_init(status, hob_list_ptr); /* Handle any resets requested by FSPM. */ fsp_handle_reset(status); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 4e7e9c5..139e172 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -17,13 +17,6 @@ #include <string.h> #include <timestamp.h> -struct fsp_notify_params { - enum fsp_notify_phase phase; -}; - -typedef asmlinkage enum fsp_status (*fsp_notify_fn) - (struct fsp_notify_params *); - enum fsp_status fsp_notify(enum fsp_notify_phase phase) { enum fsp_status ret; @@ -35,8 +28,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) fspnotify = (void*) (fsps_hdr.image_base + fsps_hdr.notify_phase_entry_offset); - - printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + fsp_before_debug_notify(fspnotify, &notify_params); if (phase == AFTER_PCI_ENUM) { timestamp_add_now(TS_FSP_BEFORE_ENUMERATE); @@ -55,6 +47,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase) timestamp_add_now(TS_FSP_AFTER_FINALIZE); post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE); } + fsp_debug_notify(ret); return ret; } diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index c069ff1..b9fea66 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -23,9 +23,6 @@ struct fsp_header fsps_hdr; -typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) - (void *silicon_upd); - static enum fsp_status do_silicon_init(struct fsp_header *hdr) { struct FSPS_UPD upd, *supd; @@ -44,15 +41,18 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(&upd); - timestamp_add_now(TS_FSP_SILICON_INIT_START); - post_code(POST_FSP_SILICON_INIT); + /* Call SiliconInit */ silicon_init = (void *) (hdr->image_base + hdr->silicon_init_entry_offset); + fsp_debug_before_silicon_init(silicon_init, supd, &upd); + + timestamp_add_now(TS_FSP_SILICON_INIT_START); + post_code(POST_FSP_SILICON_INIT); status = silicon_init(&upd); timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_INIT); - printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + fsp_debug_silicon_init(status); /* Handle any resets requested by FSPS. */ fsp_handle_reset(status);

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Patch set updated for coreboot: soc/intel/common: Fix build error in reset.c
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15988 -gerrit commit 7a08a70553d322361fe9900202bf1c875f0f8db2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 10:29:37 2016 -0700 soc/intel/common: Fix build error in reset.c Fix build error caused by macro substitution in the function definition when the Kconfig value HAVE_HARD_RESET is not selected. src/soc/intel/common/reset.c:36:21: error: macro "hard_reset" passed 1 arguments, but takes just 0 void hard_reset(void) ^ src/soc/intel/common/reset.c:37:1: error: expected '=', ',', ';', 'asm' or '__attribute__' before '{' token { ^ make: *** [build/bootblock/soc/intel/common/reset.o] Error 1 TEST=Build and run on Galileo Gen2 Change-Id: I793570e62a0e46cca86cc540c243e363896ceac7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/reset.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/common/reset.c b/src/soc/intel/common/reset.c index 08f36b6..e9be185 100644 --- a/src/soc/intel/common/reset.c +++ b/src/soc/intel/common/reset.c @@ -33,6 +33,7 @@ void WEAK reset_prepare(void) { /* do nothing */ } +#if IS_ENABLED(CONFIG_HAVE_HARD_RESET) void hard_reset(void) { reset_prepare(); @@ -41,6 +42,7 @@ void hard_reset(void) while (1) hlt(); } +#endif void soft_reset(void) {

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Patch set updated for coreboot: soc/intel/quark: Make ramstage relocatable
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15994 -gerrit commit 8468812963d24495364a897c653e8501d0308cfc Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 14:14:02 2016 -0700 soc/intel/quark: Make ramstage relocatable Relocate ramstage into CBMEM. TEST=Build and run on Galileo Gen2 Change-Id: I38861f2af4b7b976c7ebb7226d81242f950981e3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index b9060d5..244cc30 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS select C_ENVIRONMENT_BOOTBLOCK select HAVE_HARD_RESET select REG_SCRIPT + select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS

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Patch set updated for coreboot: soc/intel/quark: Enable use of hard reset
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15992 -gerrit commit 48ec4050baf882d8b383bb66efb998a677ad9bed Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jul 30 10:34:22 2016 -0700 soc/intel/quark: Enable use of hard reset Select HAVE_HARD_RESET in the KCONFIG file to enable use of the hard_reset routine. TEST=Build and run on Galileo Gen2 Change-Id: Ib11a80b64cf1c55aec24f2576d197da9017b9751 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 116dc9f..b9060d5 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -28,8 +28,10 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP select C_ENVIRONMENT_BOOTBLOCK + select HAVE_HARD_RESET select REG_SCRIPT select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET select SOC_SETS_MSRS select TSC_CONSTANT_RATE select UART_OVERRIDE_REFCLK

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Patch set updated for coreboot: mainboard/intel/galileo: Add FSP 2.0 Kconfig support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15864 -gerrit commit 0d97462c9ea3d4f945cc582e77627558986268bd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:18:13 2016 -0700 mainboard/intel/galileo: Add FSP 2.0 Kconfig support Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index b0c69e4..2acc439 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -49,5 +49,12 @@ config USE_FSP1_1 bool default n select PLATFORM_USES_FSP1_1 +# select ADD_FSP_RAW_BIN + +config USE_FSP2_0 + bool + default n + select PLATFORM_USES_FSP2_0 + select POSTCAR_STAGE endif # BOARD_INTEL_QUARK

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Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 boot block support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15865 -gerrit commit d8c351ccc90ff038fd11efe5d66a696e95a60e66 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 07:41:54 2016 -0700 soc/intel/quark: Add FSP 2.0 boot block support Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Bulid and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + src/mainboard/intel/galileo/Makefile.inc | 3 +++ src/mainboard/intel/galileo/gpio.c | 4 ++++ src/mainboard/intel/galileo/romstage.c | 2 ++ src/soc/intel/quark/Makefile.inc | 10 +++++++++ src/soc/intel/quark/fsp2_0.c | 25 +++++++++++++++++++++ src/soc/intel/quark/include/soc/car.h | 29 ++++++++++++++++++++++++ src/soc/intel/quark/include/soc/ramstage.h | 6 +++++ src/soc/intel/quark/include/soc/romstage.h | 4 ++++ src/soc/intel/quark/memmap.c | 4 +++- src/soc/intel/quark/reset.c | 31 ++++++++++++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 3 +++ src/soc/intel/quark/romstage/car_stage_entry.S | 2 ++ src/soc/intel/quark/romstage/fsp2_0.c | 26 +++++++++++++++++++++ 14 files changed, 149 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 2acc439..1b651d5 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -54,6 +54,7 @@ config USE_FSP1_1 config USE_FSP2_0 bool default n + select HAVE_HARD_RESET select PLATFORM_USES_FSP2_0 select POSTCAR_STAGE diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 5aad308..efaf007 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -23,5 +23,8 @@ bootblock-y += reg_access.c romstage-y += gpio.c romstage-y += reg_access.c +postcar-y += gpio.c +postcar-y += reg_access.c + ramstage-y += gpio.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c index 8f3c2e3..f654d19 100644 --- a/src/mainboard/intel/galileo/gpio.c +++ b/src/mainboard/intel/galileo/gpio.c @@ -15,7 +15,11 @@ #include <arch/io.h> #include <console/console.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/ramstage.h> #include "reg_access.h" #include "gen1.h" diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c index dfae772..baf9af3 100644 --- a/src/mainboard/intel/galileo/romstage.c +++ b/src/mainboard/intel/galileo/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> /* All FSP specific code goes in this block */ @@ -22,3 +23,4 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Call back into chipset code with platform values updated. */ romstage_common(rp); } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 4740ec7..52d77bf 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -31,22 +31,32 @@ romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +postcar-y += fsp2_0.c +postcar-y += i2c.c +postcar-y += memmap.c +postcar-y += reg_access.c +postcar-y += tsc_freq.c +postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c new file mode 100644 index 0000000..deb9334 --- /dev/null +++ b/src/soc/intel/quark/fsp2_0.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <fsp/util.h> +#include <soc/ramstage.h> + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ +} + +asmlinkage void chipset_teardown_car(void) +{ +} diff --git a/src/soc/intel/quark/include/soc/car.h b/src/soc/intel/quark/include/soc/car.h new file mode 100644 index 0000000..23c6a24 --- /dev/null +++ b/src/soc/intel/quark/include/soc/car.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_CAR_H_ +#define _SOC_CAR_H_ + +#include <fsp/util.h> + +/* Mainboard and SoC initialization prior to console. */ +void car_mainboard_pre_console_init(void); +void car_soc_pre_console_init(void); + +/* Mainboard and SoC initialization post console initialization. */ +void car_mainboard_post_console_init(void); +void car_soc_post_console_init(void); + +#endif /* _SOC_CAR_H_ */ diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 9f201a0..b5e15ae 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,10 +19,16 @@ #include <chip.h> #include <device/device.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/ramstage.h> +#endif #include <soc/QuarkNcSocId.h> void mainboard_gpio_i2c_init(device_t dev); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void fsp_silicon_init(void); +#else +asmlinkage void chipset_teardown_car(void); +#endif #endif /* _SOC_RAMSTAGE_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index fcac3e2..d6f9186 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,11 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/romstage.h> +#else +#include <soc/car.h> +#endif #include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void); diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index f880443..28f8852 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -14,15 +14,17 @@ */ #include <cbmem.h> +#include <soc/reg_access.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp/memmap.h> #include <soc/QuarkNcSocId.h> -#include <soc/reg_access.h> size_t mmap_region_granularity(void) { /* Align to 8 MiB by default */ return 8 << 20; } +#endif /* IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) */ void *cbmem_top(void) { diff --git a/src/soc/intel/quark/reset.c b/src/soc/intel/quark/reset.c new file mode 100644 index 0000000..e898432 --- /dev/null +++ b/src/soc/intel/quark/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> +#include <reset.h> + +void chipset_handle_reset(enum fsp_status status) +{ + switch(status) { + case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */ + hard_reset(); + break; + default: + printk(BIOS_ERR, "unhandled reset type %x\n", status); + die("unknown reset type"); + break; + } +} diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 635da83..329138b 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,7 +16,10 @@ romstage-y += car.c romstage-y += car_stage_entry.S romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c romstage-y += romstage.c + +postcar-y += mtrr.c diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index d0a0db0..b820711 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -29,9 +29,11 @@ car_stage_entry: /* Enter the C code */ call car_stage_c_entry +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #if !ENV_VERSTAGE #include "src/drivers/intel/fsp1_1/after_raminit.S" #endif +#endif /* The code should never reach this point */ movb $0x69, %ah diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c new file mode 100644 index 0000000..494f84a --- /dev/null +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> +#include <soc/romstage.h> + +asmlinkage void *car_stage_c_entry(void) +{ + post_code(0x20); + console_init(); + return NULL; +}

1 0

Patch set updated for coreboot: soc/intel/quark: Add FSP 2.0 romstage support
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15866 -gerrit commit 4d17a18e2a4bc0eadf2f8030b0bed0ba0369f4bb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jul 25 10:14:07 2016 -0700 soc/intel/quark: Add FSP 2.0 romstage support Add the pieces necessary to successfully build adn run romstage using the FSP 2.0 build. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 23 ++++- src/soc/intel/quark/Makefile.inc | 4 + src/soc/intel/quark/include/soc/pm.h | 6 +- src/soc/intel/quark/romstage/Makefile.inc | 5 +- src/soc/intel/quark/romstage/debug.c | 86 +++++++++++++++++ src/soc/intel/quark/romstage/fsp2_0.c | 152 ++++++++++++++++++++++++++++++ 6 files changed, 272 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 244cc30..c1a35b2 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -127,11 +127,20 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT config DCACHE_RAM_BASE hex + default 0x80000000 if PLATFORM_USES_FSP2_0 default 0x80070000 config DCACHE_RAM_SIZE hex - default 0x00008000 + default 0x40000 if PLATFORM_USES_FSP2_0 + default 0x8000 + +config DISPLAY_ESRAM_LAYOUT + bool "Display ESRAM layout" + default n + depends on PLATFORM_USES_FSP2_0 + help + Select this option to display coreboot's use of ESRAM. ##### # Flash layout @@ -194,8 +203,8 @@ config FSP_LOC config FSP_ESRAM_LOC hex + default 0x80040000 if PLATFORM_USES_FSP2_0 default 0x80000000 - depends on PLATFORM_USES_FSP1_1 help The location in ESRAM where a copy of the FSP binary is placed. @@ -206,6 +215,16 @@ config RELOCATE_FSP_INTO_DRAM help Relocate the FSP binary into DRAM before the call to SiliconInit. +config FSP_M_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_M.fd" + +config FSP_S_FILE + string + depends on PLATFORM_USES_FSP2_0 + default "3rdparty/blobs/soc/intel/quark/FSP_S.fd" + ##### # RMU binary # The following options control the Quark chipset microcode file diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 52d77bf..bd297ed 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += memmap.c romstage-y += reg_access.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c postcar-y += fsp2_0.c postcar-y += i2c.c @@ -61,6 +62,9 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC) + # Add the FSP binary to the CBFS image cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index 7547a53..55e5e95 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -25,6 +25,10 @@ struct chipset_power_state { } __attribute__ ((packed)); struct chipset_power_state *get_power_state(void); +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) struct chipset_power_state *fill_power_state(void); - +#else +int fill_power_state(void); #endif + +#endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 329138b..3a33f43 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,8 +15,11 @@ romstage-y += car.c romstage-y += car_stage_entry.S -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c +endif # CONFIG_PLATFORM_USES_FSP2_0 +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c new file mode 100644 index 0000000..6e85a5c --- /dev/null +++ b/src/soc/intel/quark/romstage/debug.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <fsp/util.h> + +void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd, + const struct FSPM_UPD *fspm_new_upd) +{ + const struct FSP_M_CONFIG *new; + const struct FSP_M_CONFIG *old; + + old = &fspm_old_upd->FspmConfig; + new = &fspm_new_upd->FspmConfig; + + /* Display the parameters for MemoryInit */ + printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); +} diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 494f84a..6d4267b 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,13 +14,165 @@ */ #define __SIMPLE_DEVICE__ +#include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> +#include <cbmem.h> +#include "../chip.h" +#include <cpu/x86/cache.h> #include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *car_stage_c_entry(void) { + struct postcar_frame pcf; + bool s3wake; + uintptr_t top_of_ram; + uintptr_t top_of_low_usable_memory; + post_code(0x20); console_init(); + + /* Initialize DRAM */ + s3wake = fill_power_state() == ACPI_S3; + fsp_memory_init(s3wake); + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + disable_rom_shadow(); + + /* Initialize the PCIe bridges */ + pcie_init(); + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Locate the top of RAM */ + top_of_low_usable_memory = (uintptr_t) cbmem_top(); + top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB); + + /* Cache postcar and ramstage */ + postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB, + MTRR_TYPE_WRBACK); + + /* Cache RMU area */ + postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory, + 0x10000, MTRR_TYPE_WRTHROUGH); + + /* Cache ESRAM */ + postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); + + /* Cache SPI flash - Write protect not supported */ + postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE), + CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH); + + run_postcar_phase(&pcf); return NULL; } + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_power_state(void) +{ + return (struct chipset_power_state *)car_get_var_ptr(&power_state); +} + +int fill_power_state(void) +{ + struct chipset_power_state *ps = get_power_state(); + + ps->prev_sleep_state = 0; + printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps->prev_sleep_state; +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) +{ + struct FSPM_ARCH_UPD *aupd; + const struct device *dev; + const struct soc_intel_quark_config *config; + char *rmu_file; + size_t rmu_file_len; + struct FSP_M_CONFIG *upd; + + /* Clear SMI and wake events */ + clear_smi_and_wake_events(); + + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + + /* Locate the configuration data from devicetree.cb */ + dev = dev_find_slot(0, LPC_DEV_FUNC); + if (!dev) { + die("ERROR - LPC device not found!"); + } + config = dev->chip_info; + + /* Update the architectural UPD values. */ + aupd = &fspm_upd->FspmArchUpd; + aupd->BootLoaderTolumSize = cbmem_overhead_size(); + aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize); + aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; + + /* Display the ESRAM layout */ + if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) { + printk(BIOS_SPEW, "\nESRAM Layout:\n\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80080000 - ESRAM end\n"); + printk(BIOS_SPEW, "| FSP binary |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n", + CONFIG_FSP_ESRAM_LOC); + printk(BIOS_SPEW, "| FSP stack |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + aupd->StackBase); + printk(BIOS_SPEW, "| |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_relocatable_data_end); + printk(BIOS_SPEW, "| coreboot data |\n"); + printk(BIOS_SPEW, "+-------------------+ 0x%p\n", + _car_stack_end); + printk(BIOS_SPEW, "| coreboot stack |\n"); + printk(BIOS_SPEW, + "+-------------------+ 0x80000000 - ESRAM start\n\n"); + } + + /* Update the UPD data for MemoryInit */ + upd = &fspm_upd->FspmConfig; + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; +}

1 0

Patch set updated for coreboot: arch/x86: Enable postcar console
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16001 -gerrit commit 7efd4deebf9c5fa6702484dd4c9333e06e794748 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 11:53:28 2016 -0700 arch/x86: Enable postcar console Add a Kconfig value to enable the console during postcar. Add a call to console_init at the beginning of the postcar stage in exit_car.S. TEST=Build and run on Galileo Gen2 Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/exit_car.S | 5 +++++ src/console/Kconfig | 7 +++++++ src/console/init.c | 2 +- src/include/console/console.h | 3 ++- 4 files changed, 15 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index a51d662..13c2390 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -26,6 +26,11 @@ stack_top: .text .global _start _start: +#if IS_ENABLED(CONFIG_POSTCAR_CONSOLE) + /* Enable the console */ + call console_init +#endif /* CONFIG_POSTCAR_CONSOLE */ + /* chipset_teardown_car() is expected to disable cache-as-ram. */ call chipset_teardown_car diff --git a/src/console/Kconfig b/src/console/Kconfig index 90fb426..e945c25 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -7,6 +7,13 @@ config BOOTBLOCK_CONSOLE help Use console during the bootblock if supported +config POSTCAR_CONSOLE + bool "Enable console output during postcar." + depends on POSTCAR_STAGE + default n + help + Use console during the postcar if supported + config SQUELCH_EARLY_SMP bool "Squelch AP CPUs from early console." default y diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..189079b 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -30,7 +30,7 @@ int console_log_level(int msg_level) return (console_loglevel >= msg_level); } -void console_init(void) +asmlinkage void console_init(void) { #if !defined(__PRE_RAM__) console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; diff --git a/src/include/console/console.h b/src/include/console/console.h index ddb5c052..dcd5fe9 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -18,6 +18,7 @@ #include <stdint.h> #include <rules.h> +#include <arch/cpu.h> #include <console/post_codes.h> #include <commonlib/loglevel.h> @@ -51,7 +52,7 @@ void __attribute__ ((noreturn)) die(const char *msg); (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__ -void console_init(void); +asmlinkage void console_init(void); int console_log_level(int msg_level); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte);

1 0

Patch set updated for coreboot: soc/intel/quark: Remove use of EDK-II macros and data types
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15858 -gerrit commit cf71b9a69c95695d102260f671fe26e63f9eb787 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jul 21 09:17:10 2016 -0700 soc/intel/quark: Remove use of EDK-II macros and data types Replace the use of ASSERT macro with if/die. Replace the use of UINT32 data type with uint32_t. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2 Change-Id: I0bb7e43ea570f7b20355c5d05675ebf593942e83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 15 +++++++----- src/soc/intel/quark/chip.h | 52 ++++++++++++++++++++-------------------- src/soc/intel/quark/i2c.c | 20 ++++++++++------ src/soc/intel/quark/memmap.c | 2 +- src/soc/intel/quark/reg_access.c | 12 ++++++---- 5 files changed, 57 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 30ab48a..07eca13 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -101,19 +101,22 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { /* Validate the temperature settings */ - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); - ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS - > PLATFORM_CATASTROPHIC_CLEAR_CELSIUS); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS > 255\n"); + if(PLATFORM_CATASTROPHIC_TRIP_CELSIUS + <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS) + die("PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= PLATFORM_CATASTROPHIC_CLEAR_CELSIUS\n"); /* Set the temperature settings */ reg_script_run(thermal_init_script); /* Verify that the thermal configuration is locked */ - ASSERT((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) + if((reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) - == (TS_LOCK_THRM_CTRL_REGS_ENABLE - | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); + != (TS_LOCK_THRM_CTRL_REGS_ENABLE + | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) + die("(reg_rmu_temp_read(QUARK_NC_RMU_REG_CONFIG) & (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)) != (TS_LOCK_THRM_CTRL_REGS_ENABLE | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)\n"); /* Perform silicon specific init. */ if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM)) diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 66105ea..b239631 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -47,70 +47,70 @@ struct soc_intel_quark_config { * the FSP PCD field name. */ - UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */ + uint32_t FspReservedMemoryLength; /* FSP reserved memory in bytes */ - UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */ - UINT32 tRAS; /* ACT to PRE command period in picoseconds */ + uint32_t Flags; /* Bitmap of MRC_FLAG_XXX defs above */ + uint32_t tRAS; /* ACT to PRE command period in picoseconds */ /* Delay from start of internal write transaction to internal read * command in picoseconds */ - UINT32 tWTR; + uint32_t tWTR; /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tRRD; + uint32_t tRRD; /* Four activate window (JESD79 specific to page size 1K/2K) in * picoseconds */ - UINT32 tFAW; - UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */ + uint32_t tFAW; + uint8_t DramWidth; /* 0=x8, 1=x16, others=RESERVED */ /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU * support 1066 memory */ - UINT8 DramSpeed; - UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ + uint8_t DramSpeed; + uint8_t DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ - UINT8 RankMask; - UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ - UINT8 ChanWidth; /* 1=x16, others=RESERVED */ + uint8_t RankMask; + uint8_t ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ + uint8_t ChanWidth; /* 1=x16, others=RESERVED */ /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ - UINT8 AddrMode; + uint8_t AddrMode; /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ - UINT8 SrInt; - UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */ + uint8_t SrInt; + uint8_t SrTemp; /* 0=normal, 1=extended, others=RESERVED */ /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver * impedance control. */ - UINT8 DramRonVal; - UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ - UINT8 DramRttWrVal; /* 0=off others=RESERVED */ + uint8_t DramRonVal; + uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ + uint8_t DramRttWrVal; /* 0=off others=RESERVED */ /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ - UINT8 SocRdOdtVal; - UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ - UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ + uint8_t SocRdOdtVal; + uint8_t SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ + uint8_t SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ - UINT8 DramDensity; - UINT8 tCL; /* DRAM CAS Latency in clocks */ + uint8_t DramDensity; + uint8_t tCL; /* DRAM CAS Latency in clocks */ /* ECC scrub interval in miliseconds 1..255 (0 works as feature * disable) */ - UINT8 EccScrubInterval; + uint8_t EccScrubInterval; /* Number of 32B blocks read for ECC scrub 2..16 */ - UINT8 EccScrubBlkSize; + uint8_t EccScrubBlkSize; - UINT8 SmmTsegSize; /* SMM size in MiB */ + uint8_t SmmTsegSize; /* SMM size in MiB */ }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 118cbea..9e02915 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -63,9 +63,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) i2c_disable(regs); /* Set the slave address */ - ASSERT (count > 0); - ASSERT (segments != NULL); - ASSERT (segments->read == 0); + if (count == 0) + die("ERROR - count == 0\n"); + if (segments == NULL) + die("ERROR - segments == NULL\n"); + if (segments->read != 0) + die("ERROR - segments->read != \n"); /* Clear the start and stop detection */ status = regs->ic_clr_start_det; @@ -98,9 +101,12 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) while (count-- > 0) { buffer = segments->buf; length = segments->len; - ASSERT (buffer != NULL); - ASSERT (length >= 1); - ASSERT (segments->chip = chip); + if (buffer == NULL) + die("ERROR - buffer == NULL\n"); + if (length < 1) + die("ERROR - length < 1\n"); + if (segments->chip != chip) + die("ERROR - segments->chip != chip\n"); if (segments->read) { /* Place read commands into the FIFO */ @@ -166,7 +172,7 @@ int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) /* Finish reading the data bytes */ while (read_length > 0) { status = regs->ic_status; - *buffer++ = (UINT8)regs->ic_data_cmd; + *buffer++ = (uint8_t)regs->ic_data_cmd; read_length--; bytes_transferred++; status = regs->ic_status; diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c index 351fab7..f880443 100644 --- a/src/soc/intel/quark/memmap.c +++ b/src/soc/intel/quark/memmap.c @@ -26,7 +26,7 @@ size_t mmap_region_granularity(void) void *cbmem_top(void) { - UINT32 top_of_memory; + uint32_t top_of_memory; /* Determine the TSEG base */ top_of_memory = reg_host_bridge_unit_read(QNC_MSG_FSBIC_REG_HSMMC); diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 4f14173..7383ddd 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -26,7 +26,8 @@ static uint16_t get_gpe0_address(uint32_t reg_address) /* Get the GPE0 base address */ gpe0_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GPE0BLK); - ASSERT (gpe0_base_address >= 0x80000000); + if (gpe0_base_address < 0x80000000) + die("ERROR - gpe0_base_address < 0x80000000\n"); gpe0_base_address &= B_QNC_LPC_GPE0BLK_MASK; /* Return the GPE0 register address */ @@ -40,7 +41,8 @@ static uint32_t *get_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_1); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (uint32_t *)(gpio_base_address + reg_address); @@ -53,7 +55,8 @@ void *get_i2c_address(void) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(I2CGPIO_BDF, PCI_BASE_ADDRESS_0); gpio_base_address &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ASSERT (gpio_base_address != 0x00000000); + if (gpio_base_address == 0) + die("ERROR - gpio_base_address == 0\n"); /* Return the GPIO register address */ return (void *)gpio_base_address; @@ -65,7 +68,8 @@ static uint16_t get_legacy_gpio_address(uint32_t reg_address) /* Get the GPIO base address */ gpio_base_address = pci_read_config32(LPC_BDF, R_QNC_LPC_GBA_BASE); - ASSERT (gpio_base_address >= 0x80000000); + if (gpio_base_address < 0x80000000) + die("ERROR - gpio_base_address < 0x80000000\n"); gpio_base_address &= B_QNC_LPC_GPA_BASE_MASK; /* Return the GPIO register address */

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Update the debug levels
by Lee Leahy 01 Aug '16

01 Aug '16

Lee Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16003 -gerrit commit 2c0980e4ff406dd1651cb82ed2cb5e7b85abf786 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 31 16:49:28 2016 -0700 drivers/intel/fsp2_0: Update the debug levels Choose appropriate debug levels for the various messages in the FSP driver. Change: * BIOS_DEBUG --> BIOS_SPEW: Normal FSP driver output level, allows builder to disable FSP driver output by selecting CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 * BIOS_ERROR --> BIOS_CRIT: These errors will prevent coreboot and the payload from successfully booting TEST=Build and run on Galileo Gen2 Change-Id: Ic3352de2022e16482bf47fc953aedeef8f0c2880 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 10 +++++----- src/drivers/intel/fsp2_0/memory_init.c | 6 +++--- src/drivers/intel/fsp2_0/util.c | 6 +++--- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 9693cd2..9ecf702 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -223,7 +223,7 @@ void fsp_print_guid(const void *base) mid[0] = read16(id + 4); mid[1] = read16(id + 6); - printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + printk(BIOS_SPEW, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", big, mid[0], mid[1], id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); } @@ -234,13 +234,13 @@ void fsp_print_resource_descriptor(const void *base) res = fsp_hob_header_to_resource(base); - printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + printk(BIOS_SPEW, "Resource %s, attribute %x\n", resource_name(res->type), res->attribute_type); - printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + printk(BIOS_SPEW, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); if (!fsp_uuid_compare(res->owner_guid, empty_uuid)) { - printk(BIOS_DEBUG, "\tOwner GUID: "); + printk(BIOS_SPEW, "\tOwner GUID: "); fsp_print_guid(res->owner_guid); - printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + printk(BIOS_SPEW, " (%s)\n", uuid_name(res->owner_guid)); } } diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0677e74..9041cbf 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -144,7 +144,7 @@ static enum cb_err check_region_overlap(const struct memranges *ranges, continue; if (begin >= range_entry_end(r)) continue; - printk(BIOS_ERR, "'%s' overlaps currently running program: " + printk(BIOS_CRIT, "'%s' overlaps currently running program: " "[%p, %p)\n", description, (void *)begin, (void *)end); return CB_ERR; } @@ -270,7 +270,7 @@ static enum cb_err load_fspm_xip(struct fsp_header *hdr, base = rdev_mmap_full(rdev); if ((uintptr_t)base != hdr->image_base) { - printk(BIOS_ERR, "FSPM XIP base does not match: %p vs %p\n", + printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", (void *)(uintptr_t)hdr->image_base, base); return CB_ERR; } @@ -293,7 +293,7 @@ void fsp_memory_init(bool s3wake) struct range_entry freeranges[2]; if (cbfs_boot_locate(&file_desc, name, NULL)) { - printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); die("FSPM not available!\n"); } diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index bab0601..3fe2f9f 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -68,13 +68,13 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, membase = rdev_mmap(rdev, FSP_HDR_OFFSET, FSP_HDR_LEN); if (membase == NULL) { - printk(BIOS_ERR, "Could not mmap() FSP header.\n"); + printk(BIOS_CRIT, "Could not mmap() FSP header.\n"); return CB_ERR; } if (fsp_identify(hdr, membase) != CB_SUCCESS) { rdev_munmap(rdev, membase); - printk(BIOS_ERR, "No valid FSP header\n"); + printk(BIOS_CRIT, "No valid FSP header\n"); return CB_ERR; } @@ -85,7 +85,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, /* Check if size specified in the header matches the cbfs file size */ if (region_device_sz(rdev) < hdr->image_size) { - printk(BIOS_ERR, "Component size bigger than cbfs file.\n"); + printk(BIOS_CRIT, "Component size bigger than cbfs file.\n"); return CB_ERR; }

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coreboot-gerrit August 2016