the following patch was just integrated into master:
commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db
Author: Prabal Saha <coolstarorganization(a)gmail.com>
Date: Sat Jun 18 20:47:21 2016 -0700
intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano
Without this patch, eDP output is non-functional pre-graphics driver
regardless of payload (SeaBIOS, Tianocore) or video init method
(VBIOS, GOP driver) and once the standard Windows Intel HD graphics
driver is loaded.
Test: Boot Windows on peppy and auron_paine, install Intel HD
Graphics driver, observe functional eDP output with full video
acceleration.
Debugging method: adjust location of call to run VBIOS within
coreboot, observed that eDP output functional if the VBIOS is run
before the power optimizer lines, broken if run afterwards.
Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514
Signed-off-by: Prabal Saha <coolstarorganization(a)gmail.com>
Reviewed-on: https://review.coreboot.org/15261
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/15261 for details.
-gerrit
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16017
-gerrit
commit 801a6268d9517581ad33f02747d5cbd61d602ac0
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Mon Aug 1 19:42:27 2016 +0200
[WIP] arch/riscv: Set the stack pointer upon trap entry
I probably shouldn't hard-code the start-of-stack.
Change-Id: I52fae62bc6cf775179963720fbcfaa9e07f6a717
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
src/arch/riscv/trap_util.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 82a5629..9f04153 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -116,7 +116,14 @@ supervisor_trap_entry:
.global trap_entry
trap_entry:
csrw mscratch, sp
- 1:addi sp,sp,-320
+
+ # This will blow up horribly once we have multiple processors handling
+ # traps at the same time.
+ li sp, 0x8000fff0
+
+ # Somehow this faults.
+ ld zero, 0(sp)
+
save_tf
move a0,sp
jal trap_handler