coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: src/Kconfig: Capitalize ROM
by HAOUAS Elyes 29 Jul '16

29 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15952 -gerrit commit 7f75197651849e43402508c5076d7ed14f5f959e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Jul 29 07:31:54 2016 +0200 src/Kconfig: Capitalize ROM Change-Id: I6c090f5adcc46b4e069a156c6b506a76c0aa7cb5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 6911f93..3cb012e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1189,7 +1189,7 @@ config CBFS_SIZE default ROM_SIZE help This is the part of the ROM actually managed by CBFS. Set it to be - equal to the full rom size if that hasn't been overridden by the + equal to the full ROM size if that hasn't been overridden by the chipset or mainboard. config CREATE_BOARD_CHECKLIST

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Patch set updated for coreboot: google/reef: Add pull up 20K for LPC SERIRQ
by Kane Chen 29 Jul '16

29 Jul '16

Kane Chen (kane.chen(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15951 -gerrit commit 73a9134c0c3f698bdf02aabcaf82949458b9e3e5 Author: Kane Chen <kane.chen(a)intel.com> Date: Thu Jul 28 19:41:15 2016 +0800 google/reef: Add pull up 20K for LPC SERIRQ per hw team's check and info from EDS, this pin need to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory help to verify the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a --- src/mainboard/google/reef/gpio.h | 2 +- src/soc/intel/apollolake/lpc_lib.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 88f5cdc..1e88215 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */ diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c index 9428866..7627fea 100644 --- a/src/soc/intel/apollolake/lpc_lib.c +++ b/src/soc/intel/apollolake/lpc_lib.c @@ -46,6 +46,7 @@ static const struct lpc_mmio_range { }; static const struct pad_config lpc_gpios[] = { + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),

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Patch set updated for coreboot: src/cpu: Capitalize CPU
by HAOUAS Elyes 29 Jul '16

29 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15934 -gerrit commit 1214815bf70bbede802822df3e9d38387c60d1ab Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 18:58:27 2016 +0200 src/cpu: Capitalize CPU Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 8 ++++---- src/cpu/amd/pi/00630F01/model_15_init.c | 2 +- src/cpu/amd/pi/00660F01/model_15_init.c | 2 +- src/cpu/amd/pi/00730F01/model_16_init.c | 2 +- src/cpu/dmp/vortex86ex/biosdata_ex.S | 4 ++-- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 8 ++++---- src/cpu/intel/haswell/haswell_init.c | 2 +- src/cpu/intel/hyperthreading/intel_sibling.c | 8 ++++---- src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 4 ++-- src/cpu/intel/model_f3x/model_f3x_init.c | 4 ++-- src/cpu/intel/model_f4x/model_f4x_init.c | 4 ++-- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 4 ++-- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 16 ++++++++-------- src/cpu/x86/mp_init.c | 12 ++++++------ src/cpu/x86/sipi_vector.S | 4 ++-- src/cpu/x86/smm/smm_module_loader.c | 8 ++++---- src/cpu/x86/smm/smm_stub.S | 8 ++++---- src/cpu/x86/smm/smmrelocate.S | 4 ++-- 54 files changed, 102 insertions(+), 102 deletions(-) diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 12dab91..22a92e1 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -57,7 +57,7 @@ static void model_10_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 8fdd62c..a0b9479 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -62,7 +62,7 @@ static void model_12_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 159ea02..84ce755 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -82,7 +82,7 @@ static void model_14_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index d035f5e..525959f 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -67,7 +67,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c index 2c71d3e..0492be3 100644 --- a/src/cpu/amd/agesa/family15rl/model_15_init.c +++ b/src/cpu/amd/agesa/family15rl/model_15_init.c @@ -81,7 +81,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 77357e9..27aedaf 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -80,7 +80,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index bf7e3bf..3d3afec 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -79,7 +79,7 @@ static void model_16_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0edded2..6fefc3b 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -257,7 +257,7 @@ uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2) continue; if ((readback & 0x3f) == state || (readback & 0x3f) == state2 || (readback & 0x3f) == F10_APSTATE_RESET) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 153fb10..a41374d 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -133,7 +133,7 @@ static void model_10xxx_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..b6bad4d 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic(); vsm_end_post_smi(); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index 6638a83..cf8c2e2 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -75,7 +75,7 @@ static void disablememoryreadorder(void) wrmsr(MC_CF8F_DATA, msr); } -/* For cpu version C3. Should be the only released version */ +/* For CPU version C3. Should be the only released version */ void cpubug(void) { pcideadlock(); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index 5cda46b..335caa3 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -40,7 +40,7 @@ static void geode_lx_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic(); // do VSA late init diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 03415d1..9e6dfa0 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -401,7 +401,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) 0) continue; if (((readback >> 24) & 0xff) == apicid) - break; /* it is this cpu turn */ + break; /* it is this CPU turn */ } if (loop > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 51e1b7c..2ea4fb9 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -157,7 +157,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state) continue; if ((readback & 0xff) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { @@ -303,7 +303,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait - lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started if (apicid != bsp_apicid) { u32 timeout = 1; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index cf0b08a..e22eae4 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -249,15 +249,15 @@ static void init_ecc_memory(unsigned node_id) f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); if (!f1_dev) { - die("Cannot find cpu function 1\n"); + die("Cannot find CPU function 1\n"); } f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2)); if (!f2_dev) { - die("Cannot find cpu function 2\n"); + die("Cannot find CPU function 2\n"); } f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3)); if (!f3_dev) { - die("Cannot find cpu function 3\n"); + die("Cannot find CPU function 3\n"); } /* See if we scrubbing should be enabled */ @@ -508,7 +508,7 @@ static void model_fxx_init(device_t dev) /* Set the processor name string */ init_processor_name(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 42afae3..7c4d171 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -79,7 +79,7 @@ static void model_15_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 8fe6340..de7ee38 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -94,7 +94,7 @@ static void model_15_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 00a21e9..6cb3009 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -77,7 +77,7 @@ static void model_16_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S index 5ed17c6..2defe63 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.S +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -24,8 +24,8 @@ DDR3 CPU/DRAM/PCI B6 B7 BB BC BD BF 200/200/33 30 03 0F 02 8F 07 300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable +300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable 300/300/100 48 03 23 02 7F 07 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing 400/200/100 60 43 23 02 4F 07 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index bd39039..536b40e 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other CPU files are included. # # Therefore: ONLY include Makefile.inc from socket directories! diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 05c5bb1..3093975 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -34,7 +34,7 @@ static void ep80579_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index da1ea2b..1d4ae58 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -334,7 +334,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -343,7 +343,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -353,7 +353,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -386,7 +386,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 17c46b3..badadf1 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -133,7 +133,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -142,7 +142,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -152,7 +152,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -182,7 +182,7 @@ static void model_406dx_init(struct device *cpu) x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 74147ab..799b66c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -720,7 +720,7 @@ static void haswell_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 678ad2d..de59c18 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -21,7 +21,7 @@ #include <assert.h> #if CONFIG_PARALLEL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init +#error Intel hyper-threading requires serialized CPU init #endif static int first_time = 1; @@ -84,16 +84,16 @@ void intel_sibling_init(struct device *cpu) return; } - /* I am the primary cpu start up my siblings */ + /* I am the primary CPU start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - /* Allocate new cpu device structure iff sibling CPU + /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ new = alloc_find_dev(cpu->bus, &cpu_path); diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 7452973..f589430 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,5 @@ ################################################################################ -## One small file with the awesome super-power of updating the cpu microcode +## One small file with the awesome super-power of updating the CPU microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0242a44..1812084 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -322,7 +322,7 @@ static void model_1067x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Initialize the APIC timer */ @@ -347,7 +347,7 @@ static void model_1067x_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(tm2, quad); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 82552d8..ac4606b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -124,7 +124,7 @@ static void model_106cx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -138,7 +138,7 @@ static void model_106cx_init(struct device *cpu) /* TODO: PIC thermal sensor control */ - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 4005b3d..6bd20ba 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -329,13 +329,13 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + (i % threads_per_core) + ((i / threads_per_core) << 2); - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -345,7 +345,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -379,7 +379,7 @@ static void model_2065x_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7575603..a2cbfbf 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -520,7 +520,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -529,7 +529,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -539,7 +539,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start the new CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -572,7 +572,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 3cce098..14da632 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -36,7 +36,7 @@ static void model_65x_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 631e3515..d7c22fc 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -40,7 +40,7 @@ static void model_67x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3adee6f..e276791 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -44,7 +44,7 @@ static void model_68x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 214673a..d283722 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -18,7 +18,7 @@ static void model_69x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b2e5585..36da288 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -44,7 +44,7 @@ static void model_6bx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 04b73ad..73f71d8 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -31,7 +31,7 @@ static void model_6dx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6fa6d3a..bc926a8 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -154,7 +154,7 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -169,7 +169,7 @@ static void model_6ex_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 6cd2b12..30542e6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -177,7 +177,7 @@ static void model_6fx_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -192,7 +192,7 @@ static void model_6fx_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 0f0df22..102af74 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -31,7 +31,7 @@ static void model_6xx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index 94c73ce..1eb234f 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -31,7 +31,7 @@ static void model_f0x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index 259d7f6..77f442f 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -31,7 +31,7 @@ static void model_f1x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 6b847c0..092afa0 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -36,10 +36,10 @@ static void model_f2x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index e85427d..36ca5a6 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -36,10 +36,10 @@ static void model_f3x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 6211209..7d198b3 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -36,10 +36,10 @@ static void model_f4x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 66cfbca..c28766e 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -27,7 +27,7 @@ static void c3_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 9b558e9..e7c9fac 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -200,7 +200,7 @@ static void c7_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; @@ -209,7 +209,7 @@ static struct device_operations cpu_dev_ops = { }; /* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact - * ID, the cpu mask (stepping) is masked out and the check is repeated. This + * ID, the CPU mask (stepping) is masked out and the check is repeated. This * allows us to keep the table significantly smaller. */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index fdd8b7e..cdf0589 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -180,7 +180,7 @@ static void nano_init(struct device *dev) /* Set up Memory Type Range Registers */ x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index be5b730..4c0d323 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -54,7 +54,7 @@ _start16bit: * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. - * If you cpu needs it you can write a cpu dependent version of + * If you CPU needs it you can write a CPU dependent version of * entry16.inc. */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 77e5ba8..e35f5fd 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -242,10 +242,10 @@ static int lapic_start_cpu(unsigned long apicid) static atomic_t active_cpus = ATOMIC_INIT(1); /* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic + * Only starting one CPU at a time let's me remove the logic * for select the stack from assembly language. * - * In addition communicating by variables to the cpu I + * In addition communicating by variables to the CPU I * am starting allows me to verify it has started before * start_cpu returns. */ @@ -301,12 +301,12 @@ int start_cpu(struct device *cpu) cpu->enabled = 0; cpu->initialized = 0; - /* Start the cpu */ + /* Start the CPU */ result = lapic_start_cpu(apicid); if (result) { result = 0; - /* Wait 1s or until the new cpu calls in */ + /* Wait 1s or until the new CPU calls in */ for(count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; @@ -542,23 +542,23 @@ void initialize_cpus(struct bus *cpu_bus) struct device_path cpu_path; struct cpu_info *info; - /* Find the info struct for this cpu */ + /* Find the info struct for this CPU */ info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ enable_lapic(); - /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else - /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ + /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index b9084c7..ff32015 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -375,7 +375,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) struct device *new; int apic_id; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; /* Assuming linear APIC space allocation. */ @@ -385,10 +385,10 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) } cpu_path.apic.apic_id = apic_id; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); if (new == NULL) { - printk(BIOS_CRIT, "Could not allocate cpu device\n"); + printk(BIOS_CRIT, "Could not allocate CPU device\n"); max_cpus--; } cpus[i].dev = new; @@ -577,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) * * The MP initialization has the following properties: * 1. APs are brought up in parallel. - * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. + * 2. The ordering of coreboot CPU number and APIC ids is not deterministic. * Therefore, one cannot rely on this property or the order of devices in * the device tree unless the chipset or mainboard know the APIC ids * a priori. @@ -641,7 +641,7 @@ static void mp_initialize_cpu(void) cpu_initialize(info->index); } -/* Returns apic id for coreboot cpu number or < 0 on failure. */ +/* Returns apic id for coreboot CPU number or < 0 on failure. */ static int mp_get_apic_id(int cpu_slot) { if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0) @@ -843,7 +843,7 @@ static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(NULL, load_smm_handlers), /* Perform SMM relocation. */ MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), - /* Initialize each cpu through the driver framework. */ + /* Initialize each CPU through the driver framework. */ MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish everything else then let them park. */ MP_FR_BLOCK_APS(NULL, NULL), diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 985b9da..2bcce88 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -93,7 +93,7 @@ _start: mov idt_ptr, %ebx lidt (%ebx) - /* Obtain cpu number. */ + /* Obtain CPU number. */ movl ap_count, %eax 1: movl %eax, %ecx @@ -107,7 +107,7 @@ _start: movl stack_top, %edx subl %eax, %edx mov %edx, %esp - /* Save cpu number. */ + /* Save CPU number. */ mov %ecx, %esi /* Determine if one should check microcode versions. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 853923d..09ddb03 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -48,7 +48,7 @@ extern unsigned char _binary_smmstub_start[]; /* This is the SMM handler that the stub calls. It is encoded as an rmodule. */ extern unsigned char _binary_smm_start[]; -/* Per cpu minimum stack size. */ +/* Per CPU minimum stack size. */ #define SMM_MINIMUM_STACK_SIZE 32 /* @@ -75,7 +75,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, struct smm_entry_ins entry = { .jmp_rel = 0xe9 }; /* Each entry point has an IP value of 0x8000. The SMBASE for each - * cpu is different so the effective address of the entry instruction + * CPU is different so the effective address of the entry instruction * is different. Therefore, the relative displacement for each entry * instruction needs to be updated to reflect the current effective * IP. Additionally, the IP result from the jmp instruction is @@ -126,7 +126,7 @@ static void *smm_stub_place_stacks(char *base, int size, } /* Place the staggered entry points for each CPU. The entry points are - * staggered by the per cpu SMM save state size extending down from + * staggered by the per CPU SMM save state size extending down from * SMM_ENTRY_OFFSET. */ static void smm_stub_place_staggered_entry_points(char *base, const struct smm_loader_params *params, const struct rmodule *smm_stub) @@ -260,7 +260,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) stub_params->runtime.smbase = (u32)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; - /* Initialize the APIC id to cpu number table to be 1:1 */ + /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) stub_params->runtime.apic_id_to_cpu[i] = i; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 564b200..d1fe7c1 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -40,15 +40,15 @@ smbase: .long 0 save_state_size: .long 0 -/* apic_to_cpu_num is a table mapping the default APIC id to cpu num. If the - * APIC id is found at the given index, the contiguous cpu number is index +/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the + * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ apic_to_cpu_num: .fill CONFIG_MAX_CPUS,1,0xff /* end struct smm_runtime */ .data -/* Provide fallback stack to use when a valid cpu number cannot be found. */ +/* Provide fallback stack to use when a valid CPU number cannot be found. */ fallback_stack_bottom: .skip 128 fallback_stack_top: @@ -112,7 +112,7 @@ smm_trampoline32: inc %ecx cmp $CONFIG_MAX_CPUS, %ecx jne 1b - /* This is bad. One cannot find a stack entry because a cpu num could + /* This is bad. One cannot find a stack entry because a CPU num could * not be assigned. Use the fallback stack and check this condition in * C handler. */ movl $(fallback_stack_top), %esp diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 128b694..2502df8 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -89,7 +89,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 CPU cores before * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. @@ -167,7 +167,7 @@ smm_relocate: outb %al, %dx movb $'-', %al outb %al, %dx - /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ + /* calculate ascii of CPU number. More than 9 cores? -> FIXME */ movb %cl, %al addb $'0', %al outb %al, %dx

1 0

Patch set updated for coreboot: chromeos mainboards: remove chromeos.asl
by Aaron Durbin 29 Jul '16

29 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15909 -gerrit commit 9e3b5f2ea4bb4f7dda2afc178680ed0439f85f3a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jul 25 21:31:41 2016 -0500 chromeos mainboards: remove chromeos.asl Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/auron/acpi/chromeos.asl | 19 ------ src/mainboard/google/auron/chromeos.c | 10 +++ src/mainboard/google/auron/dsdt.asl | 1 - src/mainboard/google/auron/mainboard.c | 2 + src/mainboard/google/auron_paine/acpi/chromeos.asl | 19 ------ src/mainboard/google/auron_paine/chromeos.c | 10 +++ src/mainboard/google/auron_paine/dsdt.asl | 1 - src/mainboard/google/auron_paine/mainboard.c | 2 + src/mainboard/google/butterfly/acpi/chromeos.asl | 20 ------ src/mainboard/google/butterfly/chromeos.c | 12 ++++ src/mainboard/google/butterfly/dsdt.asl | 1 - src/mainboard/google/butterfly/mainboard.c | 2 + src/mainboard/google/chell/acpi/chromeos.asl | 23 ------- src/mainboard/google/chell/chromeos.c | 10 +++ src/mainboard/google/chell/dsdt.asl | 1 - src/mainboard/google/chell/mainboard.c | 2 + src/mainboard/google/cyan/acpi/chromeos.asl | 33 ---------- src/mainboard/google/cyan/chromeos.c | 10 +++ src/mainboard/google/cyan/dsdt.asl | 1 - src/mainboard/google/cyan/mainboard.c | 2 + src/mainboard/google/falco/acpi/chromeos.asl | 19 ------ src/mainboard/google/falco/chromeos.c | 11 ++++ src/mainboard/google/falco/dsdt.asl | 1 - src/mainboard/google/falco/mainboard.c | 2 + src/mainboard/google/glados/acpi/chromeos.asl | 23 ------- src/mainboard/google/glados/chromeos.c | 10 +++ src/mainboard/google/glados/dsdt.asl | 1 - src/mainboard/google/glados/mainboard.c | 2 + src/mainboard/google/guado/acpi/chromeos.asl | 19 ------ src/mainboard/google/guado/chromeos.c | 10 +++ src/mainboard/google/guado/dsdt.asl | 1 - src/mainboard/google/guado/mainboard.c | 2 + src/mainboard/google/jecht/acpi/chromeos.asl | 19 ------ src/mainboard/google/jecht/chromeos.c | 10 +++ src/mainboard/google/jecht/dsdt.asl | 1 - src/mainboard/google/jecht/mainboard.c | 2 + src/mainboard/google/lars/acpi/chromeos.asl | 24 -------- src/mainboard/google/lars/chromeos.c | 10 +++ src/mainboard/google/lars/dsdt.asl | 1 - src/mainboard/google/lars/mainboard.c | 2 + src/mainboard/google/link/acpi/chromeos.asl | 19 ------ src/mainboard/google/link/chromeos.c | 11 ++++ src/mainboard/google/link/dsdt.asl | 1 - src/mainboard/google/link/mainboard.c | 2 + src/mainboard/google/ninja/acpi/chromeos.asl | 31 ---------- src/mainboard/google/ninja/chromeos.c | 12 +++- src/mainboard/google/ninja/dsdt.asl | 1 - src/mainboard/google/ninja/mainboard.c | 2 + src/mainboard/google/panther/acpi/chromeos.asl | 19 ------ src/mainboard/google/panther/chromeos.c | 10 +++ src/mainboard/google/panther/dsdt.asl | 1 - src/mainboard/google/panther/mainboard.c | 2 + src/mainboard/google/parrot/acpi/chromeos.asl | 20 ------ src/mainboard/google/parrot/chromeos.c | 12 ++++ src/mainboard/google/parrot/dsdt.asl | 1 - src/mainboard/google/parrot/mainboard.c | 2 + src/mainboard/google/peppy/acpi/chromeos.asl | 19 ------ src/mainboard/google/peppy/chromeos.c | 11 ++++ src/mainboard/google/peppy/dsdt.asl | 1 - src/mainboard/google/peppy/mainboard.c | 2 + src/mainboard/google/rambi/acpi/chromeos.asl | 32 ---------- src/mainboard/google/rambi/chromeos.c | 11 ++++ src/mainboard/google/rambi/dsdt.asl | 1 - src/mainboard/google/rambi/mainboard.c | 2 + src/mainboard/google/reef/acpi/chromeos.asl | 23 ------- src/mainboard/google/reef/chromeos.c | 11 ++++ src/mainboard/google/reef/dsdt.asl | 1 - src/mainboard/google/reef/mainboard.c | 2 + src/mainboard/google/rikku/acpi/chromeos.asl | 19 ------ src/mainboard/google/rikku/chromeos.c | 10 +++ src/mainboard/google/rikku/dsdt.asl | 1 - src/mainboard/google/rikku/mainboard.c | 2 + src/mainboard/google/samus/acpi/chromeos.asl | 19 ------ src/mainboard/google/samus/chromeos.c | 10 +++ src/mainboard/google/samus/dsdt.asl | 1 - src/mainboard/google/samus/mainboard.c | 2 + src/mainboard/google/stout/acpi/chromeos.asl | 22 ------- src/mainboard/google/stout/chromeos.c | 12 ++++ src/mainboard/google/stout/dsdt.asl | 1 - src/mainboard/google/stout/mainboard.c | 2 + src/mainboard/google/tidus/acpi/chromeos.asl | 19 ------ src/mainboard/google/tidus/chromeos.c | 10 +++ src/mainboard/google/tidus/dsdt.asl | 1 - src/mainboard/google/tidus/mainboard.c | 2 + src/mainboard/intel/amenia/acpi/chromeos.asl | 24 -------- src/mainboard/intel/amenia/chromeos.c | 11 ++++ src/mainboard/intel/amenia/dsdt.asl | 3 - src/mainboard/intel/baskingridge/acpi/chromeos.asl | 20 ------ src/mainboard/intel/baskingridge/chromeos.c | 12 ++++ src/mainboard/intel/baskingridge/dsdt.asl | 1 - src/mainboard/intel/baskingridge/mainboard.c | 4 +- src/mainboard/intel/emeraldlake2/acpi/chromeos.asl | 20 ------ src/mainboard/intel/emeraldlake2/chromeos.c | 12 ++++ src/mainboard/intel/emeraldlake2/dsdt.asl | 1 - src/mainboard/intel/emeraldlake2/mainboard.c | 2 + src/mainboard/intel/kunimitsu/acpi/chromeos.asl | 24 -------- src/mainboard/intel/kunimitsu/chromeos.c | 10 +++ src/mainboard/intel/kunimitsu/dsdt.asl | 1 - src/mainboard/intel/kunimitsu/mainboard.c | 2 + src/mainboard/intel/strago/acpi/chromeos.asl | 33 ---------- src/mainboard/intel/strago/chromeos.c | 10 +++ src/mainboard/intel/strago/dsdt.asl | 1 - src/mainboard/intel/strago/mainboard.c | 2 + src/mainboard/intel/wtm2/acpi/chromeos.asl | 20 ------ src/mainboard/intel/wtm2/chromeos.c | 12 ++++ src/mainboard/intel/wtm2/dsdt.asl | 1 - src/mainboard/intel/wtm2/mainboard.c | 2 + src/mainboard/samsung/lumpy/acpi/chromeos.asl | 20 ------ src/mainboard/samsung/lumpy/chromeos.c | 12 ++++ src/mainboard/samsung/lumpy/dsdt.asl | 1 - src/mainboard/samsung/lumpy/mainboard.c | 2 + src/mainboard/samsung/stumpy/acpi/chromeos.asl | 20 ------ src/mainboard/samsung/stumpy/chromeos.c | 12 ++++ src/mainboard/samsung/stumpy/dsdt.asl | 1 - src/mainboard/samsung/stumpy/mainboard.c | 2 + src/soc/intel/apollolake/include/soc/gpio_defs.h | 6 ++ src/soc/intel/baytrail/include/soc/gpio.h | 2 + src/soc/intel/braswell/include/soc/gpio.h | 2 + src/soc/intel/broadwell/include/soc/gpio.h | 3 + src/soc/intel/skylake/include/soc/gpio.h | 2 + src/southbridge/intel/bd82x6x/pch.h | 6 ++ src/southbridge/intel/lynxpoint/pch.h | 2 + src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/acpi.c | 43 +++++++++++++ src/vendorcode/google/chromeos/acpi/chromeos.asl | 6 ++ src/vendorcode/google/chromeos/chromeos.h | 72 ++++++++++++++++++++++ 126 files changed, 514 insertions(+), 675 deletions(-) diff --git a/src/mainboard/google/auron/acpi/chromeos.asl b/src/mainboard/google/auron/acpi/chromeos.asl deleted file mode 100644 index 85b4415..0000000 --- a/src/mainboard/google/auron/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 4447ddc..20685c6 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 58c3481..531d6a7 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/auron/mainboard.c b/src/mainboard/google/auron/mainboard.c index 7b67cc0..188c16d 100644 --- a/src/mainboard/google/auron/mainboard.c +++ b/src/mainboard/google/auron/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -88,6 +89,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/auron_paine/acpi/chromeos.asl b/src/mainboard/google/auron_paine/acpi/chromeos.asl deleted file mode 100644 index 85b4415..0000000 --- a/src/mainboard/google/auron_paine/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c index 4447ddc..20685c6 100644 --- a/src/mainboard/google/auron_paine/chromeos.c +++ b/src/mainboard/google/auron_paine/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/auron_paine/dsdt.asl b/src/mainboard/google/auron_paine/dsdt.asl index 58c3481..531d6a7 100644 --- a/src/mainboard/google/auron_paine/dsdt.asl +++ b/src/mainboard/google/auron_paine/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/auron_paine/mainboard.c b/src/mainboard/google/auron_paine/mainboard.c index a73a4bd..81ca9cf 100644 --- a/src/mainboard/google/auron_paine/mainboard.c +++ b/src/mainboard/google/auron_paine/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -61,6 +62,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/butterfly/acpi/chromeos.asl b/src/mainboard/google/butterfly/acpi/chromeos.asl deleted file mode 100644 index a6cf28e..0000000 --- a/src/mainboard/google/butterfly/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 69887f5..b25d78e 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -23,6 +23,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/quanta/ene_kb3940q/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #define WP_GPIO 6 @@ -136,3 +137,14 @@ int get_recovery_mode_switch(void) return ec_rec_mode; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index ac005d8..2c5170d 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -34,6 +34,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/quanta/ene_kb3940q/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> static unsigned int search(char *p, char *a, unsigned int lengthp, unsigned int lengtha) @@ -276,6 +277,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/chell/acpi/chromeos.asl b/src/mainboard/google/chell/acpi/chromeos.asl deleted file mode 100644 index 90b1a4f..0000000 --- a/src/mainboard/google/chell/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index f0b3613..3ca1872 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/chell/dsdt.asl b/src/mainboard/google/chell/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/chell/dsdt.asl +++ b/src/mainboard/google/chell/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/chell/mainboard.c b/src/mainboard/google/chell/mainboard.c index 6033e21..bfa79b4 100644 --- a/src/mainboard/google/chell/mainboard.c +++ b/src/mainboard/google/chell/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl deleted file mode 100644 index 0bb7985..0000000 --- a/src/mainboard/google/cyan/acpi/chromeos.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: We need to encode gpios within the 4 separate banks - * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. - */ - -Name(OIPG, Package() { - /* No physical recovery button */ - Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10013, "Braswell" }, -}) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 757db5f..f606d09 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -123,3 +123,13 @@ int get_write_protect_state(void) return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) & PAD_VAL_HIGH); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl index b3c970d..cb6d91a 100644 --- a/src/mainboard/google/cyan/dsdt.asl +++ b/src/mainboard/google/cyan/dsdt.asl @@ -53,7 +53,6 @@ DefinitionBlock( #include <soc/intel/common/acpi/wifi.asl> } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c index 0566c8e..71ba62b 100644 --- a/src/mainboard/google/cyan/mainboard.c +++ b/src/mainboard/google/cyan/mainboard.c @@ -18,6 +18,7 @@ #include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -32,6 +33,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/google/falco/acpi/chromeos.asl b/src/mainboard/google/falco/acpi/chromeos.asl deleted file mode 100644 index 673985f..0000000 --- a/src/mainboard/google/falco/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c index 1659d9c..a8cef32 100644 --- a/src/mainboard/google/falco/chromeos.c +++ b/src/mainboard/google/falco/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -86,3 +87,13 @@ int get_write_protect_state(void) { return get_gpio(58); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl index 1020ae7..f4a4627 100644 --- a/src/mainboard/google/falco/dsdt.asl +++ b/src/mainboard/google/falco/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index b9ce50e..10252d8 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -29,6 +29,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/glados/acpi/chromeos.asl b/src/mainboard/google/glados/acpi/chromeos.asl deleted file mode 100644 index 90b1a4f..0000000 --- a/src/mainboard/google/glados/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index f0b3613..3ca1872 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/glados/dsdt.asl b/src/mainboard/google/glados/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/glados/dsdt.asl +++ b/src/mainboard/google/glados/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index d387fef..855d69d 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -73,6 +74,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/guado/acpi/chromeos.asl b/src/mainboard/google/guado/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/guado/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c index 13fbfc3..710ab48 100644 --- a/src/mainboard/google/guado/chromeos.c +++ b/src/mainboard/google/guado/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/guado/dsdt.asl b/src/mainboard/google/guado/dsdt.asl index e078694..c3d1fc9 100644 --- a/src/mainboard/google/guado/dsdt.asl +++ b/src/mainboard/google/guado/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/guado/mainboard.c b/src/mainboard/google/guado/mainboard.c index 3287a7e..1d65829 100644 --- a/src/mainboard/google/guado/mainboard.c +++ b/src/mainboard/google/guado/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/jecht/acpi/chromeos.asl b/src/mainboard/google/jecht/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/jecht/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index cc19666..c22f942 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -94,3 +94,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index b434727..3132aab 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/jecht/mainboard.c b/src/mainboard/google/jecht/mainboard.c index 58c0190..cb17797 100644 --- a/src/mainboard/google/jecht/mainboard.c +++ b/src/mainboard/google/jecht/mainboard.c @@ -30,6 +30,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -135,6 +136,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/lars/acpi/chromeos.asl b/src/mainboard/google/lars/acpi/chromeos.asl deleted file mode 100644 index 4fc5f22..0000000 --- a/src/mainboard/google/lars/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 1e0bd3c..daa85c6 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/lars/dsdt.asl b/src/mainboard/google/lars/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/google/lars/dsdt.asl +++ b/src/mainboard/google/lars/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/lars/mainboard.c b/src/mainboard/google/lars/mainboard.c index 6725f13..e044405 100644 --- a/src/mainboard/google/lars/mainboard.c +++ b/src/mainboard/google/lars/mainboard.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <stdlib.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/link/acpi/chromeos.asl b/src/mainboard/google/link/acpi/chromeos.asl deleted file mode 100644 index eec650a..0000000 --- a/src/mainboard/google/link/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button - Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index d07e851..4be31d9 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -22,6 +22,7 @@ #include <southbridge/intel/common/gpio.h> #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -107,3 +108,13 @@ int get_recovery_mode_switch(void) return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index be6a412..da4587d 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index 922061f..53915d2 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -36,6 +36,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> /* placeholder for evenual link post. Not sure what we'll * do but it will look nice @@ -199,6 +200,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/ninja/acpi/chromeos.asl b/src/mainboard/google/ninja/acpi/chromeos.asl deleted file mode 100644 index 814380c..0000000 --- a/src/mainboard/google/ninja/acpi/chromeos.asl +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: On Bay Trail we need to encode gpios within the 3 separate banks - * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded - * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery - Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect -}) diff --git a/src/mainboard/google/ninja/chromeos.c b/src/mainboard/google/ninja/chromeos.c index baafb6f..1213266 100644 --- a/src/mainboard/google/ninja/chromeos.c +++ b/src/mainboard/google/ninja/chromeos.c @@ -100,4 +100,14 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); -} \ No newline at end of file +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/ninja/dsdt.asl b/src/mainboard/google/ninja/dsdt.asl index 6475e1c..a37756f 100644 --- a/src/mainboard/google/ninja/dsdt.asl +++ b/src/mainboard/google/ninja/dsdt.asl @@ -44,7 +44,6 @@ DefinitionBlock( #include "acpi/dptf.asl" } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/ninja/mainboard.c b/src/mainboard/google/ninja/mainboard.c index a5d171e..df9ecfa 100644 --- a/src/mainboard/google/ninja/mainboard.c +++ b/src/mainboard/google/ninja/mainboard.c @@ -34,6 +34,7 @@ #include "onboard.h" #include <soc/gpio.h> #include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -144,6 +145,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/panther/acpi/chromeos.asl b/src/mainboard/google/panther/acpi/chromeos.asl deleted file mode 100644 index d77a79e..0000000 --- a/src/mainboard/google/panther/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "LynxPoint" }, // recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 014bb7e..4ee6810 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -92,3 +92,13 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/panther/dsdt.asl b/src/mainboard/google/panther/dsdt.asl index 6fdb48b..66cc041 100644 --- a/src/mainboard/google/panther/dsdt.asl +++ b/src/mainboard/google/panther/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 68932cf..661e507 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -29,6 +29,7 @@ #include <pc80/mc146818rtc.h> #include <southbridge/intel/lynxpoint/pch.h> #include <drivers/intel/gma/int15.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" @@ -51,6 +52,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/parrot/acpi/chromeos.asl b/src/mainboard/google/parrot/acpi/chromeos.asl deleted file mode 100644 index b754183..0000000 --- a/src/mainboard/google/parrot/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index c898f0e..4dcbfa5 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -23,6 +23,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <ec/compal/ene932/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" @@ -122,3 +123,14 @@ int parrot_ec_running_ro(void) { return !get_gpio(68); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index a2b7169..4d357f8 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -32,6 +32,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/compal/ene932/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -81,6 +82,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/peppy/acpi/chromeos.asl b/src/mainboard/google/peppy/acpi/chromeos.asl deleted file mode 100644 index 673985f..0000000 --- a/src/mainboard/google/peppy/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button - Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c index 1659d9c..a8cef32 100644 --- a/src/mainboard/google/peppy/chromeos.c +++ b/src/mainboard/google/peppy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -86,3 +87,13 @@ int get_write_protect_state(void) { return get_gpio(58); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl index 9e5a114..83305ab 100644 --- a/src/mainboard/google/peppy/dsdt.asl +++ b/src/mainboard/google/peppy/dsdt.asl @@ -52,7 +52,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index b9ce50e..10252d8 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -29,6 +29,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "onboard.h" @@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl deleted file mode 100644 index 3072eca..0000000 --- a/src/mainboard/google/rambi/acpi/chromeos.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: On Bay Trail we need to encode gpios within the 3 separate banks - * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded - * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. - */ - -Name(OIPG, Package() { - // No physical recovery button - Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" }, - Package () { 0x0003, 1, 0x2006, "BayTrail" }, -}) diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 1006484..4304179 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <soc/gpio.h> #include <vboot/vboot_common.h> +#include <vendorcode/google/chromeos/chromeos.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include "ec.h" @@ -111,3 +112,13 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 6475e1c..a37756f 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -44,7 +44,6 @@ DefinitionBlock( #include "acpi/dptf.asl" } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 29cebb1..adbfd96 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -34,6 +34,7 @@ #include "onboard.h" #include <soc/gpio.h> #include <bootstate.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -163,6 +164,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/reef/acpi/chromeos.asl b/src/mainboard/google/reef/acpi/chromeos.asl deleted file mode 100644 index bec6bcb..0000000 --- a/src/mainboard/google/reef/acpi/chromeos.asl +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio_defs.h> - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" }, -}) diff --git a/src/mainboard/google/reef/chromeos.c b/src/mainboard/google/reef/chromeos.c index 4de6a70..5c526dc 100644 --- a/src/mainboard/google/reef/chromeos.c +++ b/src/mainboard/google/reef/chromeos.c @@ -19,6 +19,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/gpio.h> #include "ec.h" +#include "gpio.h" #define GPIO_PCH_WP GPIO_75 #define GPIO_EC_IN_RW GPIO_41 @@ -69,3 +70,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 7a88fb6..6243c72 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -38,7 +38,6 @@ DefinitionBlock( } /* Chrome OS specific */ - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index def6900..0c4ba8d 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -20,6 +20,7 @@ #include <nhlt.h> #include <soc/gpio.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -83,6 +84,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/rikku/acpi/chromeos.asl b/src/mainboard/google/rikku/acpi/chromeos.asl deleted file mode 100644 index bad5f47..0000000 --- a/src/mainboard/google/rikku/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c index d440968..b007484 100644 --- a/src/mainboard/google/rikku/chromeos.c +++ b/src/mainboard/google/rikku/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl index 663b3c5..edb04f0 100644 --- a/src/mainboard/google/rikku/dsdt.asl +++ b/src/mainboard/google/rikku/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c index 16fe630..e3eaf4e 100644 --- a/src/mainboard/google/rikku/mainboard.c +++ b/src/mainboard/google/rikku/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/samus/acpi/chromeos.asl b/src/mainboard/google/samus/acpi/chromeos.asl deleted file mode 100644 index 604cd7d..0000000 --- a/src/mainboard/google/samus/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect -}) diff --git a/src/mainboard/google/samus/chromeos.c b/src/mainboard/google/samus/chromeos.c index 51f2f2e..7010ac9 100644 --- a/src/mainboard/google/samus/chromeos.c +++ b/src/mainboard/google/samus/chromeos.c @@ -93,3 +93,13 @@ int get_write_protect_state(void) { return get_gpio(CROS_WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/samus/dsdt.asl b/src/mainboard/google/samus/dsdt.asl index 34071b1..02e6363 100644 --- a/src/mainboard/google/samus/dsdt.asl +++ b/src/mainboard/google/samus/dsdt.asl @@ -47,7 +47,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 54c6283..9fa9c57 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -28,6 +28,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "board_version.h" #include "ec.h" @@ -51,6 +52,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/stout/acpi/chromeos.asl b/src/mainboard/google/stout/acpi/chromeos.asl deleted file mode 100644 index ddabdc8..0000000 --- a/src/mainboard/google/stout/acpi/chromeos.asl +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - // No GPIO for recovery mode, developer mode, or firmware write protect - // on stout - note: all virtual pins are active HIGH polarity on stout. - Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button - Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button - Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect -}) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 4c7a9f5..cbb9574 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -22,6 +22,7 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include <ec/quanta/it8518/ec.h> @@ -133,3 +134,14 @@ int get_recovery_mode_switch(void) return ec_in_rec_mode; #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 723cc71..3a822ed 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 2581310..4e3839f 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -32,6 +32,7 @@ #include <smbios.h> #include <device/pci.h> #include <ec/quanta/it8518/ec.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -66,6 +67,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/tidus/acpi/chromeos.asl b/src/mainboard/google/tidus/acpi/chromeos.asl deleted file mode 100644 index 492ee6b..0000000 --- a/src/mainboard/google/tidus/acpi/chromeos.asl +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button - Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/google/tidus/chromeos.c b/src/mainboard/google/tidus/chromeos.c index 13fbfc3..710ab48 100644 --- a/src/mainboard/google/tidus/chromeos.c +++ b/src/mainboard/google/tidus/chromeos.c @@ -93,3 +93,13 @@ void save_chromeos_gpios(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); } #endif + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/google/tidus/dsdt.asl b/src/mainboard/google/tidus/dsdt.asl index e078694..c3d1fc9 100644 --- a/src/mainboard/google/tidus/dsdt.asl +++ b/src/mainboard/google/tidus/dsdt.asl @@ -46,7 +46,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/google/tidus/mainboard.c b/src/mainboard/google/tidus/mainboard.c index 3287a7e..1d65829 100644 --- a/src/mainboard/google/tidus/mainboard.c +++ b/src/mainboard/google/tidus/mainboard.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" void mainboard_suspend_resume(void) @@ -35,6 +36,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/amenia/acpi/chromeos.asl b/src/mainboard/intel/amenia/acpi/chromeos.asl deleted file mode 100644 index 31d0afc..0000000 --- a/src/mainboard/intel/amenia/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio_defs.h> - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" }, -}) diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c index b6669bf..4cfc2a6 100644 --- a/src/mainboard/intel/amenia/chromeos.c +++ b/src/mainboard/intel/amenia/chromeos.c @@ -18,6 +18,7 @@ #include "ec.h" #include <ec/google/chromeec/ec.h> +#include <soc/gpio_defs.h> #include <vendorcode/google/chromeos/chromeos.h> int get_lid_switch(void) @@ -48,3 +49,13 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME), + CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 7602b1e..9314469 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -39,10 +39,7 @@ DefinitionBlock( } } - #if IS_ENABLED(CONFIG_CHROMEOS) - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> - #endif /* Mainboard Specific devices */ #include "acpi/mainboard.asl" diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl deleted file mode 100644 index 9c49265..0000000 --- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery - Package () { 0x0002, 0, 48, "LynxPoint" }, // developer - Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect -}) diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 94e8d89..1666fc5 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -102,3 +103,14 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 5cd0ffb..e4b489c 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -48,7 +48,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 4c7baca..dbf3574 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -28,6 +28,7 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -35,13 +36,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } - - // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl deleted file mode 100644 index 9f2e54a..0000000 --- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch - Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index bb4ebe9..896f876 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -91,3 +92,14 @@ int get_recovery_mode_switch(void) /* Recovery: GPIO22, active low */ return !get_gpio(22); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index 8d9e281..a31c415 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index a0fd9e8..654b1de 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -28,12 +28,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl deleted file mode 100644 index 4fc5f22..0000000 --- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "../gpio.h" - -Name (OIPG, Package () { - /* No physical recovery GPIO. */ - Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, - /* Firmware write protect GPIO. */ - Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, -}) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 1e0bd3c..daa85c6 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -82,3 +82,13 @@ int get_write_protect_state(void) /* Read PCH_WP GPIO. */ return gpio_get(GPIO_PCH_WP); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index c9e13e7..b5a37c6 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -45,7 +45,6 @@ DefinitionBlock( } // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index d634fac..9f79db6 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <string.h> #include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" #include "gpio.h" @@ -99,6 +100,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl deleted file mode 100644 index c470ca3..0000000 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Fields are in the following order. - * - Type: recovery = 1 developer mode = 2 write protect = 3 - * - Active Level - if -1 not a valid gpio - * - GPIO number encoding - if -1 not a valid gpio - * - Chipset Name - * - * Note: We need to encode gpios within the 4 separate banks - * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. - */ - -Name(OIPG, Package() { - /* No physical recovery button */ - Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10013, "Braswell" }, -}) diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 0e072f0..0fb9811 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -118,3 +118,13 @@ int get_write_protect_state(void) /* WP is enabled when the pin is reading high. */ return !!gpio_get(WP_GPIO); } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl index f1248d8..59af6dd 100644 --- a/src/mainboard/intel/strago/dsdt.asl +++ b/src/mainboard/intel/strago/dsdt.asl @@ -54,7 +54,6 @@ DefinitionBlock( #include <soc/intel/common/acpi/wifi.asl> } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 0566c8e..71ba62b 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -18,6 +18,7 @@ #include <bootstate.h> #include <device/device.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" static void mainboard_init(device_t dev) @@ -32,6 +33,7 @@ static void mainboard_init(device_t dev) static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl deleted file mode 100644 index 4257e7d..0000000 --- a/src/mainboard/intel/wtm2/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery - Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer - Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect -}) diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index feee0cb..862f4a4 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -19,6 +19,7 @@ #include <device/device.h> #include <device/pci.h> #include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> /* Compile-time settings for developer and recovery mode. */ #define DEV_MODE_SETTING 1 @@ -55,3 +56,14 @@ int get_write_protect_state(void) { return 0; } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 1601483..410f6d2 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -49,7 +49,6 @@ DefinitionBlock( #include "acpi/thermal.asl" // Chrome OS specific - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> // Chipset specific sleep states diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 253e8ff..ffb5b86 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -39,6 +40,7 @@ void mainboard_suspend_resume(void) static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl deleted file mode 100644 index f3bb40b..0000000 --- a/src/mainboard/samsung/lumpy/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 9ee32bb..71d82b5 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -21,6 +21,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 24 #define GPIO_REC_MODE 42 @@ -135,3 +136,14 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index ed3a84a..28b0c1b 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -52,7 +52,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 95a7531..3de067e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -31,6 +31,7 @@ #include "onboard.h" #include <southbridge/intel/bd82x6x/pch.h> #include <smbios.h> +#include <vendorcode/google/chromeos/chromeos.h> void mainboard_suspend_resume(void) { @@ -98,6 +99,7 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl deleted file mode 100644 index 5d69251..0000000 --- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name(OIPG, Package() { - Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button - Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch - Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect -}) diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 5f2a062..96d2b12 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 68 #define GPIO_REC_MODE 42 @@ -132,3 +133,14 @@ void init_bootmode_straps(void) pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); #endif } + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_DEV_AH(GPIO_DEV_MODE, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), +}; + +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); +} diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 4b0e730..3e13a41 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -50,7 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index a0fd9e8..654b1de 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -28,12 +28,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..aa1ce8c 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -362,6 +362,12 @@ #define PAD_W(pad) (pad - W_OFFSET) #define PAD_SW(pad) (pad - SW_OFFSET) +/* Linux names of the GPIO devices. */ +#define GPIO_COMM_N_NAME "INT3452:00" +#define GPIO_COMM_NW_NAME "INT3452:01" +#define GPIO_COMM_W_NAME "INT3452:02" +#define GPIO_COMM_SW_NAME "INT3452:03" + /* Default configurations */ #define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x)) #define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1) diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 79c19b4..3757eb0 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -22,6 +22,8 @@ /* #define GPIO_DEBUG */ +#define CROS_GPIO_DEVICE_NAME "BayTrail" + /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ #define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index c7bfb65..3c56f6a 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -22,6 +22,8 @@ #include <soc/gpio_defs.h> #include <soc/iomap.h> +#define CROS_GPIO_DEVICE_NAME "Braswell" + #define COMMUNITY_SIZE 0x20000 #define COMMUNITY_GPSOUTHWEST_BASE \ diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 7345df5..ff51283 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -18,6 +18,9 @@ #include <stdint.h> +#define CROS_GPIO_DEVICE_NAME "PCH-LP" +#define CROS_GPIO_ACPI_DEVICE_NAME "INT3437:00" + /* PCH-LP GPIOBASE Registers */ #define GPIO_OWNER(set) (0x00 + ((set) * 4)) #define GPIO_PIRQ_APIC_EN 0x10 diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 6733889..d86af0f 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -19,6 +19,8 @@ #include <soc/gpio_defs.h> +#define CROS_GPIO_DEVICE_NAME "INT344B:00" + #ifndef __ACPI__ #include <stdint.h> #include <stddef.h> diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 28323ac..f22fed5 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -51,6 +51,12 @@ #define DEFAULT_RCBA 0xfed1c000 #endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) +#define CROS_GPIO_DEVICE_NAME "CougarPoint" +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216) +#define CROS_GPIO_DEVICE_NAME "PantherPoint" +#endif + #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a3cd811..8cae50a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -19,6 +19,8 @@ #include <arch/acpi.h> +#define CROS_GPIO_DEVICE_NAME "LynxPoint" + /* * Lynx Point PCH PCI Devices: * diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index dffbcd5..c94d6ab 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += chromeos.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c new file mode 100644 index 0000000..6605809 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include "chromeos.h" + +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num) +{ + size_t i; + + acpigen_write_scope("\\"); + acpigen_write_name("OIPG"); + + acpigen_write_package(num); + for (i = 0; i < num; i++) { + acpigen_write_package(4); + acpigen_write_integer(gpios[i].type); + acpigen_write_integer(gpios[i].polarity); + acpigen_write_integer(gpios[i].gpio_num); + acpigen_write_string(gpios[i].device); + acpigen_pop_len(); + } + acpigen_pop_len(); + + acpigen_pop_len(); +} + +void chromeos_dsdt_generator(struct device *dev) +{ + mainboard_chromeos_acpi_generate(); +} diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 7d62f4a..44d9d15 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -15,6 +15,11 @@ #include <vboot/vbnv_layout.h> +#if IS_ENABLED(CONFIG_CHROMEOS) + +/* GPIO package generated at run time. */ +External (OIPG) + Device (CRHW) { Name(_HID, EISAID("GGL0001")) @@ -107,3 +112,4 @@ Device (CRHW) } #include "ramoops.asl" +#endif diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0a93ccd..fd845bf 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -19,6 +19,7 @@ #include <stddef.h> #include <stdint.h> #include <bootmode.h> +#include <device/device.h> #include <rules.h> #include <vboot/misc.h> #include <vboot/vboot_common.h> @@ -53,4 +54,75 @@ static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} void cbmem_add_vpd_calibration_data(void); +/* + * Create the OIPG package containing the Chrome OS gpios described by + * the chromeos_gpio array. + */ +struct cros_gpio; +void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num); + +/* + * Common helper function and delcarations for mainboards to use to generate + * ACPI-specific Chrome OS needs. + */ +void mainboard_chromeos_acpi_generate(void); +#if IS_ENABLED(CONFIG_CHROMEOS) +void chromeos_dsdt_generator(struct device *dev); +#else +#define chromeos_dsdt_generator DEVICE_NOOP +#endif + +enum { + CROS_GPIO_REC = 1, /* Recovery */ + CROS_GPIO_DEV = 2, /* Developer */ + CROS_GPIO_WP = 3, /* Write Protect */ + + CROS_GPIO_ACTIVE_LOW = 0, + CROS_GPIO_ACTIVE_HIGH = 1, + + CROS_GPIO_VIRTUAL = -1, +}; + +struct cros_gpio { + int type; + int polarity; + int gpio_num; + const char *device; +}; + +#define CROS_GPIO_INITIALIZER(typ, pol, num, dev) \ + { \ + .type = (typ), \ + .polarity = (pol), \ + .gpio_num = (num), \ + .device = (dev), \ + } + +#define CROS_GPIO_REC_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_REC, pol, num, dev) + +#define CROS_GPIO_REC_AL(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_REC_AH(num, dev) \ + CROS_GPIO_REC_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_DEV_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_DEV, pol, num, dev) + +#define CROS_GPIO_DEV_AL(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_DEV_AH(num, dev) \ + CROS_GPIO_DEV_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + +#define CROS_GPIO_WP_INITIALIZER(pol, num, dev) \ + CROS_GPIO_INITIALIZER(CROS_GPIO_WP, pol, num, dev) + +#define CROS_GPIO_WP_AL(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_LOW, num, dev) + +#define CROS_GPIO_WP_AH(num, dev) \ + CROS_GPIO_WP_INITIALIZER(CROS_GPIO_ACTIVE_HIGH, num, dev) + #endif /* __CHROMEOS_H__ */

1 0

Patch set updated for coreboot: google/reef: Add pull up 20K for LPC SERIRQ
by Kane Chen 29 Jul '16

29 Jul '16

Kane Chen (kane.chen(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15951 -gerrit commit 94039e1d9b776a3e77c4ed8fb0a84835621a82a8 Author: Kane Chen <kane.chen(a)intel.com> Date: Thu Jul 28 19:41:15 2016 +0800 google/reef: Add pull up 20K for LPC SERIRQ per hw team's check and info from EDS, this pin need to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory help to verify the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a --- src/mainboard/google/reef/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 88f5cdc..1e88215 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */

1 0

New patch to review for coreboot: google/reef: fixed keyboard can't be detected on some evt boards
by Kane Chen 29 Jul '16

29 Jul '16

Kane Chen (kane.chen(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15951 -gerrit commit 2b6c53d61460e5cd5ea8ffce75ba636825718fbd Author: Kane Chen <kane.chen(a)intel.com> Date: Thu Jul 28 19:41:15 2016 +0800 google/reef: fixed keyboard can't be detected on some evt boards per hw team's check and info from EDS, this pin need to be pu 20K. BUG=chrome-os-partner:55586 Branch=none Test=boot ok and Quanta factory help to verify the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a --- src/mainboard/google/reef/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 88f5cdc..1e88215 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -77,7 +77,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP), /* SMB_DATA */ /* LPC */ - PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), /* LPC_AD0 */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Configure gpio ownership
by Jagadish Krishnamoorthy 29 Jul '16

29 Jul '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15871 -gerrit commit 7c101b924f0260e7e1559b84ec435dfad5b46ce7 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Mon Jul 25 13:59:44 2016 -0700 soc/intel/apollolake: Configure gpio ownership For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 22 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 8 ++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 9 +++++++++ 3 files changed, 39 insertions(+) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a3ffb3d..9a3e97d 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -54,6 +54,25 @@ static const struct pad_community *gpio_get_community(uint16_t pad) return map; } +static void gpio_configure_owner(const struct pad_config *cfg, uint16_t port) +{ + uint16_t pin = gpio_acpi_pin(cfg->pad); + uint16_t reg; + + /* Based on the gpio pin number configure the + * corresponding bit in HOSTSW_OWN register. + * Value of 0x1 indicates Gpio Driver onwership. + */ + if (pin < 32) + reg = HOSTSW_OWN_0; + else if (pin >= 32 && pin < 64) + reg = HOSTSW_OWN_1; + else + reg = HOSTSW_OWN_2; + + iosf_write(port, reg, iosf_read(port, reg) | 1 << (pin % 32)); +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -91,6 +110,9 @@ void gpio_configure_pad(const struct pad_config *cfg) iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1); gpio_configure_itss(cfg, comm->port, config_offset); + /* Use the RO bit in pad_config 1 register to indicate the ownership */ + if (cfg->config1 & PAD_CFG1_GPIO_DRIVER) + gpio_configure_owner(cfg, comm->port); } void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 1ebac2d..f02c123 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -56,6 +56,14 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull)) +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to Gpio Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER) + /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..7fc6a08 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -45,6 +45,10 @@ #define MISCCFG_GPE0_DW2_SHIFT 16 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) +#define HOSTSW_OWN_0 0x80 /* Host Software Pad Ownership for GPIO 0 ~ 31 */ +#define HOSTSW_OWN_1 0x84 /* Host Software Pad Ownership for GPIO 32 ~ 63 */ +#define HOSTSW_OWN_2 0x88 /* Host Software Pad Ownership for GPIO 64 ~ 95 */ + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) @@ -75,6 +79,11 @@ #define PAD_CFG0_RESET_PLTRST (2 << 30) #define PAD_CFG0_RESET_RSMRST (3 << 30) +/* Use the first bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + * gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 0) #define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10)

1 0

Patch set updated for coreboot: soc/intel/apollolake: Configure gpio ownership
by Jagadish Krishnamoorthy 29 Jul '16

29 Jul '16

Jagadish Krishnamoorthy (jagadish.krishnamoorthy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15871 -gerrit commit 43cf050ccf0b198cb8b7c4a66fe0faa4e5c89841 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Mon Jul 25 13:59:44 2016 -0700 soc/intel/apollolake: Configure gpio ownership For the gpio based irq to work, the ownership of the pad should be changed to GPIO_DRIVER. Provide an option in the gpio defs to configure the PAD onwership. BUG=chrome-os-partner:54371 TEST=none Change-Id: I26d242d25d2034049340adf526045308fcdebbc0 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 22 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 7 +++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 9 +++++++++ 3 files changed, 38 insertions(+) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a3ffb3d..1b922cc 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -54,6 +54,25 @@ static const struct pad_community *gpio_get_community(uint16_t pad) return map; } +static void gpio_configure_owner(const struct pad_config *cfg, uint16_t port) +{ + uint16_t pin = gpio_acpi_pin(cfg->pad); + uint16_t reg; + + /* Based on the gpio pin number configure the + * corresponding bit in HostSW_OWN register. + * Value of 0x1 indicates Gpio Driver onwership. + */ + if (pin < 32) + reg = HOSTSW_OWN_0; + else if (pin >= 32 && pin < 64) + reg = HOSTSW_OWN_1; + else + reg = HOSTSW_OWN_2; + + iosf_write(port, reg, iosf_read(port, reg) | 1 << (pin % 32)); +} + static void gpio_configure_itss(const struct pad_config *cfg, uint16_t port, uint16_t pad_cfg_offset) { @@ -91,6 +110,9 @@ void gpio_configure_pad(const struct pad_config *cfg) iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1); gpio_configure_itss(cfg, comm->port, config_offset); + /* Use the RO bit in pad_config 1 register to indicate the ownership */ + if (cfg->config1 & PAD_CFG1_GPIO_DRIVER) + gpio_configure_owner(cfg, comm->port); } void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 1ebac2d..f936ee4 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -56,6 +56,13 @@ typedef uint32_t gpio_t; PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull)) +/* General purpose input. The following macro sets the + * Host Software Pad Ownership to Gpio Driver mode. + */ +#define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER) /* No Connect configuration for unused pad. * NC should be GPI with Term as PU20K, PD20K, NONE depending upon default Term */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..90ed515 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -45,6 +45,10 @@ #define MISCCFG_GPE0_DW2_SHIFT 16 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) +#define HOSTSW_OWN_0 0x80 /*Host Software Pad Ownership for GPIO 0 ~ 31 */ +#define HOSTSW_OWN_1 0x84 /*Host Software Pad Ownership for GPIO 32 ~ 63 */ +#define HOSTSW_OWN_2 0x88 /*Host Software Pad Ownership for GPIO 64 ~ 95 */ + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) @@ -75,6 +79,11 @@ #define PAD_CFG0_RESET_PLTRST (2 << 30) #define PAD_CFG0_RESET_RSMRST (3 << 30) +/* Use the first bit in IntSel field to indicate gpio + * ownership. This field is RO and hence not used during + gpio configuration. + */ +#define PAD_CFG1_GPIO_DRIVER (0x1 << 0) #define PAD_CFG1_IRQ_MASK (0xff << 0) #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10)

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable ELOG
by Brandon Breitenstein 29 Jul '16

29 Jul '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937 -gerrit commit 679168f16b33d6b12352be9162426327bc3624d2 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Jul 18 15:14:12 2016 -0700 soc/intel/apollolake: Enable ELOG Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 101 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 104 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..bd1602a --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. " + "Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..271a68e 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -138,6 +139,7 @@ #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable ELOG
by Brandon Breitenstein 29 Jul '16

29 Jul '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937 -gerrit commit 0ec419bcf4973d107a2d38e5afa6a9450b3a5b82 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Jul 18 15:14:12 2016 -0700 soc/intel/apollolake: Enable ELOG Add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for Apollolake. BUG=chrome-os-partner:55473 BRANCH=none TEST=Verified image boots on Amenia Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 101 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 104 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..bd1602a --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. " + "Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..aef255b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -138,6 +139,7 @@ #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5

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coreboot-gerrit July 2016