coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

Patch merged into coreboot/master: google/reef: Write protect GPIO relative to bank offset
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit ab88c7d36630db9583d1b9a602f0e293f0447f04 Author: Susendra Selvaraj <susendra.selvaraj(a)intel.com> Date: Wed Jun 22 03:52:03 2016 +0530 google/reef: Write protect GPIO relative to bank offset Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=chrome-os-partner:55604 BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab Signed-off-by: Susendra Selvaraj <susendra.selvaraj(a)intel.com> Reviewed-on: https://coreboot.intel.com/7929 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/15691 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15691 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
by Abhay Kumar 28 Jul '16

28 Jul '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14575 -gerrit commit b5646a0af1cc68ea7089930a4e5ad13b2d2e1139 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Thu Jul 14 18:43:54 2016 -0700 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/soc/intel/apollolake/chip.c | 3 +-- src/soc/intel/common/vbt.c | 20 ++++++++++++++++++++ src/soc/intel/common/vbt.h | 5 +++++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 544cd13..10b71fb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -194,8 +194,7 @@ static void soc_init(void *data) struct global_nvs_t *gnvs; /* Save VBT info and mapping */ - if (locate_vbt(&vbt_rdev) != CB_ERR) - vbt = rdev_mmap_full(&vbt_rdev); + vbt = vbt_get(&vbt_rdev); /* Snapshot the current GPIO IRQ polarities. FSP is setting a * default policy that doesn't honor boards' requirements. */ diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 80b17a2..d9bb98a 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -15,6 +15,8 @@ #include <cbfs.h> #include <console/console.h> +#include <arch/acpi.h> +#include <bootmode.h> #include "vbt.h" @@ -40,3 +42,21 @@ enum cb_err locate_vbt(struct region_device *rdev) return CB_SUCCESS; } + +void *vbt_get(struct region_device *rdev) +{ + void *vbt_data; + + /* Normal mode and S3 resume path PEIM GFX init is not needed. + * Passing NULL as VBT will not make PEIM GFX to execute. */ + if (acpi_is_wakeup_s3()) + return NULL; + if (!display_init_required()) + return NULL; + if (locate_vbt(rdev) != CB_ERR) { + vbt_data = rdev_mmap_full(rdev); + return vbt_data; + } else { + return NULL; + } +} diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index e1a45cc..9a02e6a 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -21,4 +21,9 @@ /* locate .vbt file */ enum cb_err locate_vbt(struct region_device *rdev); +/* + * Returns VBT pointer and mapping after checking prerequisites for Pre OS + * Graphics initialization + */ +void *vbt_get(struct region_device *rdev); #endif

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New patch to review for coreboot: google/reef: Use GPE0_DW1_15 as wake signal for touchpad
by Furquan Shaikh 28 Jul '16

28 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15947 -gerrit commit 8b84f9eb253bbed73fb13815823e46047c5d63b6 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 28 13:47:34 2016 -0700 google/reef: Use GPE0_DW1_15 as wake signal for touchpad Due to GPE routing, raw GPIO cannot be used for indicating the wake signal for touchpad. Instead we need to reference GPE pins. BUG=chrome-os-partner:55670 Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index a04a3cd..02a4384 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -100,7 +100,7 @@ chip soc/intel/apollolake register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" - register "wake" = "GPIO_15" + register "wake" = "GPE0_DW1_15" device i2c 15 on end end end # - I2C 4

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New patch to review for coreboot: soc/intel/apollolake: Include gpe.h in chip.h
by Furquan Shaikh 28 Jul '16

28 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15946 -gerrit commit ae437a0461e4eaa6296907507aed6ecf1a83a35d Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 28 13:44:53 2016 -0700 soc/intel/apollolake: Include gpe.h in chip.h This is required for using GPE_* macros in devicetree.cb. BUG=chrome-os-partner:55670 Change-Id: I8f6f536df96cf8145bb0c03ec413fb2f374301b5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/chip.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 37b1cc0..16c3aeb 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,7 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/gpe.h> #include <soc/gpio_defs.h> #include <soc/gpio.h> #include <soc/intel/common/lpss_i2c.h>

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Patch set updated for coreboot: libpayload: replace cbfs_media api with region_device api
by Antonello Dettori 28 Jul '16

28 Jul '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15774 -gerrit commit 66cc28aec1f98529eda522ba9fda9bd1a4e85bac Author: Antonello Dettori <dev(a)dettori.io> Date: Thu Jul 21 15:30:46 2016 +0200 libpayload: replace cbfs_media api with region_device api Replace all the functionality provided by the cbfs_image api with the more recent region_device api used throughout the rest of the coreboot project. Change-Id: Ia79f532a9f8701f6c586609d38f6a88bfdf116e9 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/libpayload/arch/arm/dummy_media.c | 5 +- payloads/libpayload/arch/arm64/dummy_media.c | 5 +- payloads/libpayload/arch/mips/dummy_media.c | 5 +- payloads/libpayload/arch/x86/rom_media.c | 85 +----- payloads/libpayload/drivers/video/graphics.c | 1 - payloads/libpayload/include/cbfs.h | 13 +- payloads/libpayload/include/cbfs_core.h | 40 +-- payloads/libpayload/include/cbfs_ram.h | 57 ---- payloads/libpayload/include/mem_pool.h | 69 +++++ payloads/libpayload/include/region_device.h | 248 +++++++++++++++ payloads/libpayload/include/stddef.h | 2 + payloads/libpayload/include/stdlib.h | 19 ++ payloads/libpayload/libc/fmap.c | 16 +- payloads/libpayload/libcbfs/Makefile.inc | 3 +- payloads/libpayload/libcbfs/cbfs.c | 36 ++- payloads/libpayload/libcbfs/cbfs_core.c | 114 +++---- payloads/libpayload/libcbfs/mem_pool.c | 48 +++ payloads/libpayload/libcbfs/ram_media.c | 118 -------- payloads/libpayload/libcbfs/region_device.c | 434 +++++++++++++++++++++++++++ 19 files changed, 938 insertions(+), 380 deletions(-) diff --git a/payloads/libpayload/arch/arm/dummy_media.c b/payloads/libpayload/arch/arm/dummy_media.c index c67344f..e74d4c7 100644 --- a/payloads/libpayload/arch/arm/dummy_media.c +++ b/payloads/libpayload/arch/arm/dummy_media.c @@ -34,10 +34,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/arm64/dummy_media.c b/payloads/libpayload/arch/arm64/dummy_media.c index c67344f..e74d4c7 100644 --- a/payloads/libpayload/arch/arm64/dummy_media.c +++ b/payloads/libpayload/arch/arm64/dummy_media.c @@ -34,10 +34,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c index 112d7fe..1732b75 100644 --- a/payloads/libpayload/arch/mips/dummy_media.c +++ b/payloads/libpayload/arch/mips/dummy_media.c @@ -33,10 +33,7 @@ /* The generic cbfs code relies on the libpayload_init_default_cbfs_media * symbol. Therefore, provide an implementation that just throws an error. */ -int libpayload_init_default_cbfs_media(struct cbfs_media *media); - -__attribute__((weak)) int libpayload_init_default_cbfs_media( - struct cbfs_media *media) +__attribute__((weak)) int libpayload_init_default_cbfs_media(void) { return -1; } diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c index 0c6f521..48c1669 100644 --- a/payloads/libpayload/arch/x86/rom_media.c +++ b/payloads/libpayload/arch/x86/rom_media.c @@ -26,86 +26,31 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ -#define LIBPAYLOAD #include <cbfs.h> #include <string.h> +#include <sysinfo.h> -#ifdef LIBPAYLOAD -# define printk(x...) -# define init_default_cbfs_media libpayload_init_default_cbfs_media - extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -#else -# include <console/console.h> -#endif +static struct mem_region_device boot_dev; -// Implementation of memory-mapped ROM media source on X86. - -static int x86_rom_open(struct cbfs_media *media) { - return 0; -} - -static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) { - void *ptr; - // Some address (ex, pointer to master header) may be given in memory - // mapped location. To workaround that, we handle >0xf0000000 as real - // memory pointer. - - if ((uint32_t)offset > (uint32_t)0xf0000000) - ptr = (void*)offset; - else - ptr = (void*)(0 - (uint32_t)media->context + offset); - return ptr; +struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; } -static void *x86_rom_unmap(struct cbfs_media *media, const void *address) { - return NULL; -} - -static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr = x86_rom_map(media, offset, count); - memcpy(dest, ptr, count); - x86_rom_unmap(media, ptr); - return count; -} +static int init_x86rom_cbfs_media(void) +{ + /* The ROM is memory mapped just below 4GiB. + * Form a pointer for the base. */ + size_t romsize = lib_sysinfo.boot_media_size; + void *rombase = (void *)(uintptr_t)(0x100000000ULL - romsize); -static int x86_rom_close(struct cbfs_media *media) { - return 0; -} + mem_region_device_ro_init(&boot_dev, rombase, romsize); -int init_x86rom_cbfs_media(struct cbfs_media *media); -int init_x86rom_cbfs_media(struct cbfs_media *media) { - // On X86, we always keep a reference of pointer to CBFS header in - // 0xfffffffc, and the pointer is still a memory-mapped address. - // Since the CBFS core always use ROM offset, we need to figure out - // header->romsize even before media is initialized. - struct cbfs_header *header = (struct cbfs_header*) - *(uint32_t*)(0xfffffffc); - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) - printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header); - media->context = (void*)CONFIG_LP_ROM_SIZE; -#else - return -1; -#endif - } else { - uint32_t romsize = ntohl(header->romsize); - media->context = (void*)romsize; -#if IS_ENABLED(CONFIG_LP_ROM_SIZE) - if (CONFIG_LP_ROM_SIZE != romsize) - printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n", - CONFIG_LP_ROM_SIZE, romsize); -#endif - } - media->open = x86_rom_open; - media->close = x86_rom_close; - media->map = x86_rom_map; - media->unmap = x86_rom_unmap; - media->read = x86_rom_read; return 0; } -int init_default_cbfs_media(struct cbfs_media *media) { - return init_x86rom_cbfs_media(media); +int libpayload_init_default_cbfs_media(void) +{ + return init_x86rom_cbfs_media(); } diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 943f8ed..3d93c88 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -52,7 +52,6 @@ static uint8_t *fbaddr; #define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT) #define PIVOT_V_MASK (PIVOT_V_TOP|PIVOT_V_CENTER|PIVOT_V_BOTTOM) #define ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) -#define ABS(x) ((x) < 0 ? -(x) : (x)) static char initialized = 0; diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index 801bdfc..12ea408 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -53,11 +53,11 @@ const struct cbfs_header *get_cbfs_header(void); struct cbfs_file *cbfs_find(const char *name); void *cbfs_find_file(const char *name, int type); -int cbfs_execute_stage(struct cbfs_media *media, const char *name); -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, +int cbfs_execute_stage(struct region_device *media, const char *name); +void *cbfs_load_optionrom(struct region_device *media, uint16_t vendor, uint16_t device); -void *cbfs_load_payload(struct cbfs_media *media, const char *name); -void *cbfs_load_stage(struct cbfs_media *media, const char *name); +void *cbfs_load_payload(struct region_device *media, const char *name); +void *cbfs_load_stage(struct region_device *media, const char *name); /* Simple buffer for streaming media. */ struct cbfs_simple_buffer { @@ -68,7 +68,7 @@ struct cbfs_simple_buffer { }; void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, + struct region_device *media, size_t offset, size_t count); void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, @@ -78,6 +78,7 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, int run_address(void *f); /* Defined in individual arch / board implementation. */ -int init_default_cbfs_media(struct cbfs_media *media); +int libpayload_init_default_cbfs_media(void); +struct region_device *boot_device_ro(void); #endif diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index f94056d..b7234cd 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -50,6 +50,8 @@ #include <stddef.h> #include <stdint.h> #include <stdlib.h> +#include <region_device.h> + /** These are standard values for the known compression alogrithms that coreboot knows about for stages and @@ -211,43 +213,14 @@ struct cbfs_optionrom { uint32_t len; } __attribute__((packed)); -#define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) -/* Media for CBFS to load files. */ -struct cbfs_media { - - /* implementation dependent context, to hold resource references */ - void *context; - - /* opens media and returns 0 on success, -1 on failure */ - int (*open)(struct cbfs_media *media); - - /* returns number of bytes read from media into dest, starting from - * offset for count of bytes */ - size_t (*read)(struct cbfs_media *media, void *dest, size_t offset, - size_t count); - - /* returns a pointer to memory with count of bytes from media source - * starting from offset, or CBFS_MEDIA_INVALID_MAP_ADDRESS on failure. - * Note: mapped data can't be free unless unmap is called, even if you - * do close first. */ - void * (*map)(struct cbfs_media *media, size_t offset, size_t count); - - /* returns NULL and releases the memory by address, which was allocated - * by map */ - void * (*unmap)(struct cbfs_media *media, const void *address); - - /* closes media and returns 0 on success, -1 on failure. */ - int (*close)(struct cbfs_media *media); -}; - /* * Returns pointer to a copy of the file content or NULL on error. * If the file is compressed, data will be decompressed. * The caller owns the returned memory. */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, +void *cbfs_get_file_content(struct region_device *media, const char *name, int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ @@ -255,11 +228,11 @@ int cbfs_decompress(int algo, void *src, void *dst, int len); /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +const struct cbfs_header *cbfs_get_header(struct region_device *media); /* Persistent handle to a CBFS file that has not yet been fully mapped. */ struct cbfs_handle { - struct cbfs_media media; /* copy of original media object */ + struct region_device *media; /* pointer to original media object */ u32 type; /* CBFS file type */ u32 media_offset; /* offset from beginning of media */ u32 attribute_offset; /* relative offset of attributes */ @@ -269,7 +242,8 @@ struct cbfs_handle { /* Returns handle to CBFS file, or NULL on error. Does not yet map contents. * Caller is responsible to free() returned handle after use. */ -struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name); +struct cbfs_handle *cbfs_get_handle(struct region_device *media, + const char *name); /* Given a cbfs_handle and an attribute tag, return a mapping for the first * instance of the attribute or NULL if none found. */ diff --git a/payloads/libpayload/include/cbfs_ram.h b/payloads/libpayload/include/cbfs_ram.h deleted file mode 100644 index 72839fe..0000000 --- a/payloads/libpayload/include/cbfs_ram.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2013 Google, Inc. - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ - -#ifndef _CBFS_RAM_H_ -#define _CBFS_RAM_H_ - -#include <stdint.h> - -struct cbfs_media; - -/* The following functions return 0 for success. None-zero on error. */ -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size); -int setup_cbfs_from_ram(void *start, uint32_t size); -int setup_cbfs_from_flash(void); - -#endif /* _CBFS_RAM_H_ */ diff --git a/payloads/libpayload/include/mem_pool.h b/payloads/libpayload/include/mem_pool.h new file mode 100644 index 0000000..c21fa0e --- /dev/null +++ b/payloads/libpayload/include/mem_pool.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MEM_POOL_H_ +#define _MEM_POOL_H_ + +#include <stddef.h> +#include <stdint.h> + +/* + * The memory pool allows one to allocate memory from a fixed size buffer + * that also allows freeing semantics for reuse. However, the current + * limitation is that the most recent allocation is the only one that + * can be freed. If one tries to free any allocation that isn't the + * most recently allocated it will result in a leak within the memory pool. + * + * The memory returned by allocations are at least 8 byte aligned. Note + * that this requires the backing buffer to start on at least an 8 byte + * alignment. + */ + +struct mem_pool { + uint8_t *buf; + size_t size; + uint8_t *last_alloc; + size_t free_offset; +}; + +#define MEM_POOL_INIT(buf_, size_) \ + { \ + .buf = (buf_), \ + .size = (size_), \ + .last_alloc = NULL, \ + .free_offset = 0, \ + } + +static inline void mem_pool_reset(struct mem_pool *mp) +{ + mp->last_alloc = NULL; + mp->free_offset = 0; +} + +/* Initialize a memory pool. */ +static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz) +{ + mp->buf = buf; + mp->size = sz; + mem_pool_reset(mp); +} + +/* Allocate requested size from the memory pool. NULL returned on error. */ +void *mem_pool_alloc(struct mem_pool *mp, size_t sz); + +/* Free allocation from memory pool. */ +void mem_pool_free(struct mem_pool *mp, void *alloc); + +#endif /* _MEM_POOL_H_ */ diff --git a/payloads/libpayload/include/region_device.h b/payloads/libpayload/include/region_device.h new file mode 100644 index 0000000..8926ecf --- /dev/null +++ b/payloads/libpayload/include/region_device.h @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _REGION_H_ +#define _REGION_H_ + +#include <sys/types.h> +#include <stdint.h> +#include <stddef.h> +#include <mem_pool.h> + +/* + * Region support. + * + * Regions are intended to abstract away the access mechanisms for blocks of + * data. This could be SPI, eMMC, or a memory region as the backing store. + * They are accessed through a region_device. Subregions can be made by + * chaining together multiple region_devices. + */ + +struct region_device; + +/* + * Returns NULL on error otherwise a buffer is returned with the conents of + * the requested data at offset of size. + */ +void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size); + +/* Unmap a previously mapped area. Returns 0 on success, < 0 on error. */ +int rdev_munmap(const struct region_device *rd, void *mapping); + +/* + * Returns < 0 on error otherwise returns size of data read at provided + * offset filling in the buffer passed. + */ +ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset, + size_t size); + +/* + * Returns < 0 on error otherwise returns size of data wrote at provided + * offset from the buffer passed. + */ +ssize_t rdev_writeat(const struct region_device *rd, void *b, size_t offset, + size_t size); + +/* + * Returns < 0 on error otherwise returns size of data erased. + * If eraseat ops is not defined it returns size which indicates + * that operation was successful. + */ +ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, + size_t size); + +/**************************************** + * Implementation of a region device * + ****************************************/ + +/* + * Create a child region of the parent provided the sub-region is within + * the parent's region. Returns < 0 on error otherwise 0 on success. Note + * that the child device only calls through the parent's operations. + */ +int rdev_chain(struct region_device *child, const struct region_device *parent, + size_t offset, size_t size); + + +/* A region_device operations. */ +struct region_device_ops { + void *(*mmap)(const struct region_device *, size_t, size_t); + int (*munmap)(const struct region_device *, void *); + ssize_t (*readat)(const struct region_device *, void *, size_t, size_t); + ssize_t (*writeat)(const struct region_device *, void *, size_t, + size_t); + ssize_t (*eraseat)(const struct region_device *, size_t, size_t); +}; + +struct region { + size_t offset; + size_t size; +}; + +struct region_device { + const struct region_device *root; + const struct region_device_ops *ops; + struct region region; +}; + +#define REGION_DEV_INIT(ops_, offset_, size_) \ + { \ + .root = NULL, \ + .ops = (ops_), \ + .region = { \ + .offset = (offset_), \ + .size = (size_), \ + }, \ + } + +/* Helper to dynamically initialize region device. */ +void region_device_init(struct region_device *rdev, + const struct region_device_ops *ops, size_t offset, + size_t size); + +static inline size_t region_offset(const struct region *r) +{ + return r->offset; +} + +static inline size_t region_sz(const struct region *r) +{ + return r->size; +} + +static inline const struct region *region_device_region( + const struct region_device *rdev) +{ + return &rdev->region; +} + +static inline size_t region_device_sz(const struct region_device *rdev) +{ + return region_sz(region_device_region(rdev)); +} + +static inline size_t region_device_offset(const struct region_device *rdev) +{ + return region_offset(region_device_region(rdev)); +} + +/* Memory map entire region device. Same semantics as rdev_mmap() above. */ +static inline void *rdev_mmap_full(const struct region_device *rd) +{ + return rdev_mmap(rd, 0, region_device_sz(rd)); +} + +/* + * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0 + * when child is not within the parent's region. + */ +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c); + +struct mem_region_device { + char *base; + struct region_device rdev; +}; + +/* Inititalize at runtime a mem_region_device. This would be used when + * the base and size are dynamic or can't be known during linking. + * There are two variants: read-only and read-write. */ +void mem_region_device_ro_init(struct mem_region_device *mdev, void *base, + size_t size); + +void mem_region_device_rw_init(struct mem_region_device *mdev, void *base, + size_t size); + +extern const struct region_device_ops mem_rdev_ro_ops; + +extern const struct region_device_ops mem_rdev_rw_ops; + +/* Statically initialize mem_region_device. */ +#define MEM_REGION_DEV_INIT(base_, size_, ops_) \ + { \ + .base = (void *)(base_), \ + .rdev = REGION_DEV_INIT((ops_), 0, (size_)), \ + } + +#define MEM_REGION_DEV_RO_INIT(base_, size_) \ + MEM_REGION_DEV_INIT(base_, size_, &mem_rdev_ro_ops) \ + +#define MEM_REGION_DEV_RW_INIT(base_, size_) \ + MEM_REGION_DEV_INIT(base_, size_, &mem_rdev_rw_ops) \ + +struct mmap_helper_region_device { + struct mem_pool pool; + struct region_device rdev; +}; + +#define MMAP_HELPER_REGION_INIT(ops_, offset_, size_) \ + { \ + .rdev = REGION_DEV_INIT((ops_), (offset_), (size_)), \ + } + +void mmap_helper_device_init(struct mmap_helper_region_device *mdev, + void *cache, size_t cache_size); + +void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t); +int mmap_helper_rdev_munmap(const struct region_device *, void *); + +/* A translated region device provides the ability to publish a region device + * in one address space and use an access mechanism within another address + * space. The sub region is the window within the 1st address space and + * the request is modified prior to accessing the second address space + * provided by access_dev. */ +struct xlate_region_device { + const struct region_device *access_dev; + struct region sub_region; + struct region_device rdev; +}; + +extern const struct region_device_ops xlate_rdev_ro_ops; + +extern const struct region_device_ops xlate_rdev_rw_ops; + +#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_, ops_) \ + { \ + .access_dev = access_dev_, \ + .sub_region = { \ + .offset = (sub_offset_), \ + .size = (sub_size_), \ + }, \ + .rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \ + } + +#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_) \ + XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ + sub_size_, parent_sz_, &xlate_rdev_ro_ops), \ + +#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \ + parent_sz_) \ + XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \ + sub_size_, parent_sz_, &xlate_rdev_rw_ops), \ + +/* Helper to dynamically initialize xlate region device. */ +void xlate_region_device_ro_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size); + +void xlate_region_device_rw_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size); + +#endif /* _REGION_H_ */ diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h index fe455b8..a35bd68 100644 --- a/payloads/libpayload/include/stddef.h +++ b/payloads/libpayload/include/stddef.h @@ -20,6 +20,8 @@ typedef __SIZE_TYPE__ ssize_t; offsetof(struct structure, member) == offset, \ "`struct " #structure "` offset for `" #member "` is not " #offset) +#define __unused __attribute__((unused)) + /* Standard units. */ #define KiB (1<<10) #define MiB (1<<20) diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 689bf01..cf9156f 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -41,6 +41,25 @@ #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define ABS(a) (((a) < 0) ? (-(a)) : (a)) +#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) +#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @param ptr: the pointer to the member. + * @param type: the type of the container struct this is embedded in. + * @param member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const __typeof__(((type *)0)->member) * __mptr = (ptr); \ + (type *)((char *)__mptr - offsetof(type, member)); }) + /** * @defgroup malloc Memory allocation functions * @{ diff --git a/payloads/libpayload/libc/fmap.c b/payloads/libpayload/libc/fmap.c index af9902e..cf0c57c 100644 --- a/payloads/libpayload/libc/fmap.c +++ b/payloads/libpayload/libc/fmap.c @@ -41,15 +41,13 @@ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, struct fmap *fmap; struct fmap fmap_head; - struct cbfs_media default_media; - struct cbfs_media *media = &default_media; + struct region_device default_media; + struct region_device *media = &default_media; - if (init_default_cbfs_media(media) != 0) - return -1; - - media->open(media); + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); - if (!media->read(media, &fmap_head, fmap_offset, sizeof(fmap_head))) + if (rdev_readat(media, &fmap_head, fmap_offset, sizeof(fmap_head)) < 0) return -1; if (memcmp(fmap_head.signature, FMAP_SIGNATURE, sizeof(fmap_head.signature))) { @@ -63,11 +61,9 @@ int fmap_region_by_name(const uint32_t fmap_offset, const char * const name, if (!fmap) return -1; - if (!media->read(media, fmap, fmap_offset, fmap_size)) + if (rdev_readat(media, fmap, fmap_offset, fmap_size) < 0) goto err; - media->close(media); - for (i = 0; i < fmap->nareas; i++) { if (strcmp((const char *)fmap->areas[i].name, name) != 0) continue; diff --git a/payloads/libpayload/libcbfs/Makefile.inc b/payloads/libpayload/libcbfs/Makefile.inc index 133b215..4a3ce1e 100644 --- a/payloads/libpayload/libcbfs/Makefile.inc +++ b/payloads/libpayload/libcbfs/Makefile.inc @@ -28,4 +28,5 @@ ## libcbfs-$(CONFIG_LP_CBFS) += cbfs.c -libcbfs-$(CONFIG_LP_CBFS) += ram_media.c +libcbfs-$(CONFIG_LP_CBFS) += region_device.c +libcbfs-$(CONFIG_LP_CBFS) += mem_pool.c diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c index 38b1ff8..3751b95 100644 --- a/payloads/libpayload/libcbfs/cbfs.c +++ b/payloads/libpayload/libcbfs/cbfs.c @@ -83,7 +83,7 @@ static void tohex16(unsigned int val, char* dest) dest[3] = tohex4(val & 0xf); } -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, +void *cbfs_load_optionrom(struct region_device *media, uint16_t vendor, uint16_t device) { char name[17] = "pciXXXX,XXXX.rom"; @@ -94,7 +94,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); } -void * cbfs_load_stage(struct cbfs_media *media, const char *name) +void *cbfs_load_stage(struct region_device *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); @@ -131,7 +131,8 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -int cbfs_execute_stage(struct cbfs_media *media, const char *name) + +int cbfs_execute_stage(struct region_device *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); @@ -152,23 +153,23 @@ int cbfs_execute_stage(struct cbfs_media *media, const char *name) return result; } -void *cbfs_load_payload(struct cbfs_media *media, const char *name) +void *cbfs_load_payload(struct region_device *media, const char *name) { return (struct cbfs_payload *)cbfs_get_file_content( media, name, CBFS_TYPE_PAYLOAD, NULL); } -struct cbfs_file *cbfs_find(const char *name) { +struct cbfs_file *cbfs_find(const char *name) +{ struct cbfs_handle *handle = cbfs_get_handle(CBFS_DEFAULT_MEDIA, name); - struct cbfs_media *m = &handle->media; void *ret; if (!handle) return NULL; - ret = m->map(m, handle->media_offset, + ret = rdev_mmap(handle->media, handle->media_offset, handle->content_offset + handle->content_size); - if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (ret == NULL) { free(handle); return NULL; } @@ -177,30 +178,32 @@ struct cbfs_file *cbfs_find(const char *name) { return ret; } -void *cbfs_find_file(const char *name, int type) { +void *cbfs_find_file(const char *name, int type) +{ return cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type, NULL); } -const struct cbfs_header *get_cbfs_header(void) { +const struct cbfs_header *get_cbfs_header(void) +{ return cbfs_get_header(CBFS_DEFAULT_MEDIA); } /* Simple buffer */ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { + struct region_device *media, size_t offset, size_t count) +{ void *address = buffer->buffer + buffer->allocated;; DEBUG("simple_buffer_map(offset=%zu, count=%zu): " "allocated=%zu, size=%zu, last_allocate=%zu\n", offset, count, buffer->allocated, buffer->size, buffer->last_allocate); if (buffer->allocated + count >= buffer->size) - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - if (media->read(media, address, offset, count) != count) { + return NULL; + if (rdev_readat(media, address, offset, count) != count) { ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; + return NULL; } buffer->allocated += count; buffer->last_allocate = count; @@ -208,7 +211,8 @@ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, } void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { + const void *address) +{ // TODO Add simple buffer management so we can free more than last // allocated one. DEBUG("simple_buffer_unmap(address=0x%p): " diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c index 7e660ce..ccca2af 100644 --- a/payloads/libpayload/libcbfs/cbfs_core.c +++ b/payloads/libpayload/libcbfs/cbfs_core.c @@ -54,32 +54,29 @@ /* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +const struct cbfs_header *cbfs_get_header(struct region_device *media) { int32_t rel_offset; const struct cbfs_header *header; - struct cbfs_media default_media; if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); } - media->open(media); - if (!media->read(media, &rel_offset, (size_t)(0 - sizeof(int32_t)), - sizeof(int32_t))) { - ERROR("Could not read CBFS master header offset!\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } - header = media->map(media, (size_t)rel_offset, sizeof(*header)); + /* Find the CBFS master header pointer/offset at 0xfffffffc. + * There is no return value check since the offset can be negative. */ + rdev_readat(media, &rel_offset, + lib_sysinfo.boot_media_size - sizeof(int32_t), + sizeof(int32_t)); + + rel_offset += lib_sysinfo.boot_media_size; + + header = rdev_mmap(media, rel_offset, sizeof(*header)); DEBUG("CBFS header at %#zx (-%#zx from end of image).\n", (size_t)rel_offset, (size_t)-rel_offset); - media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + if (header == NULL) { ERROR("Failed to load CBFS header from %#zx(-%#zx)\n", (size_t)rel_offset, (size_t)-rel_offset); return CBFS_HEADER_INVALID_ADDRESS; @@ -99,7 +96,7 @@ const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) } static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, - struct cbfs_media *media) + struct region_device *media) { const struct cbfs_header *header; @@ -115,17 +112,17 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, header = cbfs_get_header(media); if (header == CBFS_HEADER_INVALID_ADDRESS) return -1; - // Logical offset (for source media) of first file. + /* Logical offset (for source media) of first file. */ *offset = ntohl(header->offset); *cbfs_end = ntohl(header->romsize); #if IS_ENABLED(CONFIG_LP_ARCH_X86) - // resolve actual length of ROM used for CBFS components - // the bootblock size was not taken into account + /*resolve actual length of ROM used for CBFS components + * the bootblock size was not taken into account. */ *cbfs_end -= ntohl(header->bootblocksize); - // fine tune the length to handle alignment positioning. - // using (bootblock size) % align, to derive the - // number of bytes the bootblock is off from the alignment size. + /* fine tune the length to handle alignment positioning. + * using (bootblock size) % align, to derive the + * number of bytes the bootblock is off from the alignment size. */ if ((ntohl(header->bootblocksize) % CBFS_ALIGNMENT)) *cbfs_end -= (CBFS_ALIGNMENT - (ntohl(header->bootblocksize) % CBFS_ALIGNMENT)); @@ -135,10 +132,11 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end, return 0; } -/* public API starts here*/ -struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) +/* Public API starts here. */ +struct cbfs_handle *cbfs_get_handle(struct region_device *media, + const char *name) { - const char *vardata; + char *vardata; uint32_t offset, cbfs_end, vardata_len; struct cbfs_file file; struct cbfs_handle *handle = malloc(sizeof(*handle)); @@ -147,33 +145,34 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) return NULL; if (get_cbfs_range(&offset, &cbfs_end, media)) { - ERROR("Failed to find cbfs range\n"); + ERROR("Failed to find cbfs range.\n"); return NULL; } if (media == CBFS_DEFAULT_MEDIA) { - media = &handle->media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return NULL; - } + libpayload_init_default_cbfs_media(); + media = boot_device_ro(); + handle->media = media; } else { - memcpy(&handle->media, media, sizeof(*media)); + handle->media = malloc(sizeof(*media)); + if (!handle->media) + return NULL; + memcpy(handle->media, media, sizeof(*media)); } DEBUG("CBFS location: 0x%x~0x%x\n", offset, cbfs_end); DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); - media->open(media); while (offset < cbfs_end && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { + rdev_readat(media, &file, offset, sizeof(file)) == + sizeof(file)) { if (memcmp(CBFS_FILE_MAGIC, file.magic, sizeof(file.magic)) != 0) { uint32_t new_align = CBFS_ALIGNMENT; if (offset % CBFS_ALIGNMENT) new_align += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); - ERROR("ERROR: No file header found at 0x%xx - " + ERROR("ERROR: No file header found at 0x%x - " "try next aligned address: 0x%x.\n", offset, offset + new_align); offset += new_align; @@ -184,17 +183,16 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) offset, vardata_len); // load file name (arbitrary length). - vardata = (const char*)media->map( - media, offset + sizeof(file), vardata_len); - if (vardata == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + vardata = rdev_mmap(media, offset + sizeof(file), + vardata_len); + if (vardata == NULL) { ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); } else if (strcmp(vardata, name) == 0) { int file_offset = ntohl(file.offset), file_len = ntohl(file.len); DEBUG("Found file (offset=0x%x, len=%d).\n", offset + file_offset, file_len); - media->unmap(media, vardata); - media->close(media); + rdev_munmap(media, vardata); handle->type = ntohl(file.type); handle->media_offset = offset; handle->content_offset = file_offset; @@ -205,7 +203,7 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) } else { DEBUG(" (unmatched file @0x%x: %s)\n", offset, vardata); - media->unmap(media, vardata); + rdev_munmap(media, vardata); } // Move to next file. @@ -213,14 +211,13 @@ struct cbfs_handle *cbfs_get_handle(struct cbfs_media *media, const char *name) if (offset % CBFS_ALIGNMENT) offset += CBFS_ALIGNMENT - (offset % CBFS_ALIGNMENT); } - media->close(media); LOG("WARNING: '%s' not found.\n", name); return NULL; } void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) { - struct cbfs_media *m = &handle->media; + struct region_device *m = handle->media; size_t on_media_size = handle->content_size; int algo = CBFS_COMPRESS_NONE; void *ret = NULL; @@ -231,6 +228,7 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) struct cbfs_file_attr_compression *comp = cbfs_get_attr(handle, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (comp) { algo = ntohl(comp->compression); DEBUG("File '%s' is compressed (alg=%d)\n", name, algo); @@ -247,22 +245,29 @@ void *cbfs_get_contents(struct cbfs_handle *handle, size_t *size, size_t limit) } } - void *data = m->map(m, handle->media_offset + handle->content_offset, + void *data = rdev_mmap(m, handle->media_offset + handle->content_offset, on_media_size); - if (data == CBFS_MEDIA_INVALID_MAP_ADDRESS) + if (data == NULL) return NULL; + /* Used to avoid running out of heap memory from malloc. */ + if (algo == CBFS_COMPRESS_NONE) + return data; + ret = malloc(*size); + if (!ret) + return NULL; + if (ret != NULL && !cbfs_decompress(algo, data, ret, *size)) { free(ret); ret = NULL; } - m->unmap(m, data); + rdev_munmap(m, data); return ret; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, +void *cbfs_get_file_content(struct region_device *media, const char *name, int type, size_t *sz) { void *ret = NULL; @@ -283,7 +288,7 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag) { - struct cbfs_media *m = &handle->media; + struct region_device *m = handle->media; uint32_t offset = handle->media_offset + handle->attribute_offset; uint32_t end = handle->media_offset + handle->content_offset; struct cbfs_file_attribute attr; @@ -294,26 +299,23 @@ void *cbfs_get_attr(struct cbfs_handle *handle, uint32_t tag) if (handle->attribute_offset <= sizeof(struct cbfs_file)) return NULL; - m->open(m); while (offset + sizeof(attr) <= end) { - if (m->read(m, &attr, offset, sizeof(attr)) != sizeof(attr)) { + if (rdev_readat(m, &attr, offset, sizeof(attr)) != + sizeof(attr)) { ERROR("Failed to read attribute header %#x\n", offset); - m->close(m); return NULL; } if (ntohl(attr.tag) != tag) { offset += ntohl(attr.len); continue; } - ret = m->map(m, offset, ntohl(attr.len)); - if (ret == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ret = rdev_mmap(m, offset, ntohl(attr.len)); + if (ret == NULL) { ERROR("Failed to map attribute at %#x\n", offset); - m->close(m); return NULL; } return ret; } - m->close(m); return NULL; } diff --git a/payloads/libpayload/libcbfs/mem_pool.c b/payloads/libpayload/libcbfs/mem_pool.c new file mode 100644 index 0000000..c1d3961 --- /dev/null +++ b/payloads/libpayload/libcbfs/mem_pool.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdlib.h> +#include <mem_pool.h> + +void *mem_pool_alloc(struct mem_pool *mp, size_t sz) +{ + void *p; + + /* Make all allocations be at least 8 byte aligned. */ + sz = ALIGN_UP(sz, 8); + + /* Determine if any space available. */ + if ((mp->size - mp->free_offset) < sz) + return NULL; + + p = &mp->buf[mp->free_offset]; + + mp->free_offset += sz; + mp->last_alloc = p; + + return p; +} + +void mem_pool_free(struct mem_pool *mp, void *p) +{ + /* Determine if p was the most recent allocation. */ + if (p == NULL || mp->last_alloc != p) + return; + + mp->free_offset = mp->last_alloc - mp->buf; + /* No way to track allocation before this one. */ + mp->last_alloc = NULL; +} diff --git a/payloads/libpayload/libcbfs/ram_media.c b/payloads/libpayload/libcbfs/ram_media.c deleted file mode 100644 index d5469f6..0000000 --- a/payloads/libpayload/libcbfs/ram_media.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2013 Google, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ -#include <cbfs.h> -#include <cbfs_ram.h> -#include <string.h> -#include <stdio.h> -#include <stdlib.h> - -// Implementation of a media source based on given memory buffer. -struct ram_media { - char *start; - size_t size; -}; - -static int ram_open(struct cbfs_media *media) { - return 0; -} - -static void *ram_map(struct cbfs_media *media, size_t offset, size_t count) { - struct ram_media *m = (struct ram_media*)media->context; - /* assume addressing from top of image in this case */ - if (offset > 0xf0000000) { - offset = m->size + offset; - } - if (offset + count > m->size) { - printf("ERROR: ram_map: request out of range (0x%zx+0x%zx)\n", - offset, count); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - return (void*)(m->start + offset); -} - -static void *ram_unmap(struct cbfs_media *media, const void *address) { - return NULL; -} - -static size_t ram_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr = ram_map(media, offset, count); - if (ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) - return 0; - memcpy(dest, ptr, count); - ram_unmap(media, ptr); - return count; -} - -static int ram_close(struct cbfs_media *media) { - return 0; -} - -int init_cbfs_ram_media(struct cbfs_media *media, void *start, size_t size) { - // TODO Find a way to release unused media. Maybe adding media->destroy. - struct ram_media *m = (struct ram_media*)malloc(sizeof(*m)); - m->start = start; - m->size = size; - media->context = (void*)m; - media->open = ram_open; - media->close = ram_close; - media->map = ram_map; - media->unmap = ram_unmap; - media->read = ram_read; - return 0; -} - -// Legacy setup_cbfs_from_*. -static int is_default_cbfs_media_initialized; -static struct cbfs_media default_cbfs_media; - -int setup_cbfs_from_ram(void *start, uint32_t size) { - int result = init_cbfs_ram_media(&default_cbfs_media, start, size); - if (result == 0) - is_default_cbfs_media_initialized = 1; - return result; -} - -extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -int setup_cbfs_from_flash(void) { - int result = libpayload_init_default_cbfs_media(&default_cbfs_media); - if (result == 0) - is_default_cbfs_media_initialized = 1; - return result; -} - -int init_default_cbfs_media(struct cbfs_media *media) { - int result = 0; - if (is_default_cbfs_media_initialized != 1) { - result = setup_cbfs_from_flash(); - } - if (result == 0) - memcpy(media, &default_cbfs_media, sizeof(*media)); - return result; -} diff --git a/payloads/libpayload/libcbfs/region_device.c b/payloads/libpayload/libcbfs/region_device.c new file mode 100644 index 0000000..f87075a --- /dev/null +++ b/payloads/libpayload/libcbfs/region_device.c @@ -0,0 +1,434 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <stdlib.h> +#include <string.h> +#include <region_device.h> + +static inline size_t region_end(const struct region *r) +{ + return region_sz(r) + region_offset(r); +} + +static int is_subregion(const struct region *p, const struct region *c) +{ + if (region_offset(c) < region_offset(p)) + return 0; + + if (region_sz(c) > region_sz(p)) + return 0; + + if (region_end(c) > region_end(p)) + return 0; + + return 1; +} + +static int normalize_and_ok(const struct region *outer, struct region *inner) +{ + inner->offset += region_offset(outer); + return is_subregion(outer, inner); +} + +static const struct region_device *rdev_root(const struct region_device *rdev) +{ + if (rdev->root == NULL) + return rdev; + return rdev->root; +} + +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c) +{ + if (rdev_root(p) != rdev_root(c)) + return -1; + + if (!is_subregion(&p->region, &c->region)) + return -1; + + return region_device_offset(c) - region_device_offset(p); +} + +void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return NULL; + + rdev = rdev_root(rd); + + return rdev->ops->mmap(rdev, req.offset, req.size); +} + +int rdev_munmap(const struct region_device *rd, void *mapping) +{ + const struct region_device *rdev; + + rdev = rdev_root(rd); + + return rdev->ops->munmap(rdev, mapping); +} + +ssize_t rdev_readat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + return rdev->ops->readat(rdev, b, req.offset, req.size); +} + +ssize_t rdev_writeat(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + if (rdev->ops->writeat == NULL) + return -1; + + return rdev->ops->writeat(rdev, b, req.offset, req.size); +} + +ssize_t rdev_eraseat(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct region_device *rdev; + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&rd->region, &req)) + return -1; + + rdev = rdev_root(rd); + + /* If the eraseat ptr is NULL we assume that the erase + * function was completed successfully. */ + if (rdev->ops->eraseat == NULL) + return size; + + return rdev->ops->eraseat(rdev, req.offset, req.size); +} + +int rdev_chain(struct region_device *child, const struct region_device *parent, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + + if (!normalize_and_ok(&parent->region, &req)) + return -1; + + /* Keep track of root region device. Note the offsets are relative + * to the root device. */ + child->root = rdev_root(parent); + child->ops = NULL; + child->region.offset = req.offset; + child->region.size = req.size; + + return 0; +} + +static void mem_region_device_init(struct mem_region_device *mdev, + const struct region_device_ops *ops, void *base, size_t size) +{ + memset(mdev, 0, sizeof(*mdev)); + mdev->base = base; + mdev->rdev.ops = ops; + mdev->rdev.region.size = size; +} + +void mem_region_device_ro_init(struct mem_region_device *mdev, void *base, + size_t size) +{ + return mem_region_device_init(mdev, &mem_rdev_ro_ops, base, size); +} + +void mem_region_device_rw_init(struct mem_region_device *mdev, void *base, + size_t size) +{ + return mem_region_device_init(mdev, &mem_rdev_rw_ops, base, size); +} + +void region_device_init(struct region_device *rdev, + const struct region_device_ops *ops, size_t offset, + size_t size) +{ + memset(rdev, 0, sizeof(*rdev)); + rdev->root = NULL; + rdev->ops = ops; + rdev->region.offset = offset; + rdev->region.size = size; +} + +static void xlate_region_device_init(struct xlate_region_device *xdev, + const struct region_device_ops *ops, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + memset(xdev, 0, sizeof(*xdev)); + xdev->access_dev = access_dev; + xdev->sub_region.offset = sub_offset; + xdev->sub_region.size = sub_size; + region_device_init(&xdev->rdev, ops, 0, parent_size); +} + +void xlate_region_device_ro_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev, + sub_offset, sub_size, parent_size); +} + +void xlate_region_device_rw_init(struct xlate_region_device *xdev, + const struct region_device *access_dev, + size_t sub_offset, size_t sub_size, + size_t parent_size) +{ + xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev, + sub_offset, sub_size, parent_size); +} + +static void *mdev_mmap(const struct region_device *rd, size_t offset, + size_t size __unused) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + return &mdev->base[offset]; +} + +static int mdev_munmap(const struct region_device *rd __unused, + void *mapping __unused) +{ + return 0; +} + +static ssize_t mdev_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memcpy(b, &mdev->base[offset], size); + + return size; +} + +static ssize_t mdev_writeat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memcpy(&mdev->base[offset], b, size); + + return size; +} + +static ssize_t mdev_eraseat(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memset(&mdev->base[offset], 0, size); + + return size; +} + +const struct region_device_ops mem_rdev_ro_ops = { + .mmap = mdev_mmap, + .munmap = mdev_munmap, + .readat = mdev_readat, +}; + +const struct region_device_ops mem_rdev_rw_ops = { + .mmap = mdev_mmap, + .munmap = mdev_munmap, + .readat = mdev_readat, + .writeat = mdev_writeat, + .eraseat = mdev_eraseat, +}; + +void mmap_helper_device_init(struct mmap_helper_region_device *mdev, + void *cache, size_t cache_size) +{ + mem_pool_init(&mdev->pool, cache, cache_size); +} + +void *mmap_helper_rdev_mmap(const struct region_device *rd, size_t offset, + size_t size) +{ + struct mmap_helper_region_device *mdev; + void *mapping; + + mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + + mapping = mem_pool_alloc(&mdev->pool, size); + + if (mapping == NULL) + return NULL; + + if (rd->ops->readat(rd, mapping, offset, size) != size) { + mem_pool_free(&mdev->pool, mapping); + return NULL; + } + + return mapping; +} + +int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping) +{ + struct mmap_helper_region_device *mdev; + + mdev = container_of((void *)rd, __typeof__(*mdev), rdev); + + mem_pool_free(&mdev->pool, mapping); + + return 0; +} + +static void *xlate_mmap(const struct region_device *rd, size_t offset, + size_t size) +{ + const struct xlate_region_device *xldev; + struct region req = { + .offset = offset, + .size = size, + }; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return NULL; + + offset -= region_offset(&xldev->sub_region); + + return rdev_mmap(xldev->access_dev, offset, size); +} + +static int xlate_munmap(const struct region_device *rd, void *mapping) +{ + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + return rdev_munmap(xldev->access_dev, mapping); +} + +static ssize_t xlate_readat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_readat(xldev->access_dev, b, offset, size); +} + +static ssize_t xlate_writeat(const struct region_device *rd, void *b, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_writeat(xldev->access_dev, b, offset, size); +} + +static ssize_t xlate_eraseat(const struct region_device *rd, + size_t offset, size_t size) +{ + struct region req = { + .offset = offset, + .size = size, + }; + const struct xlate_region_device *xldev; + + xldev = container_of(rd, __typeof__(*xldev), rdev); + + if (!is_subregion(&xldev->sub_region, &req)) + return -1; + + offset -= region_offset(&xldev->sub_region); + + return rdev_eraseat(xldev->access_dev, offset, size); +} + +const struct region_device_ops xlate_rdev_ro_ops = { + .mmap = xlate_mmap, + .munmap = xlate_munmap, + .readat = xlate_readat, +}; + +const struct region_device_ops xlate_rdev_rw_ops = { + .mmap = xlate_mmap, + .munmap = xlate_munmap, + .readat = xlate_readat, + .writeat = xlate_writeat, + .eraseat = xlate_eraseat, +};

1 0

Patch set updated for coreboot: libpayload: split "Drivers" config section in Kconfig
by Antonello Dettori 28 Jul '16

28 Jul '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15914 -gerrit commit 0adddd024057a9129dc572e766e1d1713eb46a44 Author: Antonello Dettori <dev(a)dettori.io> Date: Wed Jul 27 12:41:04 2016 +0200 libpayload: split "Drivers" config section in Kconfig Move the configuration of the timer, storage and USB drivers from the main Kconfig to three separate ones stored in the respective directories. This reduces the LOC of Kconfig and makes it more manageable. Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- payloads/libpayload/Kconfig | 283 +--------------------------- payloads/libpayload/drivers/storage/Kconfig | 59 ++++++ payloads/libpayload/drivers/timer/Kconfig | 129 +++++++++++++ payloads/libpayload/drivers/usb/Kconfig | 129 +++++++++++++ 4 files changed, 320 insertions(+), 280 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 276eb30..51826ea 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -354,286 +354,9 @@ config SPEAKER depends on ARCH_X86 default y -config STORAGE - bool "Support for storage devices" - default y - help - Select this option if you want support for storage devices (like - hard drives, memory sticks or optical drives). - -config STORAGE_64BIT_LBA - bool "Use 64-bit integers to address sectors" - depends on STORAGE - default n - help - If this is selected, sectors will be addressed by an 64-bit integer. - Select this to support LBA-48 for ATA drives. - -config STORAGE_ATA - bool "Support ATA drives (i.e. hard drives)" - depends on STORAGE - default y - help - Select this option if you want support for ATA storage devices - (i.e. hard drives). - -config STORAGE_ATAPI - bool "Support ATAPI drives (i.e. optical drives)" - depends on STORAGE - default y - select STORAGE_ATA - help - Select this option if you want support for ATAPI storage devices - (i.e. optical drives like CD or DVD drives). - -config STORAGE_AHCI - bool "Support for AHCI host controllers" - depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI - default y - help - Select this option if you want support for SATA controllers in - AHCI mode. - -config STORAGE_AHCI_ONLY_TESTED - bool "Only enable tested controllers" - depends on STORAGE_AHCI - default y - help - If this option is selected only AHCI controllers which are known - to work will be used. - -config TIMER_RDTSC - bool - default y - depends on ARCH_X86 - -choice - prompt "Timer driver" - default TIMER_NONE - depends on !ARCH_X86 - -config TIMER_NONE - bool "None" - help - The timer driver is provided by the payload itself. - -config TIMER_MCT - bool "Exynos MCT" - -config TIMER_TEGRA_1US - bool "Tegra 1us" - -config TIMER_IPQ806X - bool "Timer for ipq806x platforms" - -config TIMER_ARMADA38X - bool "Timer for armada38x platforms" - help - This is the timer driver for marvell armada38x - platforms. - -config TIMER_IPQ40XX - bool "Timer for ipq40xx platforms" - help - This is the timer driver for QCA IPQ40xx based - platforms. - -config TIMER_RK - bool "Timer for Rockchip" - -config TIMER_BG4CD - bool "Marvell BG4CD" - -config TIMER_CYGNUS - bool "Timer for Cygnus" - -config TIMER_IMG_PISTACHIO - bool "Timer for IMG Pistachio" - -config TIMER_MTK - bool "Timer for MediaTek MT8173" - -endchoice - -config TIMER_MCT_HZ - int "Exynos MCT frequency" - depends on TIMER_MCT - default 24000000 - -config TIMER_MCT_ADDRESS - hex "Exynos MCT base address" - depends on TIMER_MCT - default 0x101c0000 - -config TIMER_RK_ADDRESS - hex "Rockchip timer base address" - depends on TIMER_RK - default 0xff810020 - -config TIMER_TEGRA_1US_ADDRESS - hex "Tegra u1s timer base address" - depends on TIMER_TEGRA_1US - default 0x60005010 - -config IPQ806X_TIMER_FREQ - int "Hardware timer frequency" - default 32000 - depends on TIMER_IPQ806X - help - IPQ hardware presently provides a single timer running at 32KHz, a - finer granulariry timer is available but is not yet enabled. - -config IPQ806X_TIMER_REG - hex "Timer register address" - default 0x0200A008 - depends on TIMER_IPQ806X - help - Address of the register to read a free running timer value. - -config ARMADA38X_TIMER_FREQ - int "Hardware timer frequency" - depends on TIMER_ARMADA38X - default 25000000 - -config ARMADA38X_TIMER_REG - hex "Timer register address" - default 0xF1020314 - depends on TIMER_ARMADA38X - -config IPROC_PERIPH_GLB_TIM_REG_BASE - hex "Cygnus timer base address" - depends on TIMER_CYGNUS - default 0x19020200 - -config TIMER_MTK_HZ - int "MediaTek GPT frequency" - depends on TIMER_MTK - default 13000000 - help - Clock frequency of MediaTek General Purpose Timer. - -config TIMER_MTK_ADDRESS - hex "MTK GPT register address" - depends on TIMER_MTK - default 0x10008048 - help - Address of GPT4's counter register to read the FREERUN-mode timer value. - -config USB - bool "USB Support" - default y - -config USB_UHCI - bool "Support for USB UHCI controllers" - depends on USB && ARCH_X86 - default y - help - Select this option if you are going to use USB 1.1 on an Intel based - system. - -config USB_OHCI - bool "Support for USB OHCI controllers" - depends on USB - default y - help - Select this option if you are going to use USB 1.1 on a non-Intel based - system. - -config USB_EHCI - bool "Support for USB EHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 2.0 - -config USB_XHCI - bool "Support for USB xHCI controllers" - depends on USB - default y - help - Select this option if you want to use USB 3.0 - -config USB_XHCI_MTK_QUIRK - bool "Support for USB xHCI controllers on MTK SoC" - depends on USB_XHCI - help - Select this option if you want to use USB 3.0 on MTK platform. - -config USB_DWC2 - bool "Support for USB DesignWare HCD controllers" - depends on USB - help - Select this option if you want to use DesignWare USB 2.0 host controller - -config USB_HID - bool "Support for USB keyboards" - depends on USB - default y - help - Select this option if you want to use devices complying to the - USB HID (Human Interface Device) standard. Such devices are for - example keyboards and mice. Currently only keyboards are supported. - Say Y here unless you know exactly what you are doing. - -config USB_HUB - bool "Support for USB hubs" - depends on USB - default y - help - Select this option if you want to compile in support for USB hubs. - Say Y here unless you know exactly what you are doing. - -config USB_EHCI_HOSTPC_ROOT_HUB_TT - bool "Support for USB EHCI ROOT HUB that has TT" - depends on USB_EHCI - default n - help - Select this option if USB EHCI root hub supports TT (Transaction - Translator). - To support this TT feature we read port-speed from non-standard - register HOSTPC (offset 84h of Operational Register base). - -config USB_MSC - bool "Support for USB storage" - depends on USB - default y - help - Select this option if you want to compile in support for USB mass - storage devices (USB memory sticks, hard drives, CDROM/DVD drives) - Say Y here unless you know exactly what you are doing. - -config USB_GEN_HUB - bool - default n if (!USB_HUB && !USB_XHCI) - default y if (USB_HUB || USB_XHCI) -config USB_PCI - bool "Auto-scan PCI bus for USB host controllers" - depends on USB - default y if ARCH_X86 - default n - -config UDC - bool "USB device mode support" - default n - help - Select this option to add support for running as - a USB device. - -config UDC_CI - bool "ChipIdea driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for ChipIdea - USB device controller. - -config UDC_DWC2 - bool "Designware driver for USB device mode" - depends on UDC - default n - help - Select this option to add the driver for Designware - USB device controller. +source "drivers/timer/Kconfig" +source "drivers/storage/Kconfig" +source "drivers/usb/Kconfig" endmenu diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig new file mode 100644 index 0000000..961144e --- /dev/null +++ b/payloads/libpayload/drivers/storage/Kconfig @@ -0,0 +1,59 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config STORAGE + bool "Support for storage devices" + default y + help + Select this option if you want support for storage devices (like + hard drives, memory sticks or optical drives). + +config STORAGE_64BIT_LBA + bool "Use 64-bit integers to address sectors" + depends on STORAGE + default n + help + If this is selected, sectors will be addressed by an 64-bit integer. + Select this to support LBA-48 for ATA drives. + +config STORAGE_ATA + bool "Support ATA drives (i.e. hard drives)" + depends on STORAGE + default y + help + Select this option if you want support for ATA storage devices + (i.e. hard drives). + +config STORAGE_ATAPI + bool "Support ATAPI drives (i.e. optical drives)" + depends on STORAGE + default y + select STORAGE_ATA + help + Select this option if you want support for ATAPI storage devices + (i.e. optical drives like CD or DVD drives). + +config STORAGE_AHCI + bool "Support for AHCI host controllers" + depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI + default y + help + Select this option if you want support for SATA controllers in + AHCI mode. + +config STORAGE_AHCI_ONLY_TESTED + bool "Only enable tested controllers" + depends on STORAGE_AHCI + default y + help + If this option is selected only AHCI controllers which are known + to work will be used. diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig new file mode 100644 index 0000000..8f047fa --- /dev/null +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +config TIMER_RDTSC + bool + default y + depends on ARCH_X86 + +choice + prompt "Timer driver" + default TIMER_NONE + depends on !ARCH_X86 + +config TIMER_NONE + bool "None" + help + The timer driver is provided by the payload itself. + +config TIMER_MCT + bool "Exynos MCT" + +config TIMER_TEGRA_1US + bool "Tegra 1us" + +config TIMER_IPQ806X + bool "Timer for ipq806x platforms" + +config TIMER_ARMADA38X + bool "Timer for armada38x platforms" + help + This is the timer driver for marvell armada38x + platforms. + +config TIMER_IPQ40XX + bool "Timer for ipq40xx platforms" + help + This is the timer driver for QCA IPQ40xx based + platforms. + +config TIMER_RK + bool "Timer for Rockchip" + +config TIMER_BG4CD + bool "Marvell BG4CD" + +config TIMER_CYGNUS + bool "Timer for Cygnus" + +config TIMER_IMG_PISTACHIO + bool "Timer for IMG Pistachio" + +config TIMER_MTK + bool "Timer for MediaTek MT8173" + +endchoice + +config TIMER_MCT_HZ + int "Exynos MCT frequency" + depends on TIMER_MCT + default 24000000 + +config TIMER_MCT_ADDRESS + hex "Exynos MCT base address" + depends on TIMER_MCT + default 0x101c0000 + +config TIMER_RK_ADDRESS + hex "Rockchip timer base address" + depends on TIMER_RK + default 0xff810020 + +config TIMER_TEGRA_1US_ADDRESS + hex "Tegra u1s timer base address" + depends on TIMER_TEGRA_1US + default 0x60005010 + +config IPQ806X_TIMER_FREQ + int "Hardware timer frequency" + default 32000 + depends on TIMER_IPQ806X + help + IPQ hardware presently provides a single timer running at 32KHz, a + finer granulariry timer is available but is not yet enabled. + +config IPQ806X_TIMER_REG + hex "Timer register address" + default 0x0200A008 + depends on TIMER_IPQ806X + help + Address of the register to read a free running timer value. + +config ARMADA38X_TIMER_FREQ + int "Hardware timer frequency" + depends on TIMER_ARMADA38X + default 25000000 + +config ARMADA38X_TIMER_REG + hex "Timer register address" + default 0xF1020314 + depends on TIMER_ARMADA38X + +config IPROC_PERIPH_GLB_TIM_REG_BASE + hex "Cygnus timer base address" + depends on TIMER_CYGNUS + default 0x19020200 + +config TIMER_MTK_HZ + int "MediaTek GPT frequency" + depends on TIMER_MTK + default 13000000 + help + Clock frequency of MediaTek General Purpose Timer. + +config TIMER_MTK_ADDRESS + hex "MTK GPT register address" + depends on TIMER_MTK + default 0x10008048 + help + Address of GPT4's counter register to read the FREERUN-mode timer value. + diff --git a/payloads/libpayload/drivers/usb/Kconfig b/payloads/libpayload/drivers/usb/Kconfig new file mode 100644 index 0000000..e1b68f7 --- /dev/null +++ b/payloads/libpayload/drivers/usb/Kconfig @@ -0,0 +1,129 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config USB + bool "USB Support" + default y + +config USB_UHCI + bool "Support for USB UHCI controllers" + depends on USB && ARCH_X86 + default y + help + Select this option if you are going to use USB 1.1 on an Intel based + system. + +config USB_OHCI + bool "Support for USB OHCI controllers" + depends on USB + default y + help + Select this option if you are going to use USB 1.1 on a non-Intel based + system. + +config USB_EHCI + bool "Support for USB EHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 2.0 + +config USB_XHCI + bool "Support for USB xHCI controllers" + depends on USB + default y + help + Select this option if you want to use USB 3.0 + +config USB_XHCI_MTK_QUIRK + bool "Support for USB xHCI controllers on MTK SoC" + depends on USB_XHCI + help + Select this option if you want to use USB 3.0 on MTK platform. + +config USB_DWC2 + bool "Support for USB DesignWare HCD controllers" + depends on USB + help + Select this option if you want to use DesignWare USB 2.0 host controller + +config USB_HID + bool "Support for USB keyboards" + depends on USB + default y + help + Select this option if you want to use devices complying to the + USB HID (Human Interface Device) standard. Such devices are for + example keyboards and mice. Currently only keyboards are supported. + Say Y here unless you know exactly what you are doing. + +config USB_HUB + bool "Support for USB hubs" + depends on USB + default y + help + Select this option if you want to compile in support for USB hubs. + Say Y here unless you know exactly what you are doing. + +config USB_EHCI_HOSTPC_ROOT_HUB_TT + bool "Support for USB EHCI ROOT HUB that has TT" + depends on USB_EHCI + default n + help + Select this option if USB EHCI root hub supports TT (Transaction + Translator). + To support this TT feature we read port-speed from non-standard + register HOSTPC (offset 84h of Operational Register base). + +config USB_MSC + bool "Support for USB storage" + depends on USB + default y + help + Select this option if you want to compile in support for USB mass + storage devices (USB memory sticks, hard drives, CDROM/DVD drives) + Say Y here unless you know exactly what you are doing. + +config USB_GEN_HUB + bool + default n if (!USB_HUB && !USB_XHCI) + default y if (USB_HUB || USB_XHCI) +config USB_PCI + bool "Auto-scan PCI bus for USB host controllers" + depends on USB + default y if ARCH_X86 + default n + +config UDC + bool "USB device mode support" + default n + help + Select this option to add support for running as + a USB device. + +config UDC_CI + bool "ChipIdea driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for ChipIdea + USB device controller. + +config UDC_DWC2 + bool "Designware driver for USB device mode" + depends on UDC + default n + help + Select this option to add the driver for Designware + USB device controller. +

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New patch to review for coreboot: src/device: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15943 -gerrit commit 913f9a19555b18302350d4fec4cb9d42417c07aa Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:31:40 2016 +0200 src/device: Capitalize CPU, RAM and ROM Change-Id: I133531391a20261e0926524d70c0901079076af9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/device/cpu_device.c | 2 +- src/device/oprom/realmode/x86_asm.S | 2 +- src/device/oprom/yabel/debug.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index 072d7c6..ccbe6ec 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -22,7 +22,7 @@ device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) struct device_path cpu_path; device_t cpu; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = apic_id; diff --git a/src/device/oprom/realmode/x86_asm.S b/src/device/oprom/realmode/x86_asm.S index b90aaa4..2bb2a3f 100644 --- a/src/device/oprom/realmode/x86_asm.S +++ b/src/device/oprom/realmode/x86_asm.S @@ -143,7 +143,7 @@ __realmode_call: mov %ax, %ds lidt __realmode_idt - /* initialize registers for option rom lcall */ + /* initialize registers for option ROM lcall */ movl __registers + 0, %eax movl __registers + 4, %ebx movl __registers + 8, %ecx diff --git a/src/device/oprom/yabel/debug.h b/src/device/oprom/yabel/debug.h index 60d4c47..b1a8600 100644 --- a/src/device/oprom/yabel/debug.h +++ b/src/device/oprom/yabel/debug.h @@ -71,7 +71,7 @@ static inline void set_ci(void) {}; * ||||||||||-DEBUG_PRINT_INT10 - let INT10 (i.e. character output) calls print messages to Debug output * |||||||||||-DEBUG_INTR - Print messages related to interrupt handling * ||||||||||||-DEBUG_CHECK_VMEM_ACCESS - Print messages related to accesse to certain areas of the virtual Memory (e.g. BDA (BIOS Data Area) or Interrupt Vectors) - * |||||||||||||-DEBUG_MEM - Print memory access made by option rom (NOTE: this also includes accesses to fetch instructions) + * |||||||||||||-DEBUG_MEM - Print memory access made by option ROM (NOTE: this also includes accesses to fetch instructions) * ||||||||||||||-DEBUG_IO - Print I/O access made by option rom * 11000111111111 - Max Binary Value, Debug All (WARNING: - This could run for hours) */

1 0

New patch to review for coreboot: src/include: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15942 -gerrit commit a72c48109b55b84f88c285f20b8d1b824ab167c0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:25:21 2016 +0200 src/include: Capitalize CPU, RAM and ROM Change-Id: Id40c1bf868820c77ea20146d19c6d552c2f970c4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/include/cbfs.h | 2 +- src/include/console/post_codes.h | 6 +++--- src/include/cpu/x86/cache.h | 2 +- src/include/cpu/x86/mp.h | 12 ++++++------ src/include/cpu/x86/msr.h | 2 +- src/include/cpu/x86/mtrr.h | 2 +- src/include/cpu/x86/smm.h | 8 ++++---- src/include/gic.h | 2 +- src/include/rmodule.h | 2 +- 9 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d19218..6d9dd42 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -23,7 +23,7 @@ * Perform CBFS operations on the boot device. * ***********************************************/ -/* Return mapping of option rom found in boot device. NULL on error. */ +/* Return mapping of option ROM found in boot device. NULL on error. */ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); /* Load stage by name into memory. Returns entry address on success. NULL on * failure. */ diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 8e47905..c7722e5 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -82,14 +82,14 @@ #define POST_ENTRY_C_START 0x13 /** - * \brief Pre call to ram stage main() + * \brief Pre call to RAM stage main() * - * POSTed right before ram stage main() is called from c_start.S + * POSTed right before RAM stage main() is called from c_start.S */ #define POST_PRE_HARDWAREMAIN 0x79 /** - * \brief Entry into coreboot in ram stage main() + * \brief Entry into coreboot in RAM stage main() * * This is the first call in hardwaremain.c. If this code is POSTed, then * ramstage has successfully loaded and started executing. diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 9c1af29..a446bbe 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -52,7 +52,7 @@ static inline void invd(void) /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * ram, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9742df0..cea3139 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -59,9 +59,9 @@ struct mp_ops { void (*get_microcode_info)(const void **microcode, int *parallel); /* * Optionally provide a function which adjusts the APIC id - * map to cpu number. By default the cpu number and APIC id - * are 1:1. To change the APIC id for a given cpu return the - * new APIC id. It's called for each cpu as indicated by + * map to CPU number. By default the CPU number and APIC id + * are 1:1. To change the APIC id for a given CPU return the + * new APIC id. It's called for each CPU as indicated by * get_cpu_count(). */ int (*adjust_cpu_apic_entry)(int cpu, int cur_apic_id); @@ -78,7 +78,7 @@ struct mp_ops { void (*adjust_smm_params)(struct smm_loader_params *slp, int is_perm); /* * Optionally provide a callback prior to the APs starting SMM - * relocation or cpu driver initialization. However, note that + * relocation or CPU driver initialization. However, note that * this callback is called after SMM handlers have been loaded. */ void (*pre_mp_smm_init)(void); @@ -88,11 +88,11 @@ struct mp_ops { */ void (*per_cpu_smm_trigger)(void); /* - * This function is called while each cpu is in the SMM relocation + * This function is called while each CPU is in the SMM relocation * handler. Its primary purpose is to adjust the SMBASE for the * permanent handler. The parameters passed are the current cpu * running the relocation handler, current SMBASE of relocation handler, - * and the pre-calculated staggered cpu SMBASE address of the permanent + * and the pre-calculated staggered CPU SMBASE address of the permanent * SMM handler. */ void (*relocation_handler)(int cpu, uintptr_t curr_smbase, diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index d644edd..151c9dc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -48,7 +48,7 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as - * ram, the cache as ram stack can no longer be used. Called + * ram, the cache as RAM stack can no longer be used. Called * functions must be inlined to avoid stack usage. Also, the * compiler must keep local variables register based and not * allocated them from the stack. With gcc 4.5.0, some functions diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d09c77e..f32bece 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -91,7 +91,7 @@ int get_free_var_mtrr(void); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) -/* At the end of romstage, low ram 0..CACHE_TM_RAMTOP may be set +/* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set * as write-back cacheable to speed up ramstage decompression. * Note MTRR boundaries, must be power of two. */ diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 2b13f8c..c1051ad 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -491,8 +491,8 @@ u16 smm_get_pmbase(void); struct smm_runtime { u32 smbase; u32 save_state_size; - /* The apic_id_to_cpu provides a mapping from APIC id to cpu number. - * The cpu number is indicated by the index into the array by matching + /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. + * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader * initializes this array with a 1:1 mapping. If the APIC ids are not * contiguous like the 1:1 mapping it is up to the caller of the stub @@ -525,7 +525,7 @@ void *smm_get_save_state(int cpu); /* The smm_loader_params structure provides direction to the SMM loader: * - stack_top - optional external stack provided to loader. It must be at * least per_cpu_stack_size * num_concurrent_stacks in size. - * - per_cpu_stack_size - stack size per cpu for smm modules. + * - per_cpu_stack_size - stack size per CPU for smm modules. * - num_concurrent_stacks - number of concurrent cpus in handler needing stack * optional for setting up relocation handler. * - per_cpu_save_state_size - the smm save state size per cpu @@ -537,7 +537,7 @@ void *smm_get_save_state(int cpu); * the address of the module's parameters (if present). * - runtime - this field is a result only. The SMM runtime location is filled * into this field so the code doing the loading can manipulate the - * runtime's assumptions. e.g. updating the apic id to cpu map to + * runtime's assumptions. e.g. updating the apic id to CPU map to * handle sparse apic id space. */ struct smm_loader_params { diff --git a/src/include/gic.h b/src/include/gic.h index 1ac1eab..f7339a4 100644 --- a/src/include/gic.h +++ b/src/include/gic.h @@ -26,7 +26,7 @@ void gic_enable(void); /* Return a pointer to the base of the GIC distributor mmio region. */ void *gicd_base(void); -/* Return a pointer to the base of the GIC cpu mmio region. */ +/* Return a pointer to the base of the GIC CPU mmio region. */ void *gicc_base(void); #else /* CONFIG_GIC */ diff --git a/src/include/rmodule.h b/src/include/rmodule.h index c0c062c..c5de9c3 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -40,7 +40,7 @@ int rmodule_load_alignment(const struct rmodule *m); /* rmodule_calc_region() calculates the region size, offset to place an * rmodule in memory, and load address offset based off of a region allocator * with an alignment of region_alignment. This function helps place an rmodule - * in the same location in ram it will run from. The offset to place the + * in the same location in RAM it will run from. The offset to place the * rmodule into the region allocated of size region_size is returned. The * load_offset is the address to load and relocate the rmodule. * region_alignment must be a power of 2. */

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Patch merged into coreboot/master: soc/intel/apollolake: Update FSP Header files for version 146_30
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit df12d1923f76576534bbdfe69e2fd56d9c820faf Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jul 22 12:25:40 2016 -0700 soc/intel/apollolake: Update FSP Header files for version 146_30 Add new UPDs for Fspm and Fsps. Update headers to make new UPDs available for use. New UPDs enable various memory and trace funtionality options as well as support for zero sized IBB region. BUG=chrome-os-partner:55513 BRANCH=none TEST=built and tested with no regressions Change-Id: Id1573baaa306ed4fe4353df5f27e5963cb1a76e6 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://review.coreboot.org/15815 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15815 for details. -gerrit

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New patch to review for coreboot: src/southbridge: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15941 -gerrit commit 94af5b617ecfdb159b1a55f708013ecb49e0a49f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:20:04 2016 +0200 src/southbridge: Capitalize CPU, RAM and ROM Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/cimx/sb700/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb800/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/bootblock.c | 4 ++-- src/southbridge/amd/cimx/sb900/bootblock.c | 4 ++-- src/southbridge/amd/cs5535/chipsetinit.c | 2 +- src/southbridge/amd/cs5536/cs5536.c | 2 +- src/southbridge/amd/pi/hudson/lpc.c | 2 +- src/southbridge/amd/rs690/early_setup.c | 2 +- src/southbridge/amd/rs690/rs690.c | 2 +- src/southbridge/amd/rs780/early_setup.c | 2 +- src/southbridge/amd/rs780/rs780.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sm.c | 2 +- src/southbridge/amd/sr5650/early_setup.c | 2 +- src/southbridge/amd/sr5650/sr5650.c | 4 ++-- src/southbridge/intel/bd82x6x/early_me.c | 2 +- src/southbridge/intel/i82371eb/fadt.c | 4 ++-- 18 files changed, 23 insertions(+), 23 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 7be1dc5..61dded8 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c index 3cf647b..2f67a36 100644 --- a/src/southbridge/amd/cimx/sb700/bootblock.c +++ b/src/southbridge/amd/cimx/sb700/bootblock.c @@ -45,7 +45,7 @@ static void sb700_enable_rom(void) dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; pci_io_write_config32(dev, 0x48, dword); - /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ /* Set the 4MB enable bits */ word = pci_io_read_config16(dev, 0x6c); word = 0xFFC0; @@ -54,6 +54,6 @@ static void sb700_enable_rom(void) static void bootblock_southbridge_init(void) { - /* Setup the rom access for 2M */ + /* Setup the ROM access for 2M */ sb700_enable_rom(); } diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 78be023..5748f79 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -214,7 +214,7 @@ config SB800_IMC_FAN_CONTROL depends on SB800_IMC_FWM help Set up the SB800 to use the IMC based Fan controller. This requires - the IMC rom from AMD. Configure the registers in devicetree.cb. + the IMC ROM from AMD. Configure the registers in devicetree.cb. endchoice diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index cbf6918..89e56b6 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -44,7 +44,7 @@ static void enable_rom(void) dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); pci_io_write_config32(dev, 0x48, dword); - /* Enable rom access */ + /* Enable ROM access */ word = pci_io_read_config16(dev, 0x6c); word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); pci_io_write_config16(dev, 0x6c, word); @@ -107,7 +107,7 @@ static void enable_clocks(void) static void bootblock_southbridge_init(void) { - /* Setup the rom access for 2M */ + /* Setup the ROM access for 2M */ enable_rom(); enable_prefetch(); enable_spi_fast_mode(); diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c index cf81724..50d3087 100644 --- a/src/southbridge/amd/cimx/sb900/bootblock.c +++ b/src/southbridge/amd/cimx/sb900/bootblock.c @@ -44,7 +44,7 @@ static void sb900_enable_rom(void) dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ; pci_io_write_config32(dev, 0x48, dword); - /* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */ + /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */ /* Set the 4MB enable bits */ word = pci_io_read_config16(dev, 0x6c); word = 0xFFC0; @@ -53,6 +53,6 @@ static void sb900_enable_rom(void) static void bootblock_southbridge_init(void) { - /* Setup the rom access for 2M */ + /* Setup the ROM access for 2M */ sb900_enable_rom(); } diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..05fb6eb 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -310,7 +310,7 @@ chipsetinit(void) outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); /* Allow IO read and writes during a ATA DMA operation. */ - /* This could be done in the HD rom but do it here for easier debugging. */ + /* This could be done in the HD ROM but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 4651257..345752e 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -560,7 +560,7 @@ void chipsetinit(void) outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT); /* Allow IO read and writes during a ATA DMA operation. */ - /* This could be done in the HD rom but do it here for easier debugging. */ + /* This could be done in the HD ROM but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 057058b..9f01020 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; diff --git a/src/southbridge/amd/rs690/early_setup.c b/src/southbridge/amd/rs690/early_setup.c index 7e17807..ec14073 100644 --- a/src/southbridge/amd/rs690/early_setup.c +++ b/src/southbridge/amd/rs690/early_setup.c @@ -279,7 +279,7 @@ static void rs690_por_pcicfg_init(device_t nb_dev) /* Power Management Register Enable */ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80); - /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1); diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c index 453dd80..f0c8134 100644 --- a/src/southbridge/amd/rs690/rs690.c +++ b/src/southbridge/amd/rs690/rs690.c @@ -116,7 +116,7 @@ static u32 get_vid_did(device_t dev) * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by cpu in hypertransport.c line458, +* case 0 will be called twice, one is by CPU in hypertransport.c line458, * the other is by rs690. ***********************************************/ void rs690_enable(device_t dev) diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index ca8d79a..da98d51 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -419,7 +419,7 @@ static void rs780_por_pcicfg_init(device_t nb_dev) /* Power Management Register Enable */ set_nbcfg_enable_bits_8(nb_dev, 0x84, (u8)(~0xFF), 0x80); - /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ set_nbcfg_enable_bits_8(nb_dev, 0x4C, (u8)(~0x00), 0x42 | 1); diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index 6eb4295..c2da54d 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -262,7 +262,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by cpu in hypertransport.c line458, +* case 0 will be called twice, one is by CPU in hypertransport.c line458, * the other is by rs780. ***********************************************/ void rs780_enable(device_t dev) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 18d4471..3ba47a0 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -59,7 +59,7 @@ static void lpc_init(device_t dev) interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 8488d71..ba9e806 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -83,7 +83,7 @@ static void sm_init(device_t dev) printk(BIOS_INFO, "sm_init().\n"); /* Don't rename APIC ID */ - /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. + /* TODO: We should call setup_ioapic() here. But kernel hangs if CPU is K8. * We need to check out why and change back. */ clear_ioapic(VIO_APIC_VADDR); //setup_ioapic(IO_APIC_ADDR, 0); diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 1fc0427..a96b127 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -343,7 +343,7 @@ static void sr5650_por_pcicfg_init(device_t nb_dev) set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0); set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010); - /* Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + /* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge * Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation * BMMsgEn */ set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 818b0e6..d28adfc 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -564,7 +564,7 @@ void sr5650_nb_pci_table(device_t nb_dev) printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); - //Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge + //Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge //Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation pci_write_config8(nb_dev, 0x4c, 0x42); temp8 = pci_read_config8(nb_dev, 0x4e); @@ -605,7 +605,7 @@ void sr5650_nb_pci_table(device_t nb_dev) * 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2 * 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1 -* case 0 will be called twice, one is by cpu in hypertransport.c line458, +* case 0 will be called twice, one is by CPU in hypertransport.c line458, * the other is by sr5650. ***********************************************/ void sr5650_enable(device_t dev) diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 62ea0c5..8fc72b8 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -156,7 +156,7 @@ int intel_early_me_init_done(u8 status) printk(BIOS_NOTICE, "ME: Current PM event: 0x%x\n", (me_fws2 & 0xf000000) >> 24); printk(BIOS_NOTICE, "ME: Progress code : 0x%x\n", (me_fws2 & 0xf0000000) >> 28); - // Poll cpu replaced for 50ms + // Poll CPU replaced for 50ms millisec = 0; while ((((me_fws2 & 0x100) >> 8) == 0) && millisec < 50) { udelay(1000); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index 9d0e15c..b77ed4a 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -78,11 +78,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->cst_cnt = 0; /* smi command to indicate c state changed notification */ fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */ fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */ - fadt->flush_size = 0; /* only needed if cpu wbinvd is broken */ + fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */ fadt->flush_stride = 0; fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */ fadt->duty_width = 3; /* this width is in bits */ - fadt->day_alrm = 0x0d; /* rtc cmos ram offset */ + fadt->day_alrm = 0x0d; /* rtc cmos RAM offset */ fadt->mon_alrm = 0x0; /* not supported */ fadt->century = 0x0; /* not supported */ /*

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coreboot-gerrit July 2016