coreboot-gerrit July 2016

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Patch set updated for coreboot: src/northbridge: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15940 -gerrit commit 2328c9e2a6f64b859140d5a8b9e993aa2d8ca7bb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:05:26 2016 +0200 src/northbridge: Capitalize CPU, RAM and ROM Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdht/h3finit.c | 6 +++--- src/northbridge/amd/amdk8/coherent_ht.c | 6 +++--- src/northbridge/amd/amdk8/early_ht.c | 2 +- src/northbridge/amd/amdk8/f.h | 2 +- src/northbridge/amd/amdk8/incoherent_ht.c | 4 ++-- src/northbridge/amd/amdk8/raminit.c | 6 +++--- src/northbridge/amd/amdk8/raminit_f.c | 4 ++-- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridge.c | 4 ++-- src/northbridge/amd/lx/northbridgeinit.c | 2 +- src/northbridge/intel/e7501/northbridge.c | 2 +- src/northbridge/intel/e7505/northbridge.c | 2 +- src/northbridge/intel/gm45/early_reset.c | 2 +- src/northbridge/intel/haswell/Kconfig | 2 +- src/northbridge/intel/i3100/northbridge.c | 2 +- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i855/northbridge.c | 2 +- src/northbridge/intel/i855/raminit.c | 2 +- src/northbridge/intel/i945/raminit.c | 4 ++-- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- src/northbridge/via/cx700/lpc.c | 4 ++-- src/northbridge/via/vx800/lpc.c | 8 ++++---- src/northbridge/via/vx800/northbridge.c | 2 +- src/northbridge/via/vx800/uma_ram_setting.c | 2 +- src/northbridge/via/vx900/northbridge.c | 2 +- 26 files changed, 41 insertions(+), 41 deletions(-) diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 1199a50..3e59a32 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -41,7 +41,7 @@ static void enumerate_ht_chain(void) if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 6a45f10..bfda13d 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -917,7 +917,7 @@ static void lookupComputeAndLoadRoutingTables(sMainData *pDat) * * Description: * Find the total number of cores and update the number of nodes and cores in all cpus. - * Limit cpu config access to installed cpus. + * Limit CPU config access to installed cpus. * * Parameters: * @param[in] sMainData* pDat = our global state, number of nodes discovered. @@ -1357,12 +1357,12 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i+1].SelRegang = FALSE; if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ for (j = i+2; j < pDat->TotalLinks*2; j += 2) { if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) continue; /* Links must be from the same source */ diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8779ec7..a7c3fc2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) static void disable_probes(void) { /* disable read/write/fill probes for uniprocessor setup - * they don't make sense if only one cpu is available + * they don't make sense if only one CPU is available */ /* Hypetransport Transaction Control Register @@ -1597,7 +1597,7 @@ static void coherent_ht_finalize(unsigned nodes) } #endif - /* set up cpu count and node count and enable Limit + /* set up CPU count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range * registers on Hammer A0 revision. @@ -1622,7 +1622,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif pci_write_config32(dev, 0x60, val); - /* Only respond to real cpu pci configuration cycles + /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b..1bc34e4 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -8,7 +8,7 @@ static void enumerate_ht_chain(void) /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index af4658d..f83282b 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -535,7 +535,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if(sysinfo->nodes == 1) return; // in case only one CPU installed for(i=1; i<sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d765fc7..12b8290 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -481,7 +481,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ @@ -631,7 +631,7 @@ static int ht_setup_chains(uint8_t ht_c_num) #endif { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index fbcb887..f502287 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -859,7 +859,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1243,7 +1243,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; @@ -2476,7 +2476,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //FIXME add enable node interleaving here -- yhlu /*needed? - 1. check how many nodes we have , if not all has ram installed get out + 1. check how many nodes we have , if not all has RAM installed get out 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index cd4b9fb..8ed0335 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index efbe51e..f21d717 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -538,7 +538,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 0ff7917..2ba4a04 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -46,7 +46,7 @@ #define WRITE_COMBINE (1<<4) #define WRITE_SERIALIZE (1<<5) -/* ram has none of this stuff */ +/* RAM has none of this stuff */ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) @@ -86,7 +86,7 @@ struct msr_defaults { /* for 180a, for now, we assume VSM will configure it */ /* 180b is left at reset value,a0000-bffff is non-cacheable */ /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ + /* oops, 180c will be set by CPU bug handling in cpubug.c */ //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 08259f8..6c48fb4 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -591,7 +591,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..5296bdb 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -69,7 +69,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the limit of the remap window */ remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, 0xc4); diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..4a3e993 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the limit of the remap window */ remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, TOLM); diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index b24e3a6..c987cb3 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -64,6 +64,6 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Perform system reset through CF9 interface. */ outb(0x02, 0xcf9); /* Set system reset bit. */ - outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ + outb(0x06, 0xcf9); /* Set CPU reset bit, too. */ halt(); } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5e59233..b15f933 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -65,7 +65,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x2000 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config HAVE_MRC bool "Add a System Agent binary" diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 10e57f4..8d37f38 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the offset of the remap window from tolm */ remapoffsetk = remapbasek - tolmk; } - /* Write the ram configruation registers, + /* Write the RAM configruation registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, 0xc4); diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index b69efbc..443716f 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -603,7 +603,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; - /* Test if we can read the spd and if ram is ddr or ddr2 */ + /* Test if we can read the spd and if RAM is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { printk(BIOS_ERR, "No memory for this cpu\n"); diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index aba1966..e9b1cac 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 63ee98b..4789663 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -878,7 +878,7 @@ static void spd_update(u8 reg, u32 new_value) #endif } -/* if ram still doesn't work do this function */ +/* if RAM still doesn't work do this function */ static void spd_set_undocumented_registers(void) { spd_update(0x74, 0x00000001); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 59a31de..5469059 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -85,7 +85,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command) static void ram_read32(u32 offset) { - PRINTK_DEBUG(" ram read: %08x\n", offset); + PRINTK_DEBUG(" RAM read: %08x\n", offset); read32((void *)offset); } @@ -1453,7 +1453,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno val_err: die("Bad SPD value\n"); hw_err: - /* If a hardware error occurs the spd rom probably does not exist. + /* If a hardware error occurs the spd ROM probably does not exist. * In this case report that there is no memory */ sz.side1 = 0; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4ac7f3d..421763c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1121,7 +1121,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) gfxstolenbase -= tsegbasedelta; toludbase -= tsegbasedelta; - // Test if it is possible to reclaim a hole in the ram addressing + // Test if it is possible to reclaim a hole in the RAM addressing if (tom - me_uma_size > toludbase) { // Reclaim is possible reclaim = 1; @@ -4080,7 +4080,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, /* Set scheduler parameters */ MCHBAR32(0x4c20) = 0x10100005; - /* Set cpu specific register */ + /* Set CPU specific register */ set_4f8c(); /* Clear IO reset bit */ diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index ece05b1..2d74316 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -203,7 +203,7 @@ static void cx700_set_lpc_registers(struct device *dev) enables |= 1 << 3; pci_write_config8(dev, 0x4d, enables); - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); @@ -220,7 +220,7 @@ static void cx700_set_lpc_registers(struct device *dev) // Power management setup setup_pm(dev); - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); /* Enable HPET timer */ diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 25ceed1..00c1999 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -269,7 +269,7 @@ static void vx800_sb_init(struct device *dev) enables |= 0x41; // pci_write_config8(dev, 0x58, enables); - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); @@ -283,7 +283,7 @@ static void vx800_sb_init(struct device *dev) // Power management setup setup_pm(dev); - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); // Start the rtc @@ -329,14 +329,14 @@ static void southbridge_init(struct device *dev) S3_usb_wakeup(dev); S3_lid_wakeup(dev); -/* enable acpi cpu c3 state. (c2 state need not do anything.) +/* enable acpi CPU c3 state. (c2 state need not do anything.) #1 fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 fadt->p_lvl2_lat = 0x50; //this is the coreboot source fadt->p_lvl3_lat = 0x320;// fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 - ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) + ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 4925b53..6391321 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -70,7 +70,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { /* - * the order is important to find the correct ram size. + * the order is important to find the correct RAM size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; device_t mc_dev; diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index dc3ab39..1aa0967 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -168,7 +168,7 @@ void SetUMARam(void) Tmp = VIACONFIG_VGA_PCI_14; pci_write_config32(vga_dev, 0x14, Tmp); - //enable direct cpu frame buffer access + //enable direct CPU frame buffer access i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i); diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 368ff8c..32bb539 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -259,7 +259,7 @@ static void vx900_set_resources(device_t dev) tolmk = MIN(full_tolmk, tomk); tolmk -= fbufk; ram_resource(dev, idx++, 0, 640); - printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10); + printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10); /* FIXME: how can we avoid leaving this hole? * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem

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New patch to review for coreboot: src/northbridge: Capitalize CPU, RAM and ROM
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15940 -gerrit commit 20b23fd45f7bdcd07ee84c51ca8f0ce5f859443c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 21:05:26 2016 +0200 src/northbridge: Capitalize CPU, RAM and ROM Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdfam10/early_ht.c | 2 +- src/northbridge/amd/amdht/h3finit.c | 6 +++--- src/northbridge/amd/amdk8/coherent_ht.c | 6 +++--- src/northbridge/amd/amdk8/early_ht.c | 2 +- src/northbridge/amd/amdk8/f.h | 3 ++- src/northbridge/amd/amdk8/incoherent_ht.c | 4 ++-- src/northbridge/amd/amdk8/raminit.c | 6 +++--- src/northbridge/amd/amdk8/raminit_f.c | 4 ++-- src/northbridge/amd/gx2/northbridgeinit.c | 2 +- src/northbridge/amd/lx/northbridge.c | 4 ++-- src/northbridge/amd/lx/northbridgeinit.c | 2 +- src/northbridge/intel/e7501/northbridge.c | 2 +- src/northbridge/intel/e7505/northbridge.c | 2 +- src/northbridge/intel/gm45/early_reset.c | 2 +- src/northbridge/intel/haswell/Kconfig | 2 +- src/northbridge/intel/i3100/northbridge.c | 2 +- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i855/northbridge.c | 2 +- src/northbridge/intel/i855/raminit.c | 2 +- src/northbridge/intel/i945/raminit.c | 4 ++-- src/northbridge/intel/sandybridge/raminit.c | 4 ++-- src/northbridge/via/cx700/lpc.c | 4 ++-- src/northbridge/via/vx800/lpc.c | 8 ++++---- src/northbridge/via/vx800/northbridge.c | 2 +- src/northbridge/via/vx800/uma_ram_setting.c | 2 +- src/northbridge/via/vx900/northbridge.c | 2 +- 26 files changed, 42 insertions(+), 41 deletions(-) diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 1199a50..3e59a32 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -41,7 +41,7 @@ static void enumerate_ht_chain(void) if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 6a45f10..bfda13d 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -917,7 +917,7 @@ static void lookupComputeAndLoadRoutingTables(sMainData *pDat) * * Description: * Find the total number of cores and update the number of nodes and cores in all cpus. - * Limit cpu config access to installed cpus. + * Limit CPU config access to installed cpus. * * Parameters: * @param[in] sMainData* pDat = our global state, number of nodes discovered. @@ -1357,12 +1357,12 @@ static void regangLinks(sMainData *pDat) pDat->PortList[i+1].SelRegang = FALSE; if ( (pDat->PortList[i].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[i+1].Type != PORTLIST_TYPE_CPU)) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ for (j = i+2; j < pDat->TotalLinks*2; j += 2) { if ( (pDat->PortList[j].Type != PORTLIST_TYPE_CPU) || (pDat->PortList[j+1].Type != PORTLIST_TYPE_CPU) ) - continue; /* Only process cpu to cpu links */ + continue; /* Only process CPU to CPU links */ if (pDat->PortList[i].NodeID != pDat->PortList[j].NodeID) continue; /* Links must be from the same source */ diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 8779ec7..a7c3fc2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -113,7 +113,7 @@ static inline void print_linkn (const char *strval, uint8_t byteval) static void disable_probes(void) { /* disable read/write/fill probes for uniprocessor setup - * they don't make sense if only one cpu is available + * they don't make sense if only one CPU is available */ /* Hypetransport Transaction Control Register @@ -1597,7 +1597,7 @@ static void coherent_ht_finalize(unsigned nodes) } #endif - /* set up cpu count and node count and enable Limit + /* set up CPU count and node count and enable Limit * Config Space Range for all available CPUs. * Also clear non coherent hypertransport bus range * registers on Hammer A0 revision. @@ -1622,7 +1622,7 @@ static void coherent_ht_finalize(unsigned nodes) #endif pci_write_config32(dev, 0x60, val); - /* Only respond to real cpu pci configuration cycles + /* Only respond to real CPU pci configuration cycles * and optimize the HT settings */ val=pci_read_config32(dev, HT_TRANSACTION_CONTROL); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6449f4b..1bc34e4 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -8,7 +8,7 @@ static void enumerate_ht_chain(void) /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index af4658d..f71ceef 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -535,7 +535,8 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo) unsigned needs_reset = 0; - if(sysinfo->nodes == 1) return; // in case only one cpu installed + if (sysinfo->nodes == 1) + return; // in case only one CPU installed for(i=1; i<sysinfo->nodes; i++) { /* Skip everything if I don't have any memory on this controller */ diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index d765fc7..12b8290 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -481,7 +481,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ @@ -631,7 +631,7 @@ static int ht_setup_chains(uint8_t ht_c_num) #endif { /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. - * On most boards this just happens. If a cpu has multiple + * On most boards this just happens. If a CPU has multiple * non Coherent links the appropriate bus registers for the * links needs to be programed to point at bus 0. */ diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index fbcb887..f502287 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -859,7 +859,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1243,7 +1243,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma ((dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; @@ -2476,7 +2476,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) //FIXME add enable node interleaving here -- yhlu /*needed? - 1. check how many nodes we have , if not all has ram installed get out + 1. check how many nodes we have , if not all has RAM installed get out 2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out 3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out 4. if all ready enable node_interleaving in f1 0x40..... of every node diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index cd4b9fb..8ed0335 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1054,7 +1054,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) } /* Leave a 64M hole between TOP_MEM and TOP_MEM2 - * so I can see my rom chip and other I/O devices. + * so I can see my ROM chip and other I/O devices. */ if (tom_k >= 0x003f0000) { #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1460,7 +1460,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i ((meminfo->dimm_mask >> DIMM_SOCKETS) & ((1 << DIMM_SOCKETS) - 1))) { goto single_channel; } - /* If the cpu is not capable of doing dual channels don't do dual channels */ + /* If the CPU is not capable of doing dual channels don't do dual channels */ nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); if (!(nbcap & NBCAP_128Bit)) { goto single_channel; diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c index efbe51e..f21d717 100644 --- a/src/northbridge/amd/gx2/northbridgeinit.c +++ b/src/northbridge/amd/gx2/northbridgeinit.c @@ -538,7 +538,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 0ff7917..2ba4a04 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -46,7 +46,7 @@ #define WRITE_COMBINE (1<<4) #define WRITE_SERIALIZE (1<<5) -/* ram has none of this stuff */ +/* RAM has none of this stuff */ #define RAM_PROPERTIES (0) #define DEVICE_PROPERTIES (WRITE_SERIALIZE|CACHE_DISABLE) #define ROM_PROPERTIES (WRITE_SERIALIZE|WRITE_PROTECT|CACHE_DISABLE) @@ -86,7 +86,7 @@ struct msr_defaults { /* for 180a, for now, we assume VSM will configure it */ /* 180b is left at reset value,a0000-bffff is non-cacheable */ /* 180c, c0000-dffff is set to write serialize and non-cachable */ - /* oops, 180c will be set by cpu bug handling in cpubug.c */ + /* oops, 180c will be set by CPU bug handling in cpubug.c */ //{0x180c, {.hi = MSR_WS_CD_DEFAULT, .lo = MSR_WS_CD_DEFAULT}}, /* 180d is left at default, e0000-fffff is non-cached */ /* we will assume 180e, the ssm region configuration, is left at default or set by VSM */ diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c index 08259f8..6c48fb4 100644 --- a/src/northbridge/amd/lx/northbridgeinit.c +++ b/src/northbridge/amd/lx/northbridgeinit.c @@ -591,7 +591,7 @@ static void rom_shadow_settings(void) * * DEVRC_RCONF_DEFAULT: * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. * SYSTOP(27:8) = top of system memory * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 64bf840..5296bdb 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -69,7 +69,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the limit of the remap window */ remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, 0xc4); diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 08cd023..4a3e993 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -65,7 +65,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the limit of the remap window */ remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16)); } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, TOLM); diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index b24e3a6..c987cb3 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -64,6 +64,6 @@ void gm45_early_reset(void/*const timings_t *const timings*/) /* Perform system reset through CF9 interface. */ outb(0x02, 0xcf9); /* Set system reset bit. */ - outb(0x06, 0xcf9); /* Set cpu reset bit, too. */ + outb(0x06, 0xcf9); /* Set CPU reset bit, too. */ halt(); } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 5e59233..b15f933 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -65,7 +65,7 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE default 0x2000 help The amount of anticipated stack usage from the data cache - during pre-ram rom stage execution. + during pre-ram ROM stage execution. config HAVE_MRC bool "Add a System Agent binary" diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 10e57f4..8d37f38 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -93,7 +93,7 @@ static void pci_domain_set_resources(device_t dev) /* Find the offset of the remap window from tolm */ remapoffsetk = remapbasek - tolmk; } - /* Write the ram configruation registers, + /* Write the RAM configruation registers, * preserving the reserved bits. */ tolm_r = pci_read_config16(mc_dev, 0xc4); diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index b69efbc..443716f 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -603,7 +603,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) { long dimm_mask; - /* Test if we can read the spd and if ram is ddr or ddr2 */ + /* Test if we can read the spd and if RAM is ddr or ddr2 */ dimm_mask = spd_detect_dimms(ctrl); if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { printk(BIOS_ERR, "No memory for this cpu\n"); diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index aba1966..e9b1cac 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -87,7 +87,7 @@ static void pci_domain_set_resources(device_t dev) */ tolmk = tomk; } - /* Write the ram configuration registers, + /* Write the RAM configuration registers, * preserving the reserved bits. */ diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 63ee98b..4789663 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -878,7 +878,7 @@ static void spd_update(u8 reg, u32 new_value) #endif } -/* if ram still doesn't work do this function */ +/* if RAM still doesn't work do this function */ static void spd_set_undocumented_registers(void) { spd_update(0x74, 0x00000001); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 59a31de..5469059 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -85,7 +85,7 @@ static __attribute__((noinline)) void do_ram_command(u32 command) static void ram_read32(u32 offset) { - PRINTK_DEBUG(" ram read: %08x\n", offset); + PRINTK_DEBUG(" RAM read: %08x\n", offset); read32((void *)offset); } @@ -1453,7 +1453,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno val_err: die("Bad SPD value\n"); hw_err: - /* If a hardware error occurs the spd rom probably does not exist. + /* If a hardware error occurs the spd ROM probably does not exist. * In this case report that there is no memory */ sz.side1 = 0; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4ac7f3d..421763c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -1121,7 +1121,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) gfxstolenbase -= tsegbasedelta; toludbase -= tsegbasedelta; - // Test if it is possible to reclaim a hole in the ram addressing + // Test if it is possible to reclaim a hole in the RAM addressing if (tom - me_uma_size > toludbase) { // Reclaim is possible reclaim = 1; @@ -4080,7 +4080,7 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, /* Set scheduler parameters */ MCHBAR32(0x4c20) = 0x10100005; - /* Set cpu specific register */ + /* Set CPU specific register */ set_4f8c(); /* Clear IO reset bit */ diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index ece05b1..2d74316 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -203,7 +203,7 @@ static void cx700_set_lpc_registers(struct device *dev) enables |= 1 << 3; pci_write_config8(dev, 0x4d, enables); - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); @@ -220,7 +220,7 @@ static void cx700_set_lpc_registers(struct device *dev) // Power management setup setup_pm(dev); - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); /* Enable HPET timer */ diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 25ceed1..00c1999 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -269,7 +269,7 @@ static void vx800_sb_init(struct device *dev) enables |= 0x41; // pci_write_config8(dev, 0x58, enables); - /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ + /* Set bit 3 of 0x4f to match award (use INIT# as CPU reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); @@ -283,7 +283,7 @@ static void vx800_sb_init(struct device *dev) // Power management setup setup_pm(dev); - /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ + /* set up isa bus -- i/o recovery time, ROM write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); // Start the rtc @@ -329,14 +329,14 @@ static void southbridge_init(struct device *dev) S3_usb_wakeup(dev); S3_lid_wakeup(dev); -/* enable acpi cpu c3 state. (c2 state need not do anything.) +/* enable acpi CPU c3 state. (c2 state need not do anything.) #1 fadt->pm2_cnt_blk = 0x22;//to support cpu-c3 fadt->p_lvl2_lat = 0x50; //this is the coreboot source fadt->p_lvl3_lat = 0x320;// fadt->pm2_cnt_len = 1;//to support cpu-c3 #2 - ssdt? ->every cpu has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) + ssdt? ->every CPU has a P_BLK address. set it to 0x10 (so that "Read Processor Level3 register(PMIORx15<7:0>) to enter C3 state"---VIA vx800 P SPEC ) #3 write 0x17 in to PMIO=VX800_ACPI_IO_BASE + 0x26, following the describtion in the P-spec. 1 enable SLP# asserts in C3 state PMIORx26<1> =1 2 enable CPUSTP# asserts in C3 state; PMIORx26<2> =1 diff --git a/src/northbridge/via/vx800/northbridge.c b/src/northbridge/via/vx800/northbridge.c index 4925b53..6391321 100644 --- a/src/northbridge/via/vx800/northbridge.c +++ b/src/northbridge/via/vx800/northbridge.c @@ -70,7 +70,7 @@ static const struct pci_driver memctrl_driver __pci_driver = { static void pci_domain_set_resources(device_t dev) { /* - * the order is important to find the correct ram size. + * the order is important to find the correct RAM size. */ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; device_t mc_dev; diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c index dc3ab39..1aa0967 100644 --- a/src/northbridge/via/vx800/uma_ram_setting.c +++ b/src/northbridge/via/vx800/uma_ram_setting.c @@ -168,7 +168,7 @@ void SetUMARam(void) Tmp = VIACONFIG_VGA_PCI_14; pci_write_config32(vga_dev, 0x14, Tmp); - //enable direct cpu frame buffer access + //enable direct CPU frame buffer access i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i); diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 368ff8c..32bb539 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -259,7 +259,7 @@ static void vx900_set_resources(device_t dev) tolmk = MIN(full_tolmk, tomk); tolmk -= fbufk; ram_resource(dev, idx++, 0, 640); - printk(BIOS_SPEW, "System ram left: %dMB\n", tolmk >> 10); + printk(BIOS_SPEW, "System RAM left: %dMB\n", tolmk >> 10); /* FIXME: how can we avoid leaving this hole? * Leave a hole for VGA, 0xa0000 - 0xc0000 ?? */ /* TODO: VGA Memory hole can be disabled in SNMIC. Upper 64k of ROM seem

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Patch set updated for coreboot: src/cpu: Capitalize CPU
by HAOUAS Elyes 28 Jul '16

28 Jul '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15934 -gerrit commit 4aec34dc352ed2f9ae62d9bb8ffbc7da09ab1c23 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Jul 28 18:58:27 2016 +0200 src/cpu: Capitalize CPU Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 8 ++++---- src/cpu/amd/pi/00630F01/model_15_init.c | 2 +- src/cpu/amd/pi/00660F01/model_15_init.c | 2 +- src/cpu/amd/pi/00730F01/model_16_init.c | 2 +- src/cpu/dmp/vortex86ex/biosdata_ex.S | 4 ++-- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 8 ++++---- src/cpu/intel/haswell/haswell_init.c | 2 +- src/cpu/intel/hyperthreading/intel_sibling.c | 8 ++++---- src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 4 ++-- src/cpu/intel/model_f3x/model_f3x_init.c | 4 ++-- src/cpu/intel/model_f4x/model_f4x_init.c | 4 ++-- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 4 ++-- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 16 ++++++++-------- src/cpu/x86/mp_init.c | 12 ++++++------ src/cpu/x86/sipi_vector.S | 4 ++-- src/cpu/x86/smm/smm_module_loader.c | 8 ++++---- src/cpu/x86/smm/smm_stub.S | 8 ++++---- src/cpu/x86/smm/smmrelocate.S | 4 ++-- 54 files changed, 102 insertions(+), 102 deletions(-) diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 12dab91..22a92e1 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -57,7 +57,7 @@ static void model_10_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 8fdd62c..a0b9479 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -62,7 +62,7 @@ static void model_12_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 159ea02..84ce755 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -82,7 +82,7 @@ static void model_14_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index d035f5e..525959f 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -67,7 +67,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c index 2c71d3e..0492be3 100644 --- a/src/cpu/amd/agesa/family15rl/model_15_init.c +++ b/src/cpu/amd/agesa/family15rl/model_15_init.c @@ -81,7 +81,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 77357e9..27aedaf 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -80,7 +80,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index bf7e3bf..3d3afec 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -79,7 +79,7 @@ static void model_16_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0edded2..6fefc3b 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -257,7 +257,7 @@ uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2) continue; if ((readback & 0x3f) == state || (readback & 0x3f) == state2 || (readback & 0x3f) == F10_APSTATE_RESET) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 153fb10..a41374d 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -133,7 +133,7 @@ static void model_10xxx_init(device_t dev) enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Set the processor name string */ diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..b6bad4d 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic(); vsm_end_post_smi(); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index 6638a83..cf8c2e2 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -75,7 +75,7 @@ static void disablememoryreadorder(void) wrmsr(MC_CF8F_DATA, msr); } -/* For cpu version C3. Should be the only released version */ +/* For CPU version C3. Should be the only released version */ void cpubug(void) { pcideadlock(); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index 5cda46b..335caa3 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -40,7 +40,7 @@ static void geode_lx_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic(); // do VSA late init diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 03415d1..9e6dfa0 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -401,7 +401,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) 0) continue; if (((readback >> 24) & 0xff) == apicid) - break; /* it is this cpu turn */ + break; /* it is this CPU turn */ } if (loop > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 51e1b7c..2ea4fb9 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -157,7 +157,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state) continue; if ((readback & 0xff) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { @@ -303,7 +303,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait - lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started if (apicid != bsp_apicid) { u32 timeout = 1; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index cf0b08a..e22eae4 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -249,15 +249,15 @@ static void init_ecc_memory(unsigned node_id) f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); if (!f1_dev) { - die("Cannot find cpu function 1\n"); + die("Cannot find CPU function 1\n"); } f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2)); if (!f2_dev) { - die("Cannot find cpu function 2\n"); + die("Cannot find CPU function 2\n"); } f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3)); if (!f3_dev) { - die("Cannot find cpu function 3\n"); + die("Cannot find CPU function 3\n"); } /* See if we scrubbing should be enabled */ @@ -508,7 +508,7 @@ static void model_fxx_init(device_t dev) /* Set the processor name string */ init_processor_name(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 42afae3..7c4d171 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -79,7 +79,7 @@ static void model_15_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 8fe6340..de7ee38 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -94,7 +94,7 @@ static void model_15_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 00a21e9..6cb3009 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -77,7 +77,7 @@ static void model_16_init(device_t dev) } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); #if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S index 5ed17c6..2defe63 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.S +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -24,8 +24,8 @@ DDR3 CPU/DRAM/PCI B6 B7 BB BC BD BF 200/200/33 30 03 0F 02 8F 07 300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable +300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable 300/300/100 48 03 23 02 7F 07 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing 400/200/100 60 43 23 02 4F 07 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index bd39039..536b40e 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other CPU files are included. # # Therefore: ONLY include Makefile.inc from socket directories! diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 05c5bb1..3093975 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -34,7 +34,7 @@ static void ep80579_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index da1ea2b..50d2bee 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -334,7 +334,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -343,7 +343,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -353,7 +353,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -386,7 +386,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 17c46b3..b457453 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -133,7 +133,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -142,7 +142,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -152,7 +152,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -182,7 +182,7 @@ static void model_406dx_init(struct device *cpu) x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 74147ab..799b66c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -720,7 +720,7 @@ static void haswell_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 678ad2d..de59c18 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -21,7 +21,7 @@ #include <assert.h> #if CONFIG_PARALLEL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init +#error Intel hyper-threading requires serialized CPU init #endif static int first_time = 1; @@ -84,16 +84,16 @@ void intel_sibling_init(struct device *cpu) return; } - /* I am the primary cpu start up my siblings */ + /* I am the primary CPU start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; - /* Allocate new cpu device structure iff sibling CPU + /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ new = alloc_find_dev(cpu->bus, &cpu_path); diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 7452973..f589430 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,5 @@ ################################################################################ -## One small file with the awesome super-power of updating the cpu microcode +## One small file with the awesome super-power of updating the CPU microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0242a44..1812084 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -322,7 +322,7 @@ static void model_1067x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Initialize the APIC timer */ @@ -347,7 +347,7 @@ static void model_1067x_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(tm2, quad); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 82552d8..ac4606b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -124,7 +124,7 @@ static void model_106cx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -138,7 +138,7 @@ static void model_106cx_init(struct device *cpu) /* TODO: PIC thermal sensor control */ - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 4005b3d..4bcab2a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -329,13 +329,13 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + (i % threads_per_core) + ((i / threads_per_core) << 2); - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -345,7 +345,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -379,7 +379,7 @@ static void model_2065x_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7575603..1b875f6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -520,7 +520,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -529,7 +529,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -539,7 +539,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -572,7 +572,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 3cce098..14da632 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -36,7 +36,7 @@ static void model_65x_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 631e3515..d7c22fc 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -40,7 +40,7 @@ static void model_67x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3adee6f..e276791 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -44,7 +44,7 @@ static void model_68x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 214673a..d283722 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -18,7 +18,7 @@ static void model_69x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b2e5585..36da288 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -44,7 +44,7 @@ static void model_6bx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 04b73ad..73f71d8 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -31,7 +31,7 @@ static void model_6dx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6fa6d3a..bc926a8 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -154,7 +154,7 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -169,7 +169,7 @@ static void model_6ex_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 6cd2b12..30542e6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -177,7 +177,7 @@ static void model_6fx_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); /* Enable virtualization */ @@ -192,7 +192,7 @@ static void model_6fx_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); } diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 0f0df22..102af74 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -31,7 +31,7 @@ static void model_6xx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index 94c73ce..1eb234f 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -31,7 +31,7 @@ static void model_f0x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index 259d7f6..77f442f 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -31,7 +31,7 @@ static void model_f1x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 6b847c0..092afa0 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -36,10 +36,10 @@ static void model_f2x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index e85427d..36ca5a6 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -36,10 +36,10 @@ static void model_f3x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 6211209..7d198b3 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -36,10 +36,10 @@ static void model_f4x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); - /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 66cfbca..c28766e 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -27,7 +27,7 @@ static void c3_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 9b558e9..e7c9fac 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -200,7 +200,7 @@ static void c7_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }; @@ -209,7 +209,7 @@ static struct device_operations cpu_dev_ops = { }; /* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact - * ID, the cpu mask (stepping) is masked out and the check is repeated. This + * ID, the CPU mask (stepping) is masked out and the check is repeated. This * allows us to keep the table significantly smaller. */ diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index fdd8b7e..cdf0589 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -180,7 +180,7 @@ static void nano_init(struct device *dev) /* Set up Memory Type Range Registers */ x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); } diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index be5b730..4c0d323 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -54,7 +54,7 @@ _start16bit: * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. - * If you cpu needs it you can write a cpu dependent version of + * If you CPU needs it you can write a CPU dependent version of * entry16.inc. */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 77e5ba8..1abc28f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -242,10 +242,10 @@ static int lapic_start_cpu(unsigned long apicid) static atomic_t active_cpus = ATOMIC_INIT(1); /* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic + * Only starting one CPU at a time let's me remove the logic * for select the stack from assembly language. * - * In addition communicating by variables to the cpu I + * In addition communicating by variables to the CPU I * am starting allows me to verify it has started before * start_cpu returns. */ @@ -301,12 +301,12 @@ int start_cpu(struct device *cpu) cpu->enabled = 0; cpu->initialized = 0; - /* Start the cpu */ + /* Start the CPU */ result = lapic_start_cpu(apicid); if (result) { result = 0; - /* Wait 1s or until the new cpu calls in */ + /* Wait 1s or until thenew CPU calls in */ for(count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; @@ -542,23 +542,23 @@ void initialize_cpus(struct bus *cpu_bus) struct device_path cpu_path; struct cpu_info *info; - /* Find the info struct for this cpu */ + /* Find the info struct for this CPU */ info = cpu_info(); #if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ enable_lapic(); - /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else - /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; #endif - /* Find the device structure for the boot cpu */ + /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path); #if CONFIG_SMP && CONFIG_MAX_CPUS > 1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index b9084c7..ff32015 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -375,7 +375,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) struct device *new; int apic_id; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; /* Assuming linear APIC space allocation. */ @@ -385,10 +385,10 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) } cpu_path.apic.apic_id = apic_id; - /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); if (new == NULL) { - printk(BIOS_CRIT, "Could not allocate cpu device\n"); + printk(BIOS_CRIT, "Could not allocate CPU device\n"); max_cpus--; } cpus[i].dev = new; @@ -577,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) * * The MP initialization has the following properties: * 1. APs are brought up in parallel. - * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. + * 2. The ordering of coreboot CPU number and APIC ids is not deterministic. * Therefore, one cannot rely on this property or the order of devices in * the device tree unless the chipset or mainboard know the APIC ids * a priori. @@ -641,7 +641,7 @@ static void mp_initialize_cpu(void) cpu_initialize(info->index); } -/* Returns apic id for coreboot cpu number or < 0 on failure. */ +/* Returns apic id for coreboot CPU number or < 0 on failure. */ static int mp_get_apic_id(int cpu_slot) { if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0) @@ -843,7 +843,7 @@ static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(NULL, load_smm_handlers), /* Perform SMM relocation. */ MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), - /* Initialize each cpu through the driver framework. */ + /* Initialize each CPU through the driver framework. */ MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish everything else then let them park. */ MP_FR_BLOCK_APS(NULL, NULL), diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 985b9da..2bcce88 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -93,7 +93,7 @@ _start: mov idt_ptr, %ebx lidt (%ebx) - /* Obtain cpu number. */ + /* Obtain CPU number. */ movl ap_count, %eax 1: movl %eax, %ecx @@ -107,7 +107,7 @@ _start: movl stack_top, %edx subl %eax, %edx mov %edx, %esp - /* Save cpu number. */ + /* Save CPU number. */ mov %ecx, %esi /* Determine if one should check microcode versions. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 853923d..09ddb03 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -48,7 +48,7 @@ extern unsigned char _binary_smmstub_start[]; /* This is the SMM handler that the stub calls. It is encoded as an rmodule. */ extern unsigned char _binary_smm_start[]; -/* Per cpu minimum stack size. */ +/* Per CPU minimum stack size. */ #define SMM_MINIMUM_STACK_SIZE 32 /* @@ -75,7 +75,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, struct smm_entry_ins entry = { .jmp_rel = 0xe9 }; /* Each entry point has an IP value of 0x8000. The SMBASE for each - * cpu is different so the effective address of the entry instruction + * CPU is different so the effective address of the entry instruction * is different. Therefore, the relative displacement for each entry * instruction needs to be updated to reflect the current effective * IP. Additionally, the IP result from the jmp instruction is @@ -126,7 +126,7 @@ static void *smm_stub_place_stacks(char *base, int size, } /* Place the staggered entry points for each CPU. The entry points are - * staggered by the per cpu SMM save state size extending down from + * staggered by the per CPU SMM save state size extending down from * SMM_ENTRY_OFFSET. */ static void smm_stub_place_staggered_entry_points(char *base, const struct smm_loader_params *params, const struct rmodule *smm_stub) @@ -260,7 +260,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) stub_params->runtime.smbase = (u32)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; - /* Initialize the APIC id to cpu number table to be 1:1 */ + /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) stub_params->runtime.apic_id_to_cpu[i] = i; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 564b200..d1fe7c1 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -40,15 +40,15 @@ smbase: .long 0 save_state_size: .long 0 -/* apic_to_cpu_num is a table mapping the default APIC id to cpu num. If the - * APIC id is found at the given index, the contiguous cpu number is index +/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the + * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ apic_to_cpu_num: .fill CONFIG_MAX_CPUS,1,0xff /* end struct smm_runtime */ .data -/* Provide fallback stack to use when a valid cpu number cannot be found. */ +/* Provide fallback stack to use when a valid CPU number cannot be found. */ fallback_stack_bottom: .skip 128 fallback_stack_top: @@ -112,7 +112,7 @@ smm_trampoline32: inc %ecx cmp $CONFIG_MAX_CPUS, %ecx jne 1b - /* This is bad. One cannot find a stack entry because a cpu num could + /* This is bad. One cannot find a stack entry because a CPU num could * not be assigned. Use the fallback stack and check this condition in * C handler. */ movl $(fallback_stack_top), %esp diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 128b694..2502df8 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -89,7 +89,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 CPU cores before * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. @@ -167,7 +167,7 @@ smm_relocate: outb %al, %dx movb $'-', %al outb %al, %dx - /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ + /* calculate ascii of CPU number. More than 9 cores? -> FIXME */ movb %cl, %al addb $'0', %al outb %al, %dx

1 0

New patch to review for coreboot: intel/apollolake & skylake: Move EC_SOFTWARE_SYNC to platforms
by Martin Roth 28 Jul '16

28 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15939 -gerrit commit 014905302f59ebd74f9f368b8b1148e3fe2a0447 Author: Martin Roth <martinroth(a)chromium.org> Date: Thu Jul 28 12:43:47 2016 -0600 intel/apollolake & skylake: Move EC_SOFTWARE_SYNC to platforms Move the EC_SOFTWARE_SYNC option out of the SOC directory and into the platform Kconfigs, to match all the other chrome platforms. Change-Id: I7a9f220f5555a497a18b204d6dd3bdb7fdca0282 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- src/mainboard/google/chell/Kconfig | 1 + src/mainboard/google/glados/Kconfig | 1 + src/mainboard/google/lars/Kconfig | 1 + src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/intel/amenia/Kconfig | 1 + src/mainboard/intel/kunimitsu/Kconfig | 1 + src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 3 +-- 8 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/chell/Kconfig b/src/mainboard/google/chell/Kconfig index 5ed211a..00943af 100644 --- a/src/mainboard/google/chell/Kconfig +++ b/src/mainboard/google/chell/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config CHROMEOS select LID_SWITCH + select EC_SOFTWARE_SYNC config DRIVERS_I2C_GENERIC def_bool y diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index 3acb8e9..e1d4411 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config CHROMEOS select LID_SWITCH + select EC_SOFTWARE_SYNC config DRIVERS_I2C_GENERIC def_bool y diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index c602523..830c5a2 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config CHROMEOS select LID_SWITCH + select EC_SOFTWARE_SYNC config DRIVERS_GENERIC_MAX98357A default y diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5fafa8b..2cac9b7 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -12,6 +12,9 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select SYSTEM_TYPE_LAPTOP +config CHROMEOS + select EC_SOFTWARE_SYNC + config BOOT_MEDIA_SPI_BUS int default 0 diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 2a4189e..93aa41f 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select LID_SWITCH + select EC_SOFTWARE_SYNC config MAINBOARD_DIR string diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d2e6951..d575aae 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config CHROMEOS select LID_SWITCH + select EC_SOFTWARE_SYNC config DRIVERS_GENERIC_MAX98357A default y diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 0745679..0b4c4d7 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -59,7 +59,6 @@ config CPU_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC select SEPARATE_VERSTAGE select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index bbffd17..40bad03 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -54,8 +54,7 @@ config CPU_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC - select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC - select VBOOT_EC_SLOW_UPDATE + select VBOOT_EC_SLOW_UPDATE if EC_SOFTWARE_SYNC select VBOOT_OPROM_MATTERS select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT select VBOOT_VBNV_CMOS

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Patch set updated for coreboot: google/lars & intel/kunimitsu: Disable EC build
by Martin Roth 28 Jul '16

28 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15869 -gerrit commit 47d445cd6590d116db72fbbe60f206eea8a5778e Author: Martin Roth <martinroth(a)google.com> Date: Tue Jul 26 12:08:12 2016 -0600 google/lars & intel/kunimitsu: Disable EC build The Chrome EC codebase no longer supports the google/lars and intel/kunimitsu boards. Disable the build in those platforms. Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/lars/Kconfig | 10 +--------- src/mainboard/intel/kunimitsu/Kconfig | 9 +-------- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/lars/Kconfig b/src/mainboard/google/lars/Kconfig index 830c5a2..41333b0 100644 --- a/src/mainboard/google/lars/Kconfig +++ b/src/mainboard/google/lars/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD + select EC_EXTERNAL_FIRMWARE select EXCLUDE_NATIVE_SD_INTERFACE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -22,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy config CHROMEOS select LID_SWITCH - select EC_SOFTWARE_SYNC config DRIVERS_GENERIC_MAX98357A default y @@ -70,14 +70,6 @@ config INCLUDE_NHLT_BLOBS select NHLT_MAX98357 select NHLT_NAU88L25 -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "lars" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "lars_pd" - config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index d575aae..fa650b0 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC_LPC select EC_GOOGLE_CHROMEEC_MEC select EC_GOOGLE_CHROMEEC_PD + select EC_EXTERNAL_FIRMWARE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -71,14 +72,6 @@ config INCLUDE_NHLT_BLOBS select NHLT_NAU88L25 select NHLT_SSM4567 -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "kunimitsu" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "kunimitsu_pd" - config GBB_HWID string depends on CHROMEOS

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Patch set updated for coreboot: intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal
by Venkateswarlu V Vinjamuri 28 Jul '16

28 Jul '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15777 -gerrit commit 613481b14e67c9729f6a578c6fddac072b5f2738 Author: Shankar, Vaibhav <vaibhav.shankar(a)intel.com> Date: Mon Jul 18 12:07:34 2016 -0700 intel/amenia: Add GPIO changes to assert SLP_S0/Reset signal PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar(a)intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/mainboard/intel/amenia/gpio.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index a3b7611..d79ddcf 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ - PAD_CFG_NF(PMU_SLP_S0_B, NONE, DEEP, NF1), /* PMU_SLP_S0_N */ + PAD_CFG_NF_IOSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), /* PMU_SLP_S0_N */ PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ @@ -164,7 +164,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(PMC_SPI_CLK, DN_20K), /* PMC_SPI_CLK */ /* PMIC */ PAD_NC(PMIC_PWRGOOD, NONE), /* PMIC_PWRGOOD */ - PAD_NC(PMIC_RESET_B, NONE), /* PMIC_RESET_B */ + PAD_CFG_NF_IOSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE), /* PMIC_RESET_B */ PAD_NC(GPIO_213, NONE), /* PMIC_SDWN_B */ PAD_NC(GPIO_214, DN_20K), /* PMIC_BCUDISW2 */ PAD_NC(GPIO_215, DN_20K), /* PMIC_BCUDISCRIT */

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Patch set updated for coreboot: soc/intel/apollolake: Add iosstate macros for GPIO
by Venkateswarlu V Vinjamuri 28 Jul '16

28 Jul '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15776 -gerrit commit b7c0e7e49f0df3f0183720c0d27af2ca588cc665 Author: Shankar, Vaibhav <vaibhav.shankar(a)intel.com> Date: Wed Jul 13 14:00:08 2016 -0700 soc/intel/apollolake: Add iosstate macros for GPIO IO Standby State (IOSSTATE): The I/O Standby State defines which state the pad should be parked in when the I/O is in a standby state. Iosstate set to 15 means IO-Standby is ignored for this pin (same as functional mode), So that pin keeps on functioning in S3/S0iX. Change-Id: Ie51ff86a2ea63fa6535407fcc2df7a137ee43e8b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar(a)intel.com> --- src/soc/intel/apollolake/gpio.c | 12 +++++++++++- src/soc/intel/apollolake/include/soc/gpio.h | 6 ++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 3 +++ 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index a3ffb3d..2440b1a 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -85,10 +85,20 @@ static void gpio_configure_itss(const struct pad_config *cfg, void gpio_configure_pad(const struct pad_config *cfg) { + uint32_t dw1; const struct pad_community *comm = gpio_get_community(cfg->pad); uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); + + /* Iostandby bits are tentatively stored in [3:0] bits(RO) of config1. + * dw1 is used to extract the bits of Iostandby. + * This is done to preserve config1 size as unit16 in gpio.h + */ + dw1 = cfg->config1; + dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_IGNORE_MASK) << PAD_CFG1_IOSSTATE_SET; + dw1 &= ~PAD_CFG1_IOSSTATE_IGNORE_MASK; + iosf_write(comm->port, config_offset, cfg->config0); - iosf_write(comm->port, config_offset + sizeof(uint32_t), cfg->config1); + iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1); gpio_configure_itss(cfg, comm->port, config_offset); } diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index 1ebac2d..61d1b74 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -28,6 +28,7 @@ typedef uint32_t gpio_t; #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_RESET_##value #define PAD_PULL(value) PAD_CFG1_PULL_##value +#define PAD_IOSSTATE(value) PAD_CFG1_IOSSTATE_##value #define PAD_IRQ_CFG(route, trig, inv) \ (PAD_CFG0_ROUTE_##route | \ PAD_CFG0_TRIG_##trig | \ @@ -44,6 +45,11 @@ typedef uint32_t gpio_t; #define PAD_CFG_NF(pad, pull, rst, func) \ _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull)) +/* Native function configuration for standby state */ +#define PAD_CFG_NF_IOSTATE(pad, pull, rst, func, iostate) \ + _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), (PAD_PULL(pull) | \ + PAD_IOSSTATE(iostate))) + /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 48e08e7..92c44ee 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -76,6 +76,7 @@ #define PAD_CFG0_RESET_RSMRST (3 << 30) #define PAD_CFG1_IRQ_MASK (0xff << 0) +#define PAD_CFG1_IOSSTATE_IGNORE (0xf << 0) /* Ignore Iostandby */ #define PAD_CFG1_PULL_MASK (0xf << 10) #define PAD_CFG1_PULL_NONE (0x0 << 10) #define PAD_CFG1_PULL_DN_5K (0x2 << 10) @@ -86,6 +87,8 @@ #define PAD_CFG1_PULL_UP_20K (0xc << 10) #define PAD_CFG1_PULL_UP_667 (0xd << 10) #define PAD_CFG1_PULL_NATIVE (0xf << 10) +#define PAD_CFG1_IOSSTATE_SET 14 /* set Ignore Iostandby */ +#define PAD_CFG1_IOSSTATE_IGNORE_MASK 0xf /* mask to extract Ignore Iostandby */ #define PAD_CFG_BASE 0x500 #define PAD_CFG_OFFSET(pad) (PAD_CFG_BASE + ((pad) * 8))

1 0

New patch to review for coreboot: build system: really disable building CrEC when not needed
by Martin Roth 28 Jul '16

28 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15938 -gerrit commit 42e8d5aa2a7bbbd3400544ea39c77e4d8810c3b8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu May 12 15:13:23 2016 +0200 build system: really disable building CrEC when not needed Enable users to set the EC_EXTERNAL_FIRMWARE config flag, and actively ignore anything related to EC firmware board names if enabled. BUG=none BRANCH=none CQ-DEPEND=CL:344540 TEST=emerge-samus coreboot works Change-Id: I02aa1e4bc0c98300105b83a12979e9368a40cbcf Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4f0b6fd10aa89fbb38bdebf14b8a82d52e9ee233 Original-Change-Id: I39c3038d059ec3d7710b864061fcf83b8d6d4d13 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345584 Original-Reviewed-by: Aaron Durbin <adurbin(a)google.com> Original-Commit-Queue: Martin Roth <martinroth(a)chromium.org> Original-Trybot-Ready: Martin Roth <martinroth(a)chromium.org> Original-Tested-by: Martin Roth <martinroth(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 3 ++- src/ec/google/chromeec/Makefile.inc | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 0e1b4f2..4d5de32 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -76,7 +76,8 @@ config EC_GOOGLE_CHROMEEC_SPI_CHIP config EC_EXTERNAL_FIRMWARE depends on EC_GOOGLE_CHROMEEC - def_bool n + bool "Disable building EC firmware" + default n help Disable building EC firmware if it's already built externally (and added manually.) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index aeb950f..761ab7f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -29,6 +29,7 @@ smm-$(CONFIG_VBOOT) += vboot_storage.c romstage-$(CONFIG_VBOOT) += vboot_storage.c verstage-$(CONFIG_VBOOT) += vboot_storage.c +ifneq ($(CONFIG_EC_EXTERNAL_FIRMWARE),y) # These are Chrome EC firmware images that a payload (such as depthcharge) can # use to update the EC. ecrw is the main embedded controller's firmware, # pdrw is for a USB PD controller. @@ -79,5 +80,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/%.hash: $(obj)/mainboard/$(MAINBOARDDIR)/% openssl dgst -sha256 -binary $< > $@ .PHONY: $(obj)/mainboard/$(MAINBOARDDIR)/ecrw $(obj)/mainboard/$(MAINBOARDDIR)/pdrw +endif endif

1 0

Patch merged into coreboot/master: Makefile: Include $(top) in DOTCONFIG definition to allow override
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit fde3275fb432128dcdd244f598e36692103c2433 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Sun Jul 24 12:25:07 2016 +0200 Makefile: Include $(top) in DOTCONFIG definition to allow override Including $(top) in the DOTCONFIG definition allows getting rid of the $(top) prefix in payloads, which in turns allows providing a full path for DOTCONFIG via the command line. Change-Id: I7546a12cf4a2a146e32fef81121f45f83ba67ac8 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: https://review.coreboot.org/15826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/15826 for details. -gerrit

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New patch to review for coreboot: oc/intel/apollolake: Enable ELOG for APL
by Brandon Breitenstein 28 Jul '16

28 Jul '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937 -gerrit commit 2c02344f998c334c682809c1a191cd143117ce1a Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Jul 18 15:14:12 2016 -0700 oc/intel/apollolake: Enable ELOG for APL add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for apollolake. Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 109 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 112 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..dc75859 --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + + /* PWR_FLR Power Failure */ + if (ps->gen_pmcon1 & PWR_FLR) + elog_add_event(ELOG_TYPE_POWER_FAIL); + + /* SUS Well Power Failure */ + if (ps->gen_pmcon1 & SUS_PWR_FLR) + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != 3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != SLEEP_STATE_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..aef255b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -138,6 +139,7 @@ #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5

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coreboot-gerrit July 2016