coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

Patch set updated for coreboot: soc/intel/apollolake: Enable ELOG for APL
by Brandon Breitenstein 29 Jul '16

29 Jul '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937 -gerrit commit 63dad4f5ca23dce6b4ce602c9c21e402dd0ec83d Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Jul 18 15:14:12 2016 -0700 soc/intel/apollolake: Enable ELOG for APL add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for apollolake. Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 101 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 104 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..a14bbbe --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. " + "Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..aef255b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -138,6 +139,7 @@ #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5

1 0

Patch merged into coreboot/master: skylake: fix VSDIO is at 0.8V when SDCard is not inserted
by gerrit＠coreboot.org 29 Jul '16

29 Jul '16

the following patch was just integrated into master: commit ce37e47f46e52090529a91a45d1c914d159643c8 Author: Zhuo-hao.Lee <zhuo-hao.lee(a)intel.com> Date: Wed Jul 27 13:18:22 2016 +0800 skylake: fix VSDIO is at 0.8V when SDCard is not inserted 1. Enable SoC SD_CMD/D* signals pull-down of 20k when SD-card is removed. When SD-card is disconnected, the pull-down is disabled. 2. Provide path for weak leakage from buffers of SD_CMD/D* signal to be grounded. Thus dropping voltage on the SD_CMD/D* signals to ~0V. BUG=chrome-os-partner:54421 TEST=no power leakage when SDCard isn't inserted on skylake platform Change-Id: I567199b172841125f8916a61a76005cfdaa62eb8 Signed-off-by: Zhuo-hao.Lee <zhuo-hao.lee(a)intel.com> Reviewed-on: https://review.coreboot.org/15910 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15910 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume
by gerrit＠coreboot.org 29 Jul '16

29 Jul '16

the following patch was just integrated into master: commit ec2947fb075838d1ea78754113aef6cf000cf522 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Thu Jul 14 18:43:54 2016 -0700 soc/intel/apollolake: Remove PEIM GFX from normal mode and S3 resume Do not pass VBT table to fsp in normal mode and S3 resume so that PEIM GFX will not get initialized. Change-Id: Iab7be3cceb0f80ae0273940b36fdd9c41bdb121e Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Reviewed-on: https://review.coreboot.org/14575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14575 for details. -gerrit

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable ELOG for APL
by Brandon Breitenstein 28 Jul '16

28 Jul '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15937 -gerrit commit 7f0a0f1ab9c4c766527292edd73f40ababd56078 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Jul 18 15:14:12 2016 -0700 soc/intel/apollolake: Enable ELOG for APL add in the base for ELOG for APL. Some PM events still need to be added but the basic events are logged here. This enables the basic functionality of ELOG for apollolake. Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/elog.c | 101 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pm.h | 2 + 3 files changed, 104 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e30df8..3ea2762 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -48,6 +48,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += elog.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c new file mode 100644 index 0000000..7294d22 --- /dev/null +++ b/src/soc/intel/apollolake/elog.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <stdint.h> +#include <elog.h> +#include <soc/pm.h> +#include <soc/pci_devs.h> + +static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) +{ + int i; + + gpe0_sts &= gpe0_en; + + for (i = 0; i <= 31; i++) { + if (gpe0_sts & (1 << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + } +} + +static void pch_log_wake_source(struct chipset_power_state *ps) +{ + /* Power Button */ + if (ps->pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + /* RTC */ + if (ps->pm1_en & RTC_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + /* PCI Express (TODO: determine wake device) */ + if (ps->pm1_en & PCIEXPWAK_DIS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + + /* Internal PME (TODO: determine wake device) */ + if (ps->gpe0_sts[PMC_GPE_NW_31_0] & PME_B0_EN) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + + + /* Log GPIO events in set 1-3 */ + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_31_0], ps->gpe0_en[PMC_GPE_SW_31_0], 0); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_63_32], ps->gpe0_en[PMC_GPE_SW_63_32], 32); + pch_log_gpio_gpe(ps->gpe0_sts[PMC_GPE_SW_95_64], ps->gpe0_en[PMC_GPE_SW_95_64], 64); +} + +static void pch_log_power_and_resets(struct chipset_power_state *ps) +{ + /* RTC Reset */ + if (ps->gen_pmcon2 & RPS) + elog_add_event(ELOG_TYPE_RTC_RESET); + + /* TCO Timeout */ + if (ps->prev_sleep_state != ACPI_S3 && + ps->tco_sts & TCO_TIMEOUT) + elog_add_event(ELOG_TYPE_TCO_RESET); + + /* Power Button Override */ + if (ps->pm1_sts & PRBTNOR_STS) + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + + /* ACPI Wake Event */ + if (ps->prev_sleep_state != ACPI_S0) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state); +} + +static void pch_log_state(void *unused) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_ERR, + "Not logging power state information. + Power state not found in cbmem.\n"); + return; + } + + /* Power and Reset */ + pch_log_power_and_resets(ps); + + /* Wake Sources */ + if (ps->prev_sleep_state > 0) + pch_log_wake_source(ps); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL); diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d8eb50b..aef255b 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -25,6 +25,7 @@ #define PM1_STS 0x00 #define WAK_STS (1 << 15) +#define PRBTNOR_STS (1 << 11) #define PWRBTN_STS (1 << 8) #define PM1_EN 0x02 @@ -138,6 +139,7 @@ #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 +#define PMC_GPE_SW_95_64 2 #define PMC_GPE_NW_31_0 3 #define PMC_GPE_NW_63_32 4 #define PMC_GPE_NW_95_64 5

1 0

Patch merged into coreboot/master: google/gru & kevin: Update DRAM configuration
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 3707fc2d961720152e7e96bc1606b893023cb577 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Jul 11 17:09:53 2016 +0800 google/gru & kevin: Update DRAM configuration We need to enable DRAM ODT on kevin/gru board to improve the DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms, the sdram VREF need to adjust to 840mv. This patch also makes following changes: 1. For compatiblity with the old board, add the "sdram-lpddr3-hynix-4GB-666-no-odt.inc" and "sdram-lpddr3-hynix-4GB-800-no-odt.inc" files which do not enable sdram ODT. 2. Delete the 300MHz dram inc file. The 300MHz sdram config just reduced 666MHz to 300MHz based on the 666MHz config file, and it is not stable, so delete it. 3. Delete the 928MHz dram inc file, 928MHz sdram config still in debuging, delete it for now. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358763 Original-Commit-Ready: Dan Shi <dshi(a)chromium.org> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/15813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15813 for details. -gerrit

1 0

Patch merged into coreboot/master: rockchip/rk3399: sdram: correct controller vref setting
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit df5ead9d2d01a03c4c3b00a1cb95c4e4b373bf1a Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Jul 7 19:29:55 2016 +0800 rockchip/rk3399: sdram: correct controller vref setting When enabling the controller ODT, the controller vref needs to correspond with the ODT value and DQ drive strength. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Original-Commit-Id: a7251c72b87d9f149b68d086c3252f1c668e0e80 Original-Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358762 Original-Commit-Ready: Dan Shi <dshi(a)chromium.org> Original-Tested-by: Caesar Wang <wxt(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Squashed with: rockchip/rk3399: Halt if we get an invalid odt or drv value When we were pushing the updated sdram.c to coreboot.org, the compiler there found that we were not initializing vref_value_dq in all code possible code paths. This patch updates those code paths to halt the system. Branch=none Bug=none Test=Built with coreboot.org toolchain and verified that the compile errors were gone. Change-Id: I0ad4207dc976236d64b6cdda58d10bcfbe1fde11 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362726 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I22a0cef6f12d9aae2ea4dcb99e7ebdd788f2cdd1 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Reviewed-on: https://review.coreboot.org/15812 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/15812 for details. -gerrit

1 0

New patch to review for coreboot: nvidia/tegra124: Adjust memlayout to Chrome OS toolchain
by Martin Roth 28 Jul '16

28 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15950 -gerrit commit bae906098bd62be43bd9a0d2878c28fd1fd8af81 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri May 20 14:50:38 2016 -0700 nvidia/tegra124: Adjust memlayout to Chrome OS toolchain The bootblock gets slightly too big, so adjust the space assigned to it. Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> BUG=none BRANCH=none TEST=emerge-nyan coreboot works again. Change-Id: Ib44d98692ae88c7cd3610c8e643d7d48ac858161 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 4b9038b018ed7a26fbce01d982b22166b328de37 Original-Change-Id: If494e49fb60c11e01ca780c84036ebf24459628c Original-Reviewed-on: https://chromium-review.googlesource.com/346492 Original-Reviewed-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Original-Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/soc/nvidia/tegra124/include/soc/memlayout.ld | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 5bab362..6e596f3 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -31,9 +31,9 @@ SECTIONS PRERAM_CBFS_CACHE(0x40006000, 16K) VBOOT2_WORK(0x4000A000, 16K) STACK(0x4000E000, 8K) - BOOTBLOCK(0x40010000, 24K) - VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 95K) + BOOTBLOCK(0x40010000, 26K) + VERSTAGE(0x40016800, 72K) + ROMSTAGE(0x40028800, 93K) TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000)

1 0

Patch merged into coreboot/master: drivers/intel/fsp2_0: Update the copyrights
by gerrit＠coreboot.org 28 Jul '16

28 Jul '16

the following patch was just integrated into master: commit 47bd2d957de614f52dc5392a5794a35c4941f8e3 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jul 24 18:12:16 2016 -0700 drivers/intel/fsp2_0: Update the copyrights Update the copyright dates in the FSP 2.0 files. Add a copyright to Kconfig. TEST=Build and run on Galileo Gen2 Change-Id: I0ad0c5650bde0e31d01a04bcc7d22a19273fe29b Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/15852 for details. -gerrit

1 0

New patch to review for coreboot: google/gale: Change board ID definition.
by Martin Roth 28 Jul '16

28 Jul '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15949 -gerrit commit d38b3950167f384c1e914b53a6df9bf249470c2e Author: Kan Yan <kyan(a)google.com> Date: Thu Jul 21 10:51:47 2016 -0700 google/gale: Change board ID definition. Change EVT3 board id to 5. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362391 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/gale/chromeos.c | 2 ++ src/soc/qualcomm/ipq40xx/include/soc/cdp.h | 7 ++++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 06b3d85..01f1e03 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -34,6 +34,7 @@ static int get_rec_sw_gpio_pin(void) { uint8_t board_rev = board_id(); switch (board_rev) { + case BOARD_ID_GALE_PROTO: case BOARD_ID_GALE_EVT: case BOARD_ID_GALE_EVT2: return 7; @@ -47,6 +48,7 @@ static int get_wp_status_gpio_pin(void) { uint8_t board_rev = board_id(); switch (board_rev) { + case BOARD_ID_GALE_PROTO: case BOARD_ID_GALE_EVT: case BOARD_ID_GALE_EVT2: return 6; diff --git a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h index e5ea828..1b21273 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/cdp.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/cdp.h @@ -134,9 +134,10 @@ typedef struct { #define IPQ_GMAC_NMACS 4 enum gale_board_id { - BOARD_ID_GALE_EVT = 0, - BOARD_ID_GALE_EVT2 = 1, - BOARD_ID_GALE_EVT3 = 2, + BOARD_ID_GALE_PROTO = 0, + BOARD_ID_GALE_EVT = 1, + BOARD_ID_GALE_EVT2 = 2, + BOARD_ID_GALE_EVT3 = 5, }; /* Board specific parameters */

1 0

New patch to review for coreboot: soc/intel/apollolake: Add support for logging boot count
by Furquan Shaikh 28 Jul '16

28 Jul '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15948 -gerrit commit 4a9dbde6331508f334545c91c4881d4bcd5974f0 Author: Furquan Shaikh <furquan(a)google.com> Date: Thu Jul 28 07:50:33 2016 -0700 soc/intel/apollolake: Add support for logging boot count BUG=chrome-os-partner:55473 Change-Id: Ib3e77180bd640ec0424978e73034d7c99cdcba95 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/romstage.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da7fcf1..1e3e6a2 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <device/resource.h> +#include <elog.h> #include <fsp/api.h> #include <fsp/util.h> #include <soc/iomap.h> @@ -119,6 +120,11 @@ asmlinkage void car_stage_entry(void) die("FSP memory init failed. Giving up."); } +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) + if (!s3wake) + boot_count_increment(); +#endif + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n");

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2016