Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15954
-gerrit
commit 6be547f21267cdcb68fbcfe40ac55bc930f814af
Author: Antonello Dettori <dev(a)dettori.io>
Date: Mon Jul 25 14:23:46 2016 +0200
payloads: add Kconfig option for bayou
Add an option to add bayou as the primary payload.
Change-Id: I8c0164344537b82870198b13ef6fdf20e7d095ef
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
---
payloads/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/payloads/Kconfig b/payloads/Kconfig
index 8cce778..7700631 100644
--- a/payloads/Kconfig
+++ b/payloads/Kconfig
@@ -25,12 +25,20 @@ config PAYLOAD_ELF
You will be able to specify the location and file name of the
payload image later.
+config PAYLOAD_BAYOU
+ bool "Bayou"
+ help
+ Select this option if you want to set bayou as your primary
+ payload.
+
source "payloads/external/*/Kconfig.name"
endchoice
source "payloads/external/*/Kconfig"
+source "payloads/bayou/Kconfig"
+
config PAYLOAD_FILE
string "Payload path and filename"
depends on PAYLOAD_ELF
Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15914
-gerrit
commit 6639465e21d6ef66d9bc757808ab9cd7f66e9155
Author: Antonello Dettori <dev(a)dettori.io>
Date: Wed Jul 27 12:41:04 2016 +0200
libpayload: split "Drivers" config section in Kconfig
Move the configuration of the timer, storage and USB drivers from the
main Kconfig to three separate ones stored in the respective
directories.
This reduces the LOC of Kconfig and makes it more manageable.
Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
---
payloads/libpayload/Kconfig | 283 +---------------------------
payloads/libpayload/drivers/storage/Kconfig | 59 ++++++
payloads/libpayload/drivers/timer/Kconfig | 129 +++++++++++++
payloads/libpayload/drivers/usb/Kconfig | 129 +++++++++++++
4 files changed, 320 insertions(+), 280 deletions(-)
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 276eb30..51826ea 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -354,286 +354,9 @@ config SPEAKER
depends on ARCH_X86
default y
-config STORAGE
- bool "Support for storage devices"
- default y
- help
- Select this option if you want support for storage devices (like
- hard drives, memory sticks or optical drives).
-
-config STORAGE_64BIT_LBA
- bool "Use 64-bit integers to address sectors"
- depends on STORAGE
- default n
- help
- If this is selected, sectors will be addressed by an 64-bit integer.
- Select this to support LBA-48 for ATA drives.
-
-config STORAGE_ATA
- bool "Support ATA drives (i.e. hard drives)"
- depends on STORAGE
- default y
- help
- Select this option if you want support for ATA storage devices
- (i.e. hard drives).
-
-config STORAGE_ATAPI
- bool "Support ATAPI drives (i.e. optical drives)"
- depends on STORAGE
- default y
- select STORAGE_ATA
- help
- Select this option if you want support for ATAPI storage devices
- (i.e. optical drives like CD or DVD drives).
-
-config STORAGE_AHCI
- bool "Support for AHCI host controllers"
- depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI
- default y
- help
- Select this option if you want support for SATA controllers in
- AHCI mode.
-
-config STORAGE_AHCI_ONLY_TESTED
- bool "Only enable tested controllers"
- depends on STORAGE_AHCI
- default y
- help
- If this option is selected only AHCI controllers which are known
- to work will be used.
-
-config TIMER_RDTSC
- bool
- default y
- depends on ARCH_X86
-
-choice
- prompt "Timer driver"
- default TIMER_NONE
- depends on !ARCH_X86
-
-config TIMER_NONE
- bool "None"
- help
- The timer driver is provided by the payload itself.
-
-config TIMER_MCT
- bool "Exynos MCT"
-
-config TIMER_TEGRA_1US
- bool "Tegra 1us"
-
-config TIMER_IPQ806X
- bool "Timer for ipq806x platforms"
-
-config TIMER_ARMADA38X
- bool "Timer for armada38x platforms"
- help
- This is the timer driver for marvell armada38x
- platforms.
-
-config TIMER_IPQ40XX
- bool "Timer for ipq40xx platforms"
- help
- This is the timer driver for QCA IPQ40xx based
- platforms.
-
-config TIMER_RK
- bool "Timer for Rockchip"
-
-config TIMER_BG4CD
- bool "Marvell BG4CD"
-
-config TIMER_CYGNUS
- bool "Timer for Cygnus"
-
-config TIMER_IMG_PISTACHIO
- bool "Timer for IMG Pistachio"
-
-config TIMER_MTK
- bool "Timer for MediaTek MT8173"
-
-endchoice
-
-config TIMER_MCT_HZ
- int "Exynos MCT frequency"
- depends on TIMER_MCT
- default 24000000
-
-config TIMER_MCT_ADDRESS
- hex "Exynos MCT base address"
- depends on TIMER_MCT
- default 0x101c0000
-
-config TIMER_RK_ADDRESS
- hex "Rockchip timer base address"
- depends on TIMER_RK
- default 0xff810020
-
-config TIMER_TEGRA_1US_ADDRESS
- hex "Tegra u1s timer base address"
- depends on TIMER_TEGRA_1US
- default 0x60005010
-
-config IPQ806X_TIMER_FREQ
- int "Hardware timer frequency"
- default 32000
- depends on TIMER_IPQ806X
- help
- IPQ hardware presently provides a single timer running at 32KHz, a
- finer granulariry timer is available but is not yet enabled.
-
-config IPQ806X_TIMER_REG
- hex "Timer register address"
- default 0x0200A008
- depends on TIMER_IPQ806X
- help
- Address of the register to read a free running timer value.
-
-config ARMADA38X_TIMER_FREQ
- int "Hardware timer frequency"
- depends on TIMER_ARMADA38X
- default 25000000
-
-config ARMADA38X_TIMER_REG
- hex "Timer register address"
- default 0xF1020314
- depends on TIMER_ARMADA38X
-
-config IPROC_PERIPH_GLB_TIM_REG_BASE
- hex "Cygnus timer base address"
- depends on TIMER_CYGNUS
- default 0x19020200
-
-config TIMER_MTK_HZ
- int "MediaTek GPT frequency"
- depends on TIMER_MTK
- default 13000000
- help
- Clock frequency of MediaTek General Purpose Timer.
-
-config TIMER_MTK_ADDRESS
- hex "MTK GPT register address"
- depends on TIMER_MTK
- default 0x10008048
- help
- Address of GPT4's counter register to read the FREERUN-mode timer value.
-
-config USB
- bool "USB Support"
- default y
-
-config USB_UHCI
- bool "Support for USB UHCI controllers"
- depends on USB && ARCH_X86
- default y
- help
- Select this option if you are going to use USB 1.1 on an Intel based
- system.
-
-config USB_OHCI
- bool "Support for USB OHCI controllers"
- depends on USB
- default y
- help
- Select this option if you are going to use USB 1.1 on a non-Intel based
- system.
-
-config USB_EHCI
- bool "Support for USB EHCI controllers"
- depends on USB
- default y
- help
- Select this option if you want to use USB 2.0
-
-config USB_XHCI
- bool "Support for USB xHCI controllers"
- depends on USB
- default y
- help
- Select this option if you want to use USB 3.0
-
-config USB_XHCI_MTK_QUIRK
- bool "Support for USB xHCI controllers on MTK SoC"
- depends on USB_XHCI
- help
- Select this option if you want to use USB 3.0 on MTK platform.
-
-config USB_DWC2
- bool "Support for USB DesignWare HCD controllers"
- depends on USB
- help
- Select this option if you want to use DesignWare USB 2.0 host controller
-
-config USB_HID
- bool "Support for USB keyboards"
- depends on USB
- default y
- help
- Select this option if you want to use devices complying to the
- USB HID (Human Interface Device) standard. Such devices are for
- example keyboards and mice. Currently only keyboards are supported.
- Say Y here unless you know exactly what you are doing.
-
-config USB_HUB
- bool "Support for USB hubs"
- depends on USB
- default y
- help
- Select this option if you want to compile in support for USB hubs.
- Say Y here unless you know exactly what you are doing.
-
-config USB_EHCI_HOSTPC_ROOT_HUB_TT
- bool "Support for USB EHCI ROOT HUB that has TT"
- depends on USB_EHCI
- default n
- help
- Select this option if USB EHCI root hub supports TT (Transaction
- Translator).
- To support this TT feature we read port-speed from non-standard
- register HOSTPC (offset 84h of Operational Register base).
-
-config USB_MSC
- bool "Support for USB storage"
- depends on USB
- default y
- help
- Select this option if you want to compile in support for USB mass
- storage devices (USB memory sticks, hard drives, CDROM/DVD drives)
- Say Y here unless you know exactly what you are doing.
-
-config USB_GEN_HUB
- bool
- default n if (!USB_HUB && !USB_XHCI)
- default y if (USB_HUB || USB_XHCI)
-config USB_PCI
- bool "Auto-scan PCI bus for USB host controllers"
- depends on USB
- default y if ARCH_X86
- default n
-
-config UDC
- bool "USB device mode support"
- default n
- help
- Select this option to add support for running as
- a USB device.
-
-config UDC_CI
- bool "ChipIdea driver for USB device mode"
- depends on UDC
- default n
- help
- Select this option to add the driver for ChipIdea
- USB device controller.
-
-config UDC_DWC2
- bool "Designware driver for USB device mode"
- depends on UDC
- default n
- help
- Select this option to add the driver for Designware
- USB device controller.
+source "drivers/timer/Kconfig"
+source "drivers/storage/Kconfig"
+source "drivers/usb/Kconfig"
endmenu
diff --git a/payloads/libpayload/drivers/storage/Kconfig b/payloads/libpayload/drivers/storage/Kconfig
new file mode 100644
index 0000000..961144e
--- /dev/null
+++ b/payloads/libpayload/drivers/storage/Kconfig
@@ -0,0 +1,59 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+config STORAGE
+ bool "Support for storage devices"
+ default y
+ help
+ Select this option if you want support for storage devices (like
+ hard drives, memory sticks or optical drives).
+
+config STORAGE_64BIT_LBA
+ bool "Use 64-bit integers to address sectors"
+ depends on STORAGE
+ default n
+ help
+ If this is selected, sectors will be addressed by an 64-bit integer.
+ Select this to support LBA-48 for ATA drives.
+
+config STORAGE_ATA
+ bool "Support ATA drives (i.e. hard drives)"
+ depends on STORAGE
+ default y
+ help
+ Select this option if you want support for ATA storage devices
+ (i.e. hard drives).
+
+config STORAGE_ATAPI
+ bool "Support ATAPI drives (i.e. optical drives)"
+ depends on STORAGE
+ default y
+ select STORAGE_ATA
+ help
+ Select this option if you want support for ATAPI storage devices
+ (i.e. optical drives like CD or DVD drives).
+
+config STORAGE_AHCI
+ bool "Support for AHCI host controllers"
+ depends on STORAGE && (STORAGE_ATA || STORAGE_ATAPI) && PCI
+ default y
+ help
+ Select this option if you want support for SATA controllers in
+ AHCI mode.
+
+config STORAGE_AHCI_ONLY_TESTED
+ bool "Only enable tested controllers"
+ depends on STORAGE_AHCI
+ default y
+ help
+ If this option is selected only AHCI controllers which are known
+ to work will be used.
diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig
new file mode 100644
index 0000000..8f047fa
--- /dev/null
+++ b/payloads/libpayload/drivers/timer/Kconfig
@@ -0,0 +1,129 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+
+config TIMER_RDTSC
+ bool
+ default y
+ depends on ARCH_X86
+
+choice
+ prompt "Timer driver"
+ default TIMER_NONE
+ depends on !ARCH_X86
+
+config TIMER_NONE
+ bool "None"
+ help
+ The timer driver is provided by the payload itself.
+
+config TIMER_MCT
+ bool "Exynos MCT"
+
+config TIMER_TEGRA_1US
+ bool "Tegra 1us"
+
+config TIMER_IPQ806X
+ bool "Timer for ipq806x platforms"
+
+config TIMER_ARMADA38X
+ bool "Timer for armada38x platforms"
+ help
+ This is the timer driver for marvell armada38x
+ platforms.
+
+config TIMER_IPQ40XX
+ bool "Timer for ipq40xx platforms"
+ help
+ This is the timer driver for QCA IPQ40xx based
+ platforms.
+
+config TIMER_RK
+ bool "Timer for Rockchip"
+
+config TIMER_BG4CD
+ bool "Marvell BG4CD"
+
+config TIMER_CYGNUS
+ bool "Timer for Cygnus"
+
+config TIMER_IMG_PISTACHIO
+ bool "Timer for IMG Pistachio"
+
+config TIMER_MTK
+ bool "Timer for MediaTek MT8173"
+
+endchoice
+
+config TIMER_MCT_HZ
+ int "Exynos MCT frequency"
+ depends on TIMER_MCT
+ default 24000000
+
+config TIMER_MCT_ADDRESS
+ hex "Exynos MCT base address"
+ depends on TIMER_MCT
+ default 0x101c0000
+
+config TIMER_RK_ADDRESS
+ hex "Rockchip timer base address"
+ depends on TIMER_RK
+ default 0xff810020
+
+config TIMER_TEGRA_1US_ADDRESS
+ hex "Tegra u1s timer base address"
+ depends on TIMER_TEGRA_1US
+ default 0x60005010
+
+config IPQ806X_TIMER_FREQ
+ int "Hardware timer frequency"
+ default 32000
+ depends on TIMER_IPQ806X
+ help
+ IPQ hardware presently provides a single timer running at 32KHz, a
+ finer granulariry timer is available but is not yet enabled.
+
+config IPQ806X_TIMER_REG
+ hex "Timer register address"
+ default 0x0200A008
+ depends on TIMER_IPQ806X
+ help
+ Address of the register to read a free running timer value.
+
+config ARMADA38X_TIMER_FREQ
+ int "Hardware timer frequency"
+ depends on TIMER_ARMADA38X
+ default 25000000
+
+config ARMADA38X_TIMER_REG
+ hex "Timer register address"
+ default 0xF1020314
+ depends on TIMER_ARMADA38X
+
+config IPROC_PERIPH_GLB_TIM_REG_BASE
+ hex "Cygnus timer base address"
+ depends on TIMER_CYGNUS
+ default 0x19020200
+
+config TIMER_MTK_HZ
+ int "MediaTek GPT frequency"
+ depends on TIMER_MTK
+ default 13000000
+ help
+ Clock frequency of MediaTek General Purpose Timer.
+
+config TIMER_MTK_ADDRESS
+ hex "MTK GPT register address"
+ depends on TIMER_MTK
+ default 0x10008048
+ help
+ Address of GPT4's counter register to read the FREERUN-mode timer value.
+
diff --git a/payloads/libpayload/drivers/usb/Kconfig b/payloads/libpayload/drivers/usb/Kconfig
new file mode 100644
index 0000000..e1b68f7
--- /dev/null
+++ b/payloads/libpayload/drivers/usb/Kconfig
@@ -0,0 +1,129 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config USB
+ bool "USB Support"
+ default y
+
+config USB_UHCI
+ bool "Support for USB UHCI controllers"
+ depends on USB && ARCH_X86
+ default y
+ help
+ Select this option if you are going to use USB 1.1 on an Intel based
+ system.
+
+config USB_OHCI
+ bool "Support for USB OHCI controllers"
+ depends on USB
+ default y
+ help
+ Select this option if you are going to use USB 1.1 on a non-Intel based
+ system.
+
+config USB_EHCI
+ bool "Support for USB EHCI controllers"
+ depends on USB
+ default y
+ help
+ Select this option if you want to use USB 2.0
+
+config USB_XHCI
+ bool "Support for USB xHCI controllers"
+ depends on USB
+ default y
+ help
+ Select this option if you want to use USB 3.0
+
+config USB_XHCI_MTK_QUIRK
+ bool "Support for USB xHCI controllers on MTK SoC"
+ depends on USB_XHCI
+ help
+ Select this option if you want to use USB 3.0 on MTK platform.
+
+config USB_DWC2
+ bool "Support for USB DesignWare HCD controllers"
+ depends on USB
+ help
+ Select this option if you want to use DesignWare USB 2.0 host controller
+
+config USB_HID
+ bool "Support for USB keyboards"
+ depends on USB
+ default y
+ help
+ Select this option if you want to use devices complying to the
+ USB HID (Human Interface Device) standard. Such devices are for
+ example keyboards and mice. Currently only keyboards are supported.
+ Say Y here unless you know exactly what you are doing.
+
+config USB_HUB
+ bool "Support for USB hubs"
+ depends on USB
+ default y
+ help
+ Select this option if you want to compile in support for USB hubs.
+ Say Y here unless you know exactly what you are doing.
+
+config USB_EHCI_HOSTPC_ROOT_HUB_TT
+ bool "Support for USB EHCI ROOT HUB that has TT"
+ depends on USB_EHCI
+ default n
+ help
+ Select this option if USB EHCI root hub supports TT (Transaction
+ Translator).
+ To support this TT feature we read port-speed from non-standard
+ register HOSTPC (offset 84h of Operational Register base).
+
+config USB_MSC
+ bool "Support for USB storage"
+ depends on USB
+ default y
+ help
+ Select this option if you want to compile in support for USB mass
+ storage devices (USB memory sticks, hard drives, CDROM/DVD drives)
+ Say Y here unless you know exactly what you are doing.
+
+config USB_GEN_HUB
+ bool
+ default n if (!USB_HUB && !USB_XHCI)
+ default y if (USB_HUB || USB_XHCI)
+config USB_PCI
+ bool "Auto-scan PCI bus for USB host controllers"
+ depends on USB
+ default y if ARCH_X86
+ default n
+
+config UDC
+ bool "USB device mode support"
+ default n
+ help
+ Select this option to add support for running as
+ a USB device.
+
+config UDC_CI
+ bool "ChipIdea driver for USB device mode"
+ depends on UDC
+ default n
+ help
+ Select this option to add the driver for ChipIdea
+ USB device controller.
+
+config UDC_DWC2
+ bool "Designware driver for USB device mode"
+ depends on UDC
+ default n
+ help
+ Select this option to add the driver for Designware
+ USB device controller.
+
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15834
-gerrit
commit d4e0d56792483132312fffef3c1fc9242e3b0887
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Sun Jul 24 22:54:13 2016 -0700
google/reef: Mainboard handler function for gpio SMI
This patch adds mainboard_smi_gpi_handler which handles the
SMI event. This can happen in situations like lidclose and
system goes to shutdown.
BUG=chrome-os-partner:54977
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/mainboard/google/reef/smihandler.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index 05d363f..5947c24 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -17,9 +17,17 @@
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/smm.h>
+#include <soc/gpe.h>
#include <soc/pm.h>
+#include <soc/smm.h>
#include "ec.h"
+void mainboard_smi_gpi_handler(const struct gpi_status *sts)
+{
+ if (gpi_status_get(sts, GPIO_49)) /* Gpio pin 49 is for EC SMI */
+ chromeec_smi_process_events();
+}
+
void mainboard_smi_sleep(u8 slp_typ)
{
if (slp_typ == ACPI_S3)
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15834
-gerrit
commit 37643324abda73e039842ca9e8ffc31cf0b94e43
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Sun Jul 24 22:54:13 2016 -0700
google/reef: Mainboard gpi handler function
This patch add mainboard_smi_gpi_handler which handles the
SMI event. This can happen in situations like lidclose and
system goes to shutdown.
BUG=chrome-os-partner:54977
TEST=When system is in firmware mode executing the command
lidclose from ec console shuts down the system.
Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/mainboard/google/reef/smihandler.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index 05d363f..8d592ea 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -18,8 +18,16 @@
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/smm.h>
#include <soc/pm.h>
+#include <soc/smm.h>
+#include <soc/gpe.h>
#include "ec.h"
+void mainboard_smi_gpi_handler(const struct gpi_status *sts)
+{
+ if (gpi_status_get(sts, GPIO_49)) /* Gpio pin 49 is for EC SMI */
+ chromeec_smi_process_events();
+}
+
void mainboard_smi_sleep(u8 slp_typ)
{
if (slp_typ == ACPI_S3)
HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15953
-gerrit
commit c14fdc437831f3a51789846fa7d8101c17383e44
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Fri Jul 29 07:40:41 2016 +0200
src/arch: Capitalize CPU, RAM and ROM
Change-Id: Ia6ac94a93b48037a392a9aec2cd19cd80369173f
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/arch/arm/armv4/bootblock.S | 2 +-
src/arch/arm/armv7/bootblock.S | 2 +-
src/arch/arm/cpu.c | 2 +-
src/arch/x86/Kconfig | 2 +-
src/arch/x86/c_start.S | 8 ++++----
src/arch/x86/cpu.c | 12 ++++++------
src/arch/x86/exception.c | 2 +-
src/arch/x86/include/arch/memlayout.h | 2 +-
src/arch/x86/include/arch/symbols.h | 2 +-
src/arch/x86/walkcbfs.S | 2 +-
10 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S
index 5484450..0391ebf 100644
--- a/src/arch/arm/armv4/bootblock.S
+++ b/src/arch/arm/armv4/bootblock.S
@@ -28,7 +28,7 @@
ENTRY(_start)
/*
- * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index ad7085d..da7509d 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -39,7 +39,7 @@ maskrom_param:
ENTRY(_start)
/*
- * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data
* aborts may happen early and crash before the abort handlers are
* installed, but at least the problem will show up near the code that
* causes it.
diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c
index 240d924..e138a6f 100644
--- a/src/arch/arm/cpu.c
+++ b/src/arch/arm/cpu.c
@@ -30,7 +30,7 @@
#include <stdlib.h>
#include <arch/cpu.h>
-/* Return the cpu struct which is at the high memory address of the stack.
+/* Return the CPU struct which is at the high memory address of the stack.
*/
struct cpu_info *cpu_info(void)
{
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index af73a58..e117deb 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -190,7 +190,7 @@ config VERSTAGE_ADDR
default 0x2000000
# Use the post CAR infrastructure for tearing down cache-as-ram
-# from a program loaded in ram and subsequently loading ramstage.
+# from a program loaded in RAM and subsequently loading ramstage.
config POSTCAR_STAGE
def_bool n
diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
index 6bda64f..9a64fa6 100644
--- a/src/arch/x86/c_start.S
+++ b/src/arch/x86/c_start.S
@@ -77,7 +77,7 @@ _start:
/* Push the thread pointer. */
push $0
#endif
- /* Push the cpu index and struct cpu */
+ /* Push the CPU index and struct CPU */
push $0
push $0
@@ -331,12 +331,12 @@ gdtaddr:
* which is defined in entry32.inc
*
* When the machine is initially started, we use a very simple
- * gdt from rom (that in entry32.inc) which only contains those
+ * gdt from ROM (that in entry32.inc) which only contains those
* entries we need for protected mode.
*
* When we're executing code from RAM, we want to do more complex
- * stuff, like initializing PCI option roms in real mode, or doing
- * a resume from a suspend to ram.
+ * stuff, like initializing PCI option ROMs in real mode, or doing
+ * a resume from a suspend to RAM.
*/
gdt:
/* selgdt 0, unused */
diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
index cba105a..0fdc11c 100644
--- a/src/arch/x86/cpu.c
+++ b/src/arch/x86/cpu.c
@@ -96,7 +96,7 @@ static int deep_magic_nexgen_probe(void)
}
#endif
-/* List of cpu vendor strings along with their normalized
+/* List of CPU vendor strings along with their normalized
* id values.
*/
static struct {
@@ -132,7 +132,7 @@ static const char *x86_vendor_name[] = {
static const char *cpu_vendor_name(int vendor)
{
const char *name;
- name = "<invalid cpu vendor>";
+ name = "<invalid CPU vendor>";
if ((vendor < (ARRAY_SIZE(x86_vendor_name))) &&
(x86_vendor_name[vendor] != 0))
{
@@ -246,7 +246,7 @@ void cpu_initialize(unsigned int index)
cpu = info->cpu;
if (!cpu) {
- die("CPU: missing cpu device structure");
+ die("CPU: missing CPU device structure");
}
if (cpu->initialized)
@@ -254,7 +254,7 @@ void cpu_initialize(unsigned int index)
post_log_path(cpu);
- /* Find what type of cpu we are dealing with */
+ /* Find what type of CPU we are dealing with */
identify_cpu(cpu);
printk(BIOS_DEBUG, "CPU: vendor %s device %x\n",
cpu_vendor_name(cpu->vendor), cpu->device);
@@ -273,11 +273,11 @@ void cpu_initialize(unsigned int index)
set_cpu_ops(cpu);
cpu->device += c.x86_mask;
if(!cpu->ops) die("Unknown cpu");
- printk(BIOS_DEBUG, "Using generic cpu ops (good)\n");
+ printk(BIOS_DEBUG, "Using generic CPU ops (good)\n");
}
- /* Initialize the cpu */
+ /* Initialize the CPU */
if (cpu->ops && cpu->ops->init) {
cpu->enabled = 1;
cpu->initialized = 1;
diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
index b6e6ffb..cbf0358 100644
--- a/src/arch/x86/exception.c
+++ b/src/arch/x86/exception.c
@@ -420,7 +420,7 @@ void x86_exception(struct eregs *info)
out_buffer[2] = hexchars[signo & 0xf];
out_buffer[3] = '\0';
break;
- case 'g': /* return the value of the cpu registers */
+ case 'g': /* return the value of the CPU registers */
copy_to_hex(out_buffer, &gdb_stub_registers, sizeof(gdb_stub_registers));
break;
case 'G': /* set the value of the CPU registers - return OK */
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index 5f5cba6..83e5b90 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -19,7 +19,7 @@
#include <rules.h>
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
-/* No .data or .bss sections. Cache as ram is handled separately. */
+/* No .data or .bss sections. Cache as RAM is handled separately. */
#define ARCH_STAGE_HAS_DATA_SECTION 0
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif
diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h
index e055fa0..704e3bb 100644
--- a/src/arch/x86/include/arch/symbols.h
+++ b/src/arch/x86/include/arch/symbols.h
@@ -18,7 +18,7 @@
#define __ARCH_SYMBOLS_H
/*
- * The _car_region_[start|end] covers the entirety of the cache as ram
+ * The _car_region_[start|end] covers the entirety of the cache as RAM
* region. All other symbols with the _car prefix a subsets of this
* larger region.
*/
diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S
index c5408b1..bd71f19 100644
--- a/src/arch/x86/walkcbfs.S
+++ b/src/arch/x86/walkcbfs.S
@@ -47,7 +47,7 @@ walkcbfs_asm:
mov CBFS_HEADER_ROMSIZE(%eax), %ecx
bswap %ecx
mov $0, %ebx
- sub %ecx, %ebx /* rom base address in ebx */
+ sub %ecx, %ebx /* ROM base address in ebx */
mov CBFS_HEADER_OFFSET(%eax), %ecx
bswap %ecx
add %ecx, %ebx /* address where we start looking for LARCHIVEs */