coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: arch: Add ARMv7-R configuration
by hakim giydan 08 Jul '16

08 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335 -gerrit commit 3218f693533365a1c80825b35c4ff283015625ee Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Fri Jul 8 14:11:54 2016 -0700 arch: Add ARMv7-R configuration This change adds armv7-r configuration for romstage and verstage, and any other files needed to initialize an amrv7-r processor. ARMv7-R is an ARM processor based on the Cortex-R series. Currently, there is already support for the Cortex-M series, so the same files had been renamed and reused for Cortex-R series as well. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/arch/arm/armv7/Kconfig | 8 ++++ src/arch/arm/armv7/Makefile.inc | 23 ++++++++++++ src/arch/arm/armv7/cache_m.c | 79 --------------------------------------- src/arch/arm/armv7/cache_mr.c | 79 +++++++++++++++++++++++++++++++++++++++ src/arch/arm/armv7/cpu_r.S | 65 ++++++++++++++++++++++++++++++++ src/arch/arm/armv7/exception_m.c | 36 ------------------ src/arch/arm/armv7/exception_mr.c | 36 ++++++++++++++++++ util/xcompile/xcompile | 2 +- 8 files changed, 212 insertions(+), 116 deletions(-) diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 0ab3542..4fe3fd7 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M config ARCH_VERSTAGE_ARMV7_M def_bool n select ARCH_VERSTAGE_ARM + +config ARCH_VERSTAGE_ARMV7_R + def_bool n + select ARCH_VERSTAGE_ARM + +config ARCH_ROMSTAGE_ARMV7_R + def_bool n + select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2e9c49c..ca653c5 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -73,6 +73,17 @@ libverstage-S-ccopts += $(armv7_asm_flags) verstage-generic-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y) +libverstage-generic-ccopts += $(armv7-r_flags) +libverstage-S-ccopts += $(armv7-r_asm_flags) +verstage-generic-ccopts += $(armv7-r_flags) +verstage-S-ccopts += $(armv7-r_asm_flags) + +verstage-y += cache_mr.c +verstage-y += cpu_r.S +verstage-y += exception_mr.c +verstage-y += mmu.c + endif # CONFIG_ARCH_VERSTAGE_ARMV7_M ################################################################################ @@ -91,6 +102,18 @@ romstage-S-ccopts += $(armv7_asm_flags) rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y) +romstage-y += cache_mr.c +romstage-y += cpu_r.S +romstage-y += exception_mr.c +romstage-y += mmu.c + +romstage-generic-ccopts += $(armv7-r_flags) +romstage-S-ccopts += $(armv7-r_asm_flags) + +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_ROMSTAGE_ARMV7 ############################################################################### diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c deleted file mode 100644 index ec8a970..0000000 --- a/src/arch/arm/armv7/cache_m.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * cache.c: Cache maintenance routines for ARMv7-M - */ - -#include <stdint.h> - -#include <arch/cache.h> - -void tlb_invalidate_all(void) -{ -} - -void dcache_clean_all(void) -{ -} - -void dcache_clean_invalidate_all(void) -{ -} - -void dcache_invalidate_all(void) -{ -} - -unsigned int dcache_line_bytes(void) -{ - return 0; -} - -void dcache_clean_by_mva(void const *addr, size_t len) -{ -} - -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_mmu_disable(void) -{ -} - -void dcache_mmu_enable(void) -{ -} - -void cache_sync_instructions(void) -{ -} diff --git a/src/arch/arm/armv7/cache_mr.c b/src/arch/arm/armv7/cache_mr.c new file mode 100644 index 0000000..ec8a970 --- /dev/null +++ b/src/arch/arm/armv7/cache_mr.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-M + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ +} + +void dcache_clean_all(void) +{ +} + +void dcache_clean_invalidate_all(void) +{ +} + +void dcache_invalidate_all(void) +{ +} + +unsigned int dcache_line_bytes(void) +{ + return 0; +} + +void dcache_clean_by_mva(void const *addr, size_t len) +{ +} + +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_mmu_disable(void) +{ +} + +void dcache_mmu_enable(void) +{ +} + +void cache_sync_instructions(void) +{ +} diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S new file mode 100644 index 0000000..6d5820e --- /dev/null +++ b/src/arch/arm/armv7/cpu_r.S @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> + * Copyright (c) 2014 Google Inc. + * Copyright (c) 2016 Marvell Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* + * Bring an ARM processor we just gained control of (e.g. from IROM) into a + * known state regarding caches/SCTLR. Completely cleans and invalidates + * icache/dcache, and dcache (if active), and enables unaligned + * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5. + * + * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 + */ +ENTRY(arm_init_caches) + /* r4: SCTLR, return address: r5 (stay valid for the whole function) */ + mov r5, lr + mrc p15, 0, r4, c1, c0, 0 + + /* Activate ICache (12) and Branch Prediction (11) already for speed */ + orr r4, # (1 << 11) | (1 << 12) + mcr p15, 0, r4, c1, c0, 0 + + /* Flush and invalidate dcache in ascending order */ + bl dcache_invalidate_all + + /* Deactivate Alignment Check (1) and DCache (2) */ + and r4, # ~(1 << 1) & ~(1 << 2) + mcr p15, 0, r4, c1, c0, 0 + + /* Invalidate icache for good measure */ + mcr p15, 0, r0, c7, c5, 0 + + dsb + isb + + bx r5 +ENDPROC(arm_init_caches) diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c deleted file mode 100644 index d76cc6a..0000000 --- a/src/arch/arm/armv7/exception_m.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/exception.h> -#include <console/console.h> - -void exception_init(void) -{ - printk(BIOS_DEBUG, "Exception handlers not installed.\n"); -} diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c new file mode 100644 index 0000000..d76cc6a --- /dev/null +++ b/src/arch/arm/armv7/exception_mr.c @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <console/console.h> + +void exception_init(void) +{ + printk(BIOS_DEBUG, "Exception handlers not installed.\n"); +} diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 13a0e8f..1a9c38c 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -316,7 +316,7 @@ arch_config_arm() { TBFDARCHS="littlearm" TCLIST="armv7-a armv7a arm" TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" + TSUPP="arm armv4 armv7 armv7_m armv7_r" TABI="eabi" }

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New patch to review for coreboot: AMD k8 fam10: Drop excessive spinlock initialization
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15589 -gerrit commit 2f76cf64147e2045b718dad2dff1560181e9f77f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 8 11:35:45 2016 +0300 AMD k8 fam10: Drop excessive spinlock initialization If CAR migration operations unintentionally set the lock, BSP would have got stuck on printk() calls above already. Change-Id: I35155ebcb00475a0964fc639ee74ad2755127740 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index ed0a3a5..bf27212 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -94,13 +94,6 @@ static void prepare_ramstage_region(int s3resume) memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); } -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - initialize_romstage_console_lock(); -#endif -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) - initialize_romstage_nvram_cbfs_lock(); -#endif - print_car_debug(" Done\n"); }

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New patch to review for coreboot: Romstage spinlocks require EARLY_CBMEM_INIT
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15588 -gerrit commit 4098a46036365757eb7b6d069d586cdc04eb8bc2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 8 13:33:00 2016 +0300 Romstage spinlocks require EARLY_CBMEM_INIT The lock stores need to migrate from CAR to CBMEM. Change-Id: I3cffd14bdfc57d5588d0f24afe00e0f9891bfe5a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 91b594e..c63ad41 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -538,10 +538,12 @@ config HAVE_HARD_RESET config HAVE_ROMSTAGE_CONSOLE_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n help This should be enabled on certain plaforms, such as the AMD @@ -550,6 +552,7 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n config HAVE_MONOTONIC_TIMER

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Patch set updated for coreboot: AMD k8 fam10: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15475 -gerrit commit 43087cccee90010f100675b14be2a1954d62cba9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:57 2016 +0300 AMD k8 fam10: Delay ACPI S3 backup until ramstage loader Change-Id: I6d5d3e1ccd2dab727c9eba6c6175d47955719b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 56532d1..1c68d07 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -135,9 +135,6 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - if (acpi_is_wakeup_s3()) - acpi_prepare_for_resume(); - set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute ramstage */

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Patch set updated for coreboot: AMD k8 fam10: Use common ACPI S3 recovery
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15474 -gerrit commit 3780a04524422ffb21e547221faf86c4ccab2f8b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:53:00 2016 +0300 AMD k8 fam10: Use common ACPI S3 recovery Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 16 ---------------- src/arch/x86/include/arch/acpi.h | 7 ------- src/cpu/amd/car/post_cache_as_ram.c | 26 ++------------------------ src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/model_fxx/Kconfig | 1 - 5 files changed, 2 insertions(+), 49 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index eb56b43..0d0254e 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -126,22 +126,6 @@ static int backup_create_or_update(struct resume_backup *backup_mem, return 0; } -void *acpi_backup_container(uintptr_t base, size_t size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (!backup_mem) - return NULL; - - if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size, BACKUP_PAGE_SZ)) - return NULL; - - if (backup_create_or_update(backup_mem, base, size) < 0) - return NULL; - - backup_mem->valid = 1; - return (void*)(uintptr_t)backup_mem->cbmem; -} - void backup_ramstage_section(uintptr_t base, size_t size) { struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 489edac..babb50b 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -618,13 +618,6 @@ static inline int acpi_s3_resume_allowed(void) return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME); } -/* Return address in reserved memory where to backup low memory - * while platform resumes from S3 suspend. Caller is responsible of - * making a complete copy of the region base..base+size, with - * parameteres base and size that meet page alignment requirement. - */ -void *acpi_backup_container(uintptr_t base, size_t size); - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) extern int acpi_slp_type; diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 4991b24..56532d1 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -45,12 +45,6 @@ static void memcpy_(void *d, const void *s, size_t len) memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -58,23 +52,6 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_ramstage_region(int s3resume) -{ - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); - } else { - memset_((void*)0, 0, CONFIG_RAMTOP); - } - - print_car_debug(" Done\n"); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -158,7 +135,8 @@ void cache_as_ram_new_stack (void) set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); + if (acpi_is_wakeup_s3()) + acpi_prepare_for_resume(); set_sysinfo_in_ram(1); // So other core0 could start to train mem diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 30c7dee..fda7fc8 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,6 @@ config CPU_AMD_MODEL_10XXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index 3eb5b94..c8bae33 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -9,7 +9,6 @@ config CPU_AMD_MODEL_FXX select SSE2 select TSC_SYNC_LFENCE select UDELAY_LAPIC - select ACPI_HUGE_LOWMEM_BACKUP select SUPPORT_CPU_UCODE_IN_CBFS if CPU_AMD_MODEL_FXX

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Patch set updated for coreboot: AMD k8 fam10: Separate romstage ramstack (WIP)
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15473 -gerrit commit ebbb5fe7b3184e790a5f4a60770ea740882fcee6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 19:45:19 2016 +0300 AMD k8 fam10: Separate romstage ramstack (WIP) Romstage ram stack was placed below RAMTOP. This is a vulnerable location as a large ramstage could overwrite it. Location also prevents optimizing S3 resume path since all low memory between RAMBASE..RAMTOP has to be backed to CBMEM. When possible, place ram stack high. Change-Id: I4106e91ed3256aca5d0d115d4aa7e46b75b27eec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 39 +++++++++++-------------------------- 1 file changed, 11 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index bf27212..4991b24 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -23,6 +23,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <arch/acpi.h> +#include <program_loading.h> #include <romstage_handoff.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -37,12 +38,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -63,35 +58,18 @@ static int memcmp_(void *d, const void *s, size_t len) return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - static void prepare_ramstage_region(int s3resume) { - size_t backup_top = backup_size(); print_car_debug("Prepare ramstage memory region..."); if (s3resume) { void *resume_backup_memory = acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); if (resume_backup_memory) memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE - backup_top); + HIGH_MEMORY_SAVE); + memset_((void*) CONFIG_RAMBASE, 0, HIGH_MEMORY_SAVE); } else { - memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); + memset_((void*)0, 0, CONFIG_RAMTOP); } print_car_debug(" Done\n"); @@ -111,6 +89,8 @@ static void vErrata343(void) wrmsr(BU_CFG2_MSR, msr); } +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 + void post_cache_as_ram(void) { uint32_t family = amd_fam1x_cpu_family(); @@ -128,7 +108,10 @@ void post_cache_as_ram(void) if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); - prepare_romstage_ramstack(s3resume); + /* FIXME: CBMEM stack is not wb-cacheable yet. */ + uintptr_t ramtop = romstage_ram_stack_base(ROMSTAGE_RAM_STACK_SIZE, + s3resume ? ROMSTAGE_STACK_CBMEM : ROMSTAGE_STACK_LOW_MEM); + ramtop += ROMSTAGE_RAM_STACK_SIZE; if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { struct romstage_handoff *handoff; @@ -146,7 +129,7 @@ void post_cache_as_ram(void) } size_t car_size = car_data_size(); - void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); + void *migrated_car = (void *)(ramtop - car_size); print_car_debug("Copying data from cache to RAM..."); memcpy_(migrated_car, _car_relocatable_data_start, car_size);

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Patch set updated for coreboot: AMD k8 fam10: Fix romstage handoff
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15472 -gerrit commit b4e5943fb3c32862f14874625c5455dc7c5bf215 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 15:44:05 2016 +0300 AMD k8 fam10: Fix romstage handoff It is not possible for cbmem_add() to complete succesfully before cbmem_recovery() is called. Adding more tables on S3 resume path is also not possible. Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 22f39ba..ed0a3a5 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -130,19 +130,22 @@ void post_cache_as_ram(void) if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = acpi_is_wakeup_s3(); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - int s3resume = acpi_is_wakeup_s3(); - if (s3resume) + + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) || s3resume) cbmem_recovery(s3resume); prepare_romstage_ramstack(s3resume); + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { + struct romstage_handoff *handoff; + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + } + /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { /* Family 10h and 12h, 11h until shown otherwise */

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Patch set updated for coreboot: ACPI S3: Drop too early resume backup
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15477 -gerrit commit 32d07a066f5ecce9a98283e4c93a3074199184ed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 13:09:56 2016 +0300 ACPI S3: Drop too early resume backup No longer needed as low memory backup is implemented as part of the ramstage loader, when the actual requirement of the ramstage to load is known. Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 17 ----------------- src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 19 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 0d0254e..4f4f2c2 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -148,23 +148,6 @@ void backup_ramstage_section(uintptr_t base, size_t size) backup_mem->valid = 1; } -/* Make backup of low-memory region, relying on the base and size - * of the ramstage that was loaded before entry to ACPI S3. - * - * DEPRECATED - */ -void acpi_prepare_for_resume(void) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (!backup_mem) - return; - - /* Back up the OS-controlled memory where ramstage will be loaded. */ - memcpy((void*)(uintptr_t)backup_mem->cbmem, - (void*)(uintptr_t)backup_mem->lowmem, (size_t)backup_mem->size); - backup_mem->valid = 1; -} - /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it being there during reboot time. If this fails, ACPI resume will * be disabled. We assume that ramstage does not change while in suspend, diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index babb50b..b2554ad 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -631,14 +631,12 @@ int acpi_is_wakeup(void); int acpi_is_wakeup_s3(void); int acpi_is_wakeup_s4(void); #endif -void acpi_prepare_for_resume(void); #else #define acpi_slp_type 0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; } -static inline void acpi_prepare_for_resume(void) { } #endif static inline uintptr_t acpi_align_current(uintptr_t current)

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Patch set updated for coreboot: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15476 -gerrit commit 76551ea91986f2d8d285817c302b0cead85c7076 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 28 07:50:48 2016 +0300 ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 4 ---- src/arch/x86/acpi_s3.c | 5 ----- 2 files changed, 9 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c63ad41..7c1415e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -516,10 +516,6 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 4f4f2c2..c8372d5 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -95,11 +95,6 @@ static int backup_create_or_update(struct resume_backup *backup_mem, { uintptr_t top; - if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - /* Align backup region to complete pages. */ top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); base = ALIGN_DOWN(base, BACKUP_PAGE_SZ);

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Patch set updated for coreboot: AGESA: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15470 -gerrit commit c979428f43b5f2b5f847ff3b7e4ff3d7f017c988 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:39 2016 +0300 AGESA: Delay ACPI S3 backup until ramstage loader Change-Id: I59773161f22c1ec6a52050245f9ad3e6cc74a934 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index e74c5b3..1e4aadb 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -91,9 +91,4 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); }

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coreboot-gerrit July 2016