coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

Patch merged into coreboot/master: gru: include ram_code in coreboot table
by gerrit＠coreboot.org 10 Jul '16

10 Jul '16

the following patch was just integrated into master: commit 1f83ffac1b30e7b6ed59fb26ee2ba57cec4938eb Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Jun 21 19:07:32 2016 -0700 gru: include ram_code in coreboot table This is needed to ensure that the ram-code node is included in the device tree by depthcharge. BRANCH=none BUG=chrome-os-partner:54566 TEST=built updated firmware, booted on kevin into Linux shell, checked the device tree contents: localhost ~ # od -tx1 /proc/device-tree/firmware/coreboot/ram-code 0000000 00 00 00 01 0000004 localhost # Change-Id: Ibe96e3bc8fc0106013241738f5726783d74bd78b Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 53c002114f7044b88728c9e17150cd3a2cf1f80f Original-Change-Id: Iba573fba9f9b88b87867c6963e48215e254319ed Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/354705 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/15566 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15566 for details. -gerrit

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Patch set updated for coreboot: soc/intel/quark/bootblock: Remove clear_smi_and_wake_events
by Jonathan Neuschäfer 10 Jul '16

10 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15552 -gerrit commit 8401e0d9da9a2f36d7f88df6594ba3d48c82bd7e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jul 6 22:08:46 2016 +0200 soc/intel/quark/bootblock: Remove clear_smi_and_wake_events It is not used in this file. Change-Id: I59bb41370b97b79073c0fd82b1dbcae9fd8a62d0 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/soc/intel/quark/bootblock/bootblock.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c index 669cd47..4aa774b 100644 --- a/src/soc/intel/quark/bootblock/bootblock.c +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -21,15 +21,6 @@ #include <soc/pci_devs.h> #include <soc/reg_access.h> -static const struct reg_script clear_smi_and_wake_events[] = { - /* Clear any SMI or wake events */ - REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), - REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), - REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), - REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), - REG_SCRIPT_END -}; - static const struct reg_script legacy_gpio_init[] = { /* Temporarily enable the legacy GPIO controller */ REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID

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Patch set updated for coreboot: nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration
by Jonathan Neuschäfer 10 Jul '16

10 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15554 -gerrit commit 29fb9c9b16590ed67cd14bae0faa9e17063c7fa5 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jul 6 22:08:46 2016 +0200 nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration Change-Id: I7c3973ff325f11a86728e8660c70839776981aa5 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/northbridge/intel/pineview/northbridge.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 6a3e829..c7cfec2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -36,7 +36,6 @@ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI */ static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 128; static void add_fixed_resources(device_t dev, int index) {

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Patch set updated for coreboot: spike-riscv: Remove HTIF related code
by Jonathan Neuschäfer 10 Jul '16

10 Jul '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15289 -gerrit commit 74196e0fe584064b3126123bf981edcddd8f3cd5 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jul 7 20:53:28 2016 +0200 spike-riscv: Remove HTIF related code The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/spike_util.c | 110 ++--------------------- 1 file changed, 7 insertions(+), 103 deletions(-) diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..358cb44 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -55,14 +55,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t mcall_send_ipi(uintptr_t recipient) { - //if (recipient >= num_harts) - //return -1; - - if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { - mb(); - write_csr(send_ipi, recipient); - } - + die("mcall_send_ipi is currently not implemented"); return 0; } @@ -79,50 +72,26 @@ uintptr_t mcall_clear_ipi(void) uintptr_t mcall_shutdown(void) { - while (1) write_csr(mtohost, 1); + die("mcall_shutdown is currently not implemented"); return 0; } uintptr_t mcall_set_timer(unsigned long long when) { - write_csr(mtimecmp, when); - clear_csr(mip, MIP_STIP); - set_csr(mie, MIP_MTIP); + die("mcall_set_timer is currently not implemented"); return 0; } uintptr_t mcall_dev_req(sbi_device_message *m) { - if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; - - while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); - - m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; - HLS()->device_request_queue_head = m; - HLS()->device_request_queue_size++; - + die("mcall_dev_req is currently not implemented"); return 0; } uintptr_t mcall_dev_resp(void) { - htif_interrupt(0, 0); - - sbi_device_message* m = HLS()->device_response_queue_head; - if (m) { - //printm("resp %p\n", m); - sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); - HLS()->device_response_queue_head = next; - if (!next) { - HLS()->device_response_queue_tail = 0; - - // only clear SSIP if no other events are pending - clear_csr(mip, MIP_SSIP); - mb(); - if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); - } - } - return (uintptr_t)m; + die("mcall_dev_resp is currently not implemented"); + return 0; } uintptr_t mcall_hart_id(void) @@ -136,74 +105,9 @@ void hls_init(uint32_t hart_id) HLS()->hart_id = hart_id; } -uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { - uintptr_t fromhost = swap_csr(mfromhost, 0); - if (!fromhost) - return 0; - - uintptr_t dev = FROMHOST_DEV(fromhost); - uintptr_t cmd = FROMHOST_CMD(fromhost); - uintptr_t data = FROMHOST_DATA(fromhost); - - sbi_device_message* m = HLS()->device_request_queue_head; - sbi_device_message* prev = 0x0; - unsigned long i, n; - for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) { - /* - if (!supervisor_paddr_valid(m, sizeof(*m)) - && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M) - panic("htif: page fault"); - */ - - sbi_device_message* next = (void*)m->sbi_private_data; - if (m->dev == dev && m->cmd == cmd) { - m->data = data; - - // dequeue from request queue - if (prev) - prev->sbi_private_data = (uintptr_t)next; - else - HLS()->device_request_queue_head = next; - HLS()->device_request_queue_size = n-1; - m->sbi_private_data = 0; - - // enqueue to response queue - if (HLS()->device_response_queue_tail) - { - HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; - } - else - { - HLS()->device_response_queue_head = m; - } - HLS()->device_response_queue_tail = m; - - // signal software interrupt - set_csr(mip, MIP_SSIP); - return 0; - } - - prev = m; - m = (void*)atomic_read(&m->sbi_private_data); - } - //HLT(); - return 0; - //panic("htif: no record"); -} - uintptr_t mcall_console_putchar(uint8_t ch) { - while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0); - while (1) { - uintptr_t fromhost = read_csr(mfromhost); - if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) { - if (fromhost) - htif_interrupt(0, 0); - continue; - } - write_csr(mfromhost, 0); - break; - } + do_putchar(ch); return 0; }

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Patch set updated for coreboot: Add support for F2950 single-board computer
by Andrey Korolyov 09 Jul '16

09 Jul '16

Andrey Korolyov (andrey(a)xdel.ru) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15565 -gerrit commit 795dbcf66481d71d9f43182593dcd72378c29a5d Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Fri Jul 1 20:06:37 2016 +0300 Add support for F2950 single-board computer This platform, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 Mhz, 128 or 512 Mb of RAM in the single SODIMM slot and 128 or 512 IDE DOM. The board does have three USB 2.0 ports, PS/2, VGA, Geode audio controller and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correctly while running vendor BIOS nor write flash contents. At this moment GeodeVGA does not work out-of-box after initialization by SeaBIOS, thereby preventing selection of the bootable media, Linux lxfb driver works well. Except this, all peripheral components (USB, serial, IDE, PS/2, audio and ethernet) are working well too. For all Geode LX boards toolchain at a time of this commit should use gcc-4.8 to avoid issue described in [1] until proper fix will be made for gcc default flag set or within romcc. Bisection by another coreboot user showed that the problem was bound to the specific gcc version [2]. [1]. https://www.coreboot.org/pipermail/coreboot/2016-January/080867.html [2]. https://www.coreboot.org/pipermail/coreboot/2016-April/081187.html Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 --- src/mainboard/amd/f2950/Kconfig | 27 ++++++++++++ src/mainboard/amd/f2950/Kconfig.name | 2 + src/mainboard/amd/f2950/board_info.txt | 6 +++ src/mainboard/amd/f2950/cmos.layout | 36 +++++++++++++++ src/mainboard/amd/f2950/devicetree.cb | 67 ++++++++++++++++++++++++++++ src/mainboard/amd/f2950/irq_tables.c | 64 +++++++++++++++++++++++++++ src/mainboard/amd/f2950/romstage.c | 80 ++++++++++++++++++++++++++++++++++ 7 files changed, 282 insertions(+) diff --git a/src/mainboard/amd/f2950/Kconfig b/src/mainboard/amd/f2950/Kconfig new file mode 100644 index 0000000..5bfe120 --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig @@ -0,0 +1,27 @@ +if BOARD_AMD_F2950 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_GEODE_LX + select NORTHBRIDGE_AMD_LX + select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF + select HAVE_PIRQ_TABLE + select PIRQ_ROUTE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select POWER_BUTTON_FORCE_ENABLE + +config MAINBOARD_DIR + string + default amd/f2950 + +config MAINBOARD_PART_NUMBER + string + default "F2950" + +config IRQ_SLOT_COUNT + int + default 3 + +endif # BOARD_AMD_F2950 diff --git a/src/mainboard/amd/f2950/Kconfig.name b/src/mainboard/amd/f2950/Kconfig.name new file mode 100644 index 0000000..8f6073a --- /dev/null +++ b/src/mainboard/amd/f2950/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_F2950 + bool "F2950" diff --git a/src/mainboard/amd/f2950/board_info.txt b/src/mainboard/amd/f2950/board_info.txt new file mode 100644 index 0000000..e957623 --- /dev/null +++ b/src/mainboard/amd/f2950/board_info.txt @@ -0,0 +1,6 @@ +Board name: F2950 +Category: mini +ROM package: PLCC +ROM protocol: FWH +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/amd/f2950/cmos.layout b/src/mainboard/amd/f2950/cmos.layout new file mode 100644 index 0000000..6de5ab6 --- /dev/null +++ b/src/mainboard/amd/f2950/cmos.layout @@ -0,0 +1,36 @@ +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +456 1 e 1 ECC_memory +1008 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew + +checksums + +checksum 392 1007 1008 diff --git a/src/mainboard/amd/f2950/devicetree.cb b/src/mainboard/amd/f2950/devicetree.cb new file mode 100644 index 0000000..4e563d2 --- /dev/null +++ b/src/mainboard/amd/f2950/devicetree.cb @@ -0,0 +1,67 @@ +chip northbridge/amd/lx + device domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # Integrated cryptoaccelerator + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3F8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2F8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci d.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # Com2 + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HW Monitor + end + end + device pci f.2 on end # IDE Controller + device pci f.3 on end # Audio + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device cpu_cluster 0 on + chip cpu/amd/geode_lx + device lapic 0 on end + end + end +end diff --git a/src/mainboard/amd/f2950/irq_tables.c b/src/mainboard/amd/f2950/irq_tables.c new file mode 100644 index 0000000..b438f02 --- /dev/null +++ b/src/mainboard/amd/f2950/irq_tables.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/pirq_routing.h> +#include "southbridge/amd/cs5536/cs5536.h" + +/* Platform IRQs */ +#define PIRQA 11 +#define PIRQB 5 +#define PIRQC 10 +#define PIRQD 10 + +/* Map */ +#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ +#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ +#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ +#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ + +/* Link */ +#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ +#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ +#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ +#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ + +static const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0x00, /* IRQs devoted exclusively to PCI usage */ + 0x100B, /* Vendor */ + 0x002B, /* Device */ + 0, /* Miniport data */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* cpu */ + {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ + {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/amd/f2950/romstage.c b/src/mainboard/amd/f2950/romstage.c new file mode 100644 index 0000000..318149d --- /dev/null +++ b/src/mainboard/amd/f2950/romstage.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/car.h> +#include <cpu/amd/lxdef.h> +#include <southbridge/amd/cs5536/cs5536.h> +#include <spd.h> +#include "southbridge/amd/cs5536/early_smbus.c" +#include "southbridge/amd/cs5536/early_setup.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627hf/w83627hf.h> +#include <northbridge/amd/lx/raminit.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +int spd_read_byte(unsigned int device, unsigned int address) +{ + if (device != DIMM0) + return 0xFF; + + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/lx/pll_reset.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/geode_lx/cpureginit.c" +#include "cpu/amd/geode_lx/syspreinit.c" +#include "cpu/amd/geode_lx/msrinit.c" + +void main(unsigned long bist) +{ + + static const struct mem_controller memctrl[] = { + {.channel0 = {DIMM0, DIMM1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + pll_reset(); + + cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); + + sdram_initialize(1, memctrl); + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +}

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Patch set updated for coreboot: AMD k8 fam10: Fix romstage handoff
by Kyösti Mälkki 09 Jul '16

09 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15472 -gerrit commit 45dac9cc61df28dd58d2af83fffb6b2775395ebc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 26 15:44:05 2016 +0300 AMD k8 fam10: Fix romstage handoff It is not possible for cbmem_add() to complete succesfully before cbmem_recovery() is called. Adding more tables on S3 resume path is also not possible. Change-Id: Ic14857eeef2932562acee4a36f59c22ff4ca1a84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 15b2642..b5faa77 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -130,19 +130,24 @@ void post_cache_as_ram(void) if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = acpi_is_wakeup_s3(); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - int s3resume = acpi_is_wakeup_s3(); - if (s3resume) + + /* Boards with EARLY_CBMEM_INIT need to do this in cache_as_ram_main(). + */ + if (s3resume && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) cbmem_recovery(s3resume); prepare_romstage_ramstack(s3resume); + if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { + struct romstage_handoff *handoff; + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = s3resume; + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + } + /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { /* Family 10h and 12h, 11h until shown otherwise */

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Patch set updated for coreboot: AMD k8 fam10: Drop excessive spinlock initialization
by Kyösti Mälkki 09 Jul '16

09 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15589 -gerrit commit d2c682763888616b3cdf3d0338d737289065239d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 8 11:35:45 2016 +0300 AMD k8 fam10: Drop excessive spinlock initialization If CAR migration operations unintentionally set the lock, BSP would have got stuck on printk() calls above already. Change-Id: I35155ebcb00475a0964fc639ee74ad2755127740 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index b5faa77..9cf3c6e 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -94,13 +94,6 @@ static void prepare_ramstage_region(int s3resume) memset_((void*)0, 0, CONFIG_RAMTOP - backup_top); } -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) - initialize_romstage_console_lock(); -#endif -#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) - initialize_romstage_nvram_cbfs_lock(); -#endif - print_car_debug(" Done\n"); }

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Patch set updated for coreboot: Romstage spinlocks require EARLY_CBMEM_INIT
by Kyösti Mälkki 09 Jul '16

09 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15588 -gerrit commit 7ee40810285c62431225a0444074b08e2bf42b8c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 8 13:33:00 2016 +0300 Romstage spinlocks require EARLY_CBMEM_INIT The lock stores need to migrate from CAR to CBMEM. Change-Id: I3cffd14bdfc57d5588d0f24afe00e0f9891bfe5a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index daba05a..7c1415e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -534,10 +534,12 @@ config HAVE_HARD_RESET config HAVE_ROMSTAGE_CONSOLE_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n help This should be enabled on certain plaforms, such as the AMD @@ -546,6 +548,7 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK bool + depends on EARLY_CBMEM_INIT default n config HAVE_MONOTONIC_TIMER

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Patch merged into coreboot/master: nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM
by gerrit＠coreboot.org 09 Jul '16

09 Jul '16

the following patch was just integrated into master: commit 9ae0985328d53b0a2b1a6673853367061dd695cd Author: Damien Zammit <damien(a)zamaudio.com> Date: Sat Jun 18 23:57:43 2016 +1000 nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM Previously, any 800MHz DIMMs were being slowed to 667MHz for no reason other than there was a bug in the maximum frequency detection code for the MCH. Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/15257 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15257 for details. -gerrit

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Patch set updated for coreboot: arch: Add ARMv7-R configuration
by hakim giydan 08 Jul '16

08 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15335 -gerrit commit 676d39e738ce8088dd55642996282b1c142e95f2 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Fri Jul 8 14:23:31 2016 -0700 arch: Add ARMv7-R configuration This change adds armv7-r configuration for romstage and verstage, and any other files needed to initialize an amrv7-r processor. ARMv7-R is an ARM processor based on the Cortex-R series. Currently, there is already support for the Cortex-M series, so the same files had been renamed and reused for Cortex-R series as well. Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/arch/arm/armv7/Kconfig | 8 ++++ src/arch/arm/armv7/Makefile.inc | 27 ++++++++++++- src/arch/arm/armv7/cache_m.c | 79 --------------------------------------- src/arch/arm/armv7/cache_mr.c | 79 +++++++++++++++++++++++++++++++++++++++ src/arch/arm/armv7/cpu_r.S | 65 ++++++++++++++++++++++++++++++++ src/arch/arm/armv7/exception_m.c | 36 ------------------ src/arch/arm/armv7/exception_mr.c | 36 ++++++++++++++++++ util/xcompile/xcompile | 2 +- 8 files changed, 214 insertions(+), 118 deletions(-) diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index 0ab3542..4fe3fd7 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -19,3 +19,11 @@ config ARCH_BOOTBLOCK_ARMV7_M config ARCH_VERSTAGE_ARMV7_M def_bool n select ARCH_VERSTAGE_ARM + +config ARCH_VERSTAGE_ARMV7_R + def_bool n + select ARCH_VERSTAGE_ARM + +config ARCH_ROMSTAGE_ARMV7_R + def_bool n + select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 2e9c49c..63617f1 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -46,8 +46,8 @@ bootblock-S-ccopts += $(armv7_asm_flags) ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock_m.S endif -bootblock-y += exception_m.c -bootblock-y += cache_m.c +bootblock-y += exception_mr.c +bootblock-y += cache_mr.c endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 @@ -73,6 +73,17 @@ libverstage-S-ccopts += $(armv7_asm_flags) verstage-generic-ccopts += $(armv7-m_flags) verstage-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV7_R),y) +libverstage-generic-ccopts += $(armv7-r_flags) +libverstage-S-ccopts += $(armv7-r_asm_flags) +verstage-generic-ccopts += $(armv7-r_flags) +verstage-S-ccopts += $(armv7-r_asm_flags) + +verstage-y += cache_mr.c +verstage-y += cpu_r.S +verstage-y += exception_mr.c +verstage-y += mmu.c + endif # CONFIG_ARCH_VERSTAGE_ARMV7_M ################################################################################ @@ -91,6 +102,18 @@ romstage-S-ccopts += $(armv7_asm_flags) rmodules_arm-generic-ccopts += $(armv7-a_flags) rmodules_arm-S-ccopts += $(armv7_asm_flags) +else ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7_R),y) +romstage-y += cache_mr.c +romstage-y += cpu_r.S +romstage-y += exception_mr.c +romstage-y += mmu.c + +romstage-generic-ccopts += $(armv7-r_flags) +romstage-S-ccopts += $(armv7-r_asm_flags) + +rmodules_arm-generic-ccopts += $(armv7-r_flags) +rmodules_arm-S-ccopts += $(armv7-r_asm_flags) + endif # CONFIG_ARCH_ROMSTAGE_ARMV7 ############################################################################### diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c deleted file mode 100644 index ec8a970..0000000 --- a/src/arch/arm/armv7/cache_m.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * cache.c: Cache maintenance routines for ARMv7-M - */ - -#include <stdint.h> - -#include <arch/cache.h> - -void tlb_invalidate_all(void) -{ -} - -void dcache_clean_all(void) -{ -} - -void dcache_clean_invalidate_all(void) -{ -} - -void dcache_invalidate_all(void) -{ -} - -unsigned int dcache_line_bytes(void) -{ - return 0; -} - -void dcache_clean_by_mva(void const *addr, size_t len) -{ -} - -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_invalidate_by_mva(void const *addr, size_t len) -{ -} - -void dcache_mmu_disable(void) -{ -} - -void dcache_mmu_enable(void) -{ -} - -void cache_sync_instructions(void) -{ -} diff --git a/src/arch/arm/armv7/cache_mr.c b/src/arch/arm/armv7/cache_mr.c new file mode 100644 index 0000000..ec8a970 --- /dev/null +++ b/src/arch/arm/armv7/cache_mr.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.c: Cache maintenance routines for ARMv7-M + */ + +#include <stdint.h> + +#include <arch/cache.h> + +void tlb_invalidate_all(void) +{ +} + +void dcache_clean_all(void) +{ +} + +void dcache_clean_invalidate_all(void) +{ +} + +void dcache_invalidate_all(void) +{ +} + +unsigned int dcache_line_bytes(void) +{ + return 0; +} + +void dcache_clean_by_mva(void const *addr, size_t len) +{ +} + +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_invalidate_by_mva(void const *addr, size_t len) +{ +} + +void dcache_mmu_disable(void) +{ +} + +void dcache_mmu_enable(void) +{ +} + +void cache_sync_instructions(void) +{ +} diff --git a/src/arch/arm/armv7/cpu_r.S b/src/arch/arm/armv7/cpu_r.S new file mode 100644 index 0000000..6d5820e --- /dev/null +++ b/src/arch/arm/armv7/cpu_r.S @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2010 Per Odlund <per.odlund(a)armagedon.se> + * Copyright (c) 2014 Google Inc. + * Copyright (c) 2016 Marvell Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* + * Bring an ARM processor we just gained control of (e.g. from IROM) into a + * known state regarding caches/SCTLR. Completely cleans and invalidates + * icache/dcache, and dcache (if active), and enables unaligned + * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5. + * + * THIS FUNCTION MUST PRESERVE THE VALUE OF r10 + */ +ENTRY(arm_init_caches) + /* r4: SCTLR, return address: r5 (stay valid for the whole function) */ + mov r5, lr + mrc p15, 0, r4, c1, c0, 0 + + /* Activate ICache (12) and Branch Prediction (11) already for speed */ + orr r4, # (1 << 11) | (1 << 12) + mcr p15, 0, r4, c1, c0, 0 + + /* Flush and invalidate dcache in ascending order */ + bl dcache_invalidate_all + + /* Deactivate Alignment Check (1) and DCache (2) */ + and r4, # ~(1 << 1) & ~(1 << 2) + mcr p15, 0, r4, c1, c0, 0 + + /* Invalidate icache for good measure */ + mcr p15, 0, r0, c7, c5, 0 + + dsb + isb + + bx r5 +ENDPROC(arm_init_caches) diff --git a/src/arch/arm/armv7/exception_m.c b/src/arch/arm/armv7/exception_m.c deleted file mode 100644 index d76cc6a..0000000 --- a/src/arch/arm/armv7/exception_m.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <arch/exception.h> -#include <console/console.h> - -void exception_init(void) -{ - printk(BIOS_DEBUG, "Exception handlers not installed.\n"); -} diff --git a/src/arch/arm/armv7/exception_mr.c b/src/arch/arm/armv7/exception_mr.c new file mode 100644 index 0000000..d76cc6a --- /dev/null +++ b/src/arch/arm/armv7/exception_mr.c @@ -0,0 +1,36 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/exception.h> +#include <console/console.h> + +void exception_init(void) +{ + printk(BIOS_DEBUG, "Exception handlers not installed.\n"); +} diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 13a0e8f..1a9c38c 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -316,7 +316,7 @@ arch_config_arm() { TBFDARCHS="littlearm" TCLIST="armv7-a armv7a arm" TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" + TSUPP="arm armv4 armv7 armv7_m armv7_r" TABI="eabi" }

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coreboot-gerrit July 2016