coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

1 participants
1820 discussions

Patch set updated for coreboot: AMD binaryPI: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15471 -gerrit commit 2e0b4b21dd90491d7acf7de08c7c9d12dc82d288 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:14:49 2016 +0300 AMD binaryPI: Delay ACPI S3 backup until ramstage loader Change-Id: I482cf93fe5dfab95817c87c32aad33df2e0a6439 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/s3_resume.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 6426c97..338f921 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -289,10 +289,5 @@ void prepare_for_resume(void) printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); - /* - * Copy the system memory that is in the ramstage area to the - * reserved area. - */ - acpi_prepare_for_resume(); } #endif

1 0

Patch set updated for coreboot: intel post-car: Delay ACPI S3 backup until ramstage loader
by Kyösti Mälkki 08 Jul '16

08 Jul '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15469 -gerrit commit 75d54f9201e4e71226293cceafe2960ab04a2475 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 27 12:13:48 2016 +0300 intel post-car: Delay ACPI S3 backup until ramstage loader Change-Id: If0060b9ad8703a3d6524004fb69cb2171f8d89a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/sandybridge/early_init.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index f518775..0e7309d 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 1deab65..db1d62f 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -179,7 +179,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c..7b8d7f9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 92ee021..04c9513 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index fc0c8d3..e8bd1e2 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ade120f..3164f25 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -900,7 +900,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index a013ec3..86d1c00 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -234,7 +234,6 @@ void northbridge_romstage_finalize(int s3resume) */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);

1 0

Patch merged into coreboot/master: soc/intel/quark: Pass in the memory initialization parameters
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit dc542702108fc80997f074978ac404c83ee0e9bf Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jun 18 18:52:43 2016 -0700 soc/intel/quark: Pass in the memory initialization parameters Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15260 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15260 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/intel/galileo: Gen1 - Set correct I2C scripts
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit 5d94c2665360aad315b494b9ed47ed7f33a695a5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jun 18 09:54:43 2016 -0700 mainboard/intel/galileo: Gen1 - Set correct I2C scripts Switch the I2C scripts to properly match the I2C address selection for the Galileo Gen1 board. TEST=Build an run on Galileo Gen1 Change-Id: I9fc8b59a3a719abb474c99a83e0d538794626da9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15258 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15258 for details. -gerrit

1 0

Patch merged into coreboot/master: Documentation/Intel: Add feature documentation table
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit 24ba659d08cf6e4cbd32608105333e355dcecf2e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jun 18 08:40:28 2016 -0700 Documentation/Intel: Add feature documentation table Add table containing feature documentation: * Feature name with link to specification or documentation * Linux utility name with link to utility documentation * EDK-II utility name with link to utility documentation Change-Id: Ie33d8563320697c12b34974286bffcadf92c016e Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15256 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15256 for details. -gerrit

1 0

Patch merged into coreboot/master: Documentation: Add index.html
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit 8b022dd8843f7d63d3833d40279c161c8fa2c44a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jun 16 12:40:24 2016 -0700 Documentation: Add index.html Add the initial index.html file. The web server is currently not converting .md files into html. Instead they are being downloaded in their raw .md file format. Use the index.html file to enable the web server to find and process the file. TEST=None Change-Id: I27334ccacdb34b56946a9061132acf2808d32175 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15218 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15218 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/quark: Remove use of PDAT.bin file
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit e98d72e2a31c51739fdd997022155b7178e94828 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 15 12:29:51 2016 -0700 soc/intel/quark: Remove use of PDAT.bin file Remove the unused Kconfig values which specify the PDAT file, its location and inclusion into the coreboot file system. Remove the code in romstage which locates the pdat.bin file. TEST=Build and run on Galileo Gen2 Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15205 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15205 for details. -gerrit

1 0

Patch merged into coreboot/master: soc/intel/apollolake: Include gpio_defs header
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit d9fc5fb31b5496d4257f1ac1ab5afec8a559c19c Author: Harsha Priya <harshapriya.n(a)intel.com> Date: Wed Jul 6 12:00:49 2016 -0700 soc/intel/apollolake: Include gpio_defs header Add the gpio_defs.h reference in chip.h to enable reef and amenia devicetree.cb to use the definitions from gpio_defs.h. Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517b1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Reviewed-on: https://review.coreboot.org/15550 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15550 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/google/reef: Use device driver for DA7219 configuration
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit 5edbb0427c912a8a3ac90eb03aa378398342d358 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 20:05:43 2016 -0700 mainboard/google/reef: Use device driver for DA7219 configuration Use the device driver for DA7219 device configuration in the SSDT and remove the static copy in the DSDT. Tested on reef to ensure that the generated SSDT contents are equivalent to the current DSDT contents. Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15539 for details. -gerrit

1 0

Patch merged into coreboot/master: drivers/i2c/da7219: Add driver for generating device in SSDT
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit dba7e76da1e32d1761a0aaaca2e50d19298becce Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 20:00:56 2016 -0700 drivers/i2c/da7219: Add driver for generating device in SSDT Add a device driver to generate the device and required properties into the SSDT. This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel. This was tested on the reef mainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object. Change-Id: Ia809e953932a7e127352a7ef193974d95e511565 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15538 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15538 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2016