coreboot-gerrit July 2016

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Patch merged into coreboot/master: acpi: Change device properties to work as a tree
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit ffc9990ece4c6a2148ba0a43de85f1b8ac9343ee Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Jul 2 19:56:06 2016 -0700 acpi: Change device properties to work as a tree There is a second ACPI _DSD document from the UEFI Forum that details how _DSD style tables can be nested, creating a tree of similarly formatted tables. This document is linked from acpi_device.h. In order to support this the device property interface needs to be more flexible and build up a tree of properties to write all entries at once instead of writing each entry as it is generated. In the end this is a more flexible solution that can support drivers that need child tables like the DA7219 codec, while only requiring minor changes to the existing drivers that use the device property interface. This was tested on reef (apollolake) and chell (skylake) boards to ensure that there was no change in the generated SSDT AML. Change-Id: Ia22e3a5fd3982ffa7c324bee1a8d190d49f853dd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15537 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15537 for details. -gerrit

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Patch merged into coreboot/master: google/reef: Add Maxim98357a support
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit 9217f9def0fa1282fc2b510ac143c751a055dee2 Author: Harsha Priya <harshapriya.n(a)intel.com> Date: Fri Jun 24 17:13:54 2016 -0700 google/reef: Add Maxim98357a support Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Reviewed-on: https://review.coreboot.org/15435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15435 for details. -gerrit

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Patch set updated for coreboot: soc/intel/quark: Remove use of PDAT.bin file
by Leroy P Leahy 08 Jul '16

08 Jul '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15205 -gerrit commit 7527cf169a0dc6df58a79be879a352d17f6ae678 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 15 12:29:51 2016 -0700 soc/intel/quark: Remove use of PDAT.bin file Remove the unused Kconfig values which specify the PDAT file, its location and inclusion into the coreboot file system. Remove the code in romstage which locates the pdat.bin file. TEST=Build and run on Galileo Gen2 Change-Id: I397aa22ada6c073c60485a735d6e2cb42bfd40ab Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 32 -------------------------------- src/soc/intel/quark/Makefile.inc | 6 ------ src/soc/intel/quark/romstage/romstage.c | 11 ----------- 3 files changed, 49 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 37b669d..6669d81 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -204,38 +204,6 @@ config RELOCATE_FSP_INTO_DRAM Relocate the FSP binary into DRAM before the call to SiliconInit. ##### -# FSP PDAT binary -# The following options control the FSP platform data binary -# file placement in the flash image. -##### - -config ADD_FSP_PDAT_FILE - bool "Should the PDAT binary be added to the flash image?" - default n - depends on PLATFORM_USES_FSP1_1 - help - The PDAT file is required for the FSP 1.1 binary - -config FSP_PDAT_FILE - string - default "3rdparty/blobs/soc/intel/quark/pdat.bin" - depends on PLATFORM_USES_FSP1_1 - depends on ADD_FSP_PDAT_FILE - help - The path and filename of the Intel Galileo platform-data-patch (PDAT) - binary. This binary file is generated by the platform-data-patch.py - script released with the Quark BSP and contains the Ethernet address. - -config FSP_PDAT_LOC - hex - default 0xfff10000 - depends on PLATFORM_USES_FSP1_1 - depends on ADD_FSP_PDAT_FILE - help - The location in CBFS that the PDAT is located. It must match the - PCD PcdPlatformDataBaseAddress of Quark SoC FSP. - -##### # RMU binary # The following options control the Quark chipset microcode file # placement in the flash image. This file is required to bring diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index edbb8be..f5b9746 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -56,12 +56,6 @@ fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := raw -# Add the platform data file to the CBFS image -cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin -pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) -pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) -pdat.bin-type := raw - # Add the chipset microcode file to the CBFS image cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c14acb7..b99ad54 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -127,20 +127,9 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) { const struct device *dev; - char *pdat_file; - size_t pdat_file_len; const struct soc_intel_quark_config *config; struct chipset_power_state *ps = car_get_var_ptr(&power_state); - /* Locate the pdat.bin file */ - pdat_file = cbfs_boot_map_with_leak("pdat.bin", CBFS_TYPE_RAW, - &pdat_file_len); - if (!pdat_file) { - printk(BIOS_DEBUG, - "Platform configuration file (pdat.bin) not found."); - pdat_file_len = 0; - } - /* Locate the configuration data from devicetree.cb */ dev = dev_find_slot(0, LPC_DEV_FUNC); if (!dev) {

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Patch set updated for coreboot: soc/intel/quark: Pass in the memory initialization parameters
by Leroy P Leahy 08 Jul '16

08 Jul '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15260 -gerrit commit 78b4031abda123cb90524af2fe808528cd9a9963 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jun 18 18:52:43 2016 -0700 soc/intel/quark: Pass in the memory initialization parameters Specify the memory initialization parameters in mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to initialize memory. TEST=Build and run on Galileo Gen2 Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/Galileo_checklist.html | 10 +-- src/mainboard/intel/galileo/devicetree.cb | 27 +++++- src/soc/intel/quark/chip.h | 79 ++++++++++++++++- src/soc/intel/quark/romstage/romstage.c | 101 ++++++++++++++++++++-- src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 101 +++++++++++++++++++--- 5 files changed, 293 insertions(+), 25 deletions(-) diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html index ba1469b..3fc04b1 100644 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -3,7 +3,7 @@ <title>Galileo Implementation Status</title> </title> <body> -<h1>Galileo Implementation Status<br>2016/06/08 17:18:24 PDT</h1> +<h1>Galileo Implementation Status<br>2016/07/08 06:51:34 PDT</h1> <table> <tr><td colspan=2><b>Legend</b></td></tr> <tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr> @@ -31,7 +31,7 @@ <td width=5> </td> <td> <table border=1> -<tr><th colspan=2>romstage: 66% Done</th></tr> +<tr><th colspan=2>romstage: 67% Done</th></tr> <tr><th>Type</th><th>Routine</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> @@ -78,7 +78,7 @@ <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr> <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> @@ -98,7 +98,7 @@ <td width=5> </td> <td> <table border=1> -<tr><th colspan=2>ramstage: 55% Done</th></tr> +<tr><th colspan=2>ramstage: 60% Done</th></tr> <tr><th>Type</th><th>Routine</td></tr> <tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> @@ -138,7 +138,7 @@ <tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_silicon_init_params</td></tr> <tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr> diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index fcc0dae..f7d666d 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -20,7 +20,32 @@ chip soc/intel/quark # Set the parameters for MemoryInit ############################################################ - register "PcdSmmTsegSize" = "0" # SMM Region size in MiB + register "AddrMode" = "0" + register "ChanMask" = "1" # Channel 0 enabled + register "ChanWidth" = "1" # 16-bit channel + register "DramDensity" = "1" # 1 Gib; + register "DramRonVal" = "0" # 34 Ohm + register "DramRttNomVal" = "2" # 120 Ohm + register "DramRttWrVal" = "0" # off + register "DramSpeed" = "0" # 800 MHz + register "DramType" = "0" # DDR3 + register "DramWidth" = "0" # 8-bit + register "EccScrubBlkSize" = "2" # 64 byte blocks + register "EccScrubInterval" = "0" # ECC scrub disabled + register "Flags" = "MRC_FLAG_SCRAMBLE_EN" + register "FspReservedMemoryLength" = "0x00100000" # Size in bytes + register "RankMask" = "1" # RANK 0 enabled + register "SmmTsegSize" = "0" # SMM Region size in MiB + register "SocRdOdtVal" = "0" # off + register "SocWrRonVal" = "1" # 32 Ohm + register "SocWrSlewRate" = "1" # 4V/nSec + register "SrInt" = "3" # 7.8 uSec + register "SrTemp" = "0" # normal + register "tCL" = "6" # clocks + register "tFAW" = "40000" # picoseconds + register "tRAS" = "37500" # picoseconds + register "tRRD" = "10000" # picoseconds + register "tWTR" = "10000" # picoseconds ############################################################ # Enable the devices diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index fc9890f..66105ea 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -23,6 +23,19 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +/// +/// MRC Flags bits +/// +#define MRC_FLAG_ECC_EN BIT0 +#define MRC_FLAG_SCRAMBLE_EN BIT1 +#define MRC_FLAG_MEMTEST_EN BIT2 + +/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ +#define MRC_FLAG_TOP_TREE_EN BIT3 + +/* If set ODR signal is asserted to DRAM devices on writes */ +#define MRC_FLAG_WR_ODT_EN BIT4 + struct soc_intel_quark_config { /* * MemoryInit: @@ -33,7 +46,71 @@ struct soc_intel_quark_config { * built into the coreboot image. The fields below contain retain * the FSP PCD field name. */ - UINT16 PcdSmmTsegSize; + + UINT32 FspReservedMemoryLength; /* FSP reserved memory in bytes */ + + UINT32 Flags; /* Bitmap of MRC_FLAG_XXX defs above */ + UINT32 tRAS; /* ACT to PRE command period in picoseconds */ + + /* Delay from start of internal write transaction to internal read + * command in picoseconds + */ + UINT32 tWTR; + + /* ACT to ACT command period (JESD79 specific to page size 1K/2K) in + * picoseconds + */ + UINT32 tRRD; + + /* Four activate window (JESD79 specific to page size 1K/2K) in + * picoseconds + */ + UINT32 tFAW; + UINT8 DramWidth; /* 0=x8, 1=x16, others=RESERVED */ + + /* 0=DDRFREQ_800, 1=DDRFREQ_1066, others=RESERVED. Only 533MHz SKU + * support 1066 memory + */ + UINT8 DramSpeed; + UINT8 DramType; /* 0=DDR3,1=DDR3L, others=RESERVED */ + + /* bit[0] RANK0_EN, bit[1] RANK1_EN, others=RESERVED */ + UINT8 RankMask; + UINT8 ChanMask; /* bit[0] CHAN0_EN, others=RESERVED */ + UINT8 ChanWidth; /* 1=x16, others=RESERVED */ + + /* 0, 1, 2 (mode 2 forced if ecc enabled), others=RESERVED */ + UINT8 AddrMode; + + /* 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED. REFRESH_RATE */ + UINT8 SrInt; + UINT8 SrTemp; /* 0=normal, 1=extended, others=RESERVED */ + + /* 0=34ohm, 1=40ohm, others=RESERVED. RON_VALUE Select MRS1.DIC driver + * impedance control. + */ + UINT8 DramRonVal; + UINT8 DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ + UINT8 DramRttWrVal; /* 0=off others=RESERVED */ + + /* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ + UINT8 SocRdOdtVal; + UINT8 SocWrRonVal; /* 0=27ohm, 1=32ohm, 2=40ohm, others=RESERVED */ + UINT8 SocWrSlewRate; /* 0=2.5V/ns, 1=4V/ns, others=RESERVED */ + + /* 0=512Mb, 1=1Gb, 2=2Gb, 3=4Gb, others=RESERVED */ + UINT8 DramDensity; + UINT8 tCL; /* DRAM CAS Latency in clocks */ + + /* ECC scrub interval in miliseconds 1..255 (0 works as feature + * disable) + */ + UINT8 EccScrubInterval; + + /* Number of 32B blocks read for ECC scrub 2..16 */ + UINT8 EccScrubBlkSize; + + UINT8 SmmTsegSize; /* SMM size in MiB */ }; extern struct chip_operations soc_ops; diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index b99ad54..2a4c658 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -129,6 +129,8 @@ void soc_memory_init_params(struct romstage_params *params, const struct device *dev; const struct soc_intel_quark_config *config; struct chipset_power_state *ps = car_get_var_ptr(&power_state); + char *rmu_file; + size_t rmu_file_len; /* Locate the configuration data from devicetree.cb */ dev = dev_find_slot(0, LPC_DEV_FUNC); @@ -150,11 +152,44 @@ void soc_memory_init_params(struct romstage_params *params, reg_script_run_on_dev(LPC_BDF, clear_smi_and_wake_events); } + /* Locate the RMU data file in flash */ + rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW, + &rmu_file_len); + if (!rmu_file) + die("Microcode file (rmu.bin) not found."); + /* Update the UPD data for MemoryInit */ printk(BIOS_DEBUG, "Updating UPD values for MemoryInit: 0x%p\n", upd); - upd->PcdSerialRegisterBase = UART_BASE_ADDRESS; - upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->PcdSmmTsegSize : 0; + upd->AddrMode = config->AddrMode; + upd->ChanMask = config->ChanMask; + upd->ChanWidth = config->ChanWidth; + upd->DramDensity = config->DramDensity; + upd->DramRonVal = config->DramRonVal; + upd->DramRttNomVal = config->DramRttNomVal; + upd->DramRttWrVal = config->DramRttWrVal; + upd->DramSpeed = config->DramSpeed; + upd->DramType = config->DramType; + upd->DramWidth = config->DramWidth; + upd->EccScrubBlkSize = config->EccScrubBlkSize; + upd->EccScrubInterval = config->EccScrubInterval; + upd->Flags = config->Flags; + upd->FspReservedMemoryLength = config->FspReservedMemoryLength; + upd->RankMask = config->RankMask; + upd->RmuBaseAddress = (uintptr_t)rmu_file; + upd->RmuLength = rmu_file_len; + upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? + config->SmmTsegSize : 0; + upd->SocRdOdtVal = config->SocRdOdtVal; + upd->SocWrRonVal = config->SocWrRonVal; + upd->SocWrSlewRate = config->SocWrSlewRate; + upd->SrInt = config->SrInt; + upd->SrTemp = config->SrTemp; + upd->tCL = config->tCL; + upd->tFAW = config->tFAW; + upd->tRAS = config->tRAS; + upd->tRRD = config->tRRD; + upd->tWTR = config->tWTR; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -162,11 +197,61 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, { /* Display the parameters for MemoryInit */ printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new); - fsp_display_upd_value("PcdSerialRegisterBase", - sizeof(old->PcdSerialRegisterBase), - old->PcdSerialRegisterBase, new->PcdSerialRegisterBase); - fsp_display_upd_value("PcdSmmTsegSize", sizeof(old->PcdSmmTsegSize), - old->PcdSmmTsegSize, new->PcdSmmTsegSize); + fsp_display_upd_value("AddrMode", sizeof(old->AddrMode), + old->AddrMode, new->AddrMode); + fsp_display_upd_value("ChanMask", sizeof(old->ChanMask), + old->ChanMask, new->ChanMask); + fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth), + old->ChanWidth, new->ChanWidth); + fsp_display_upd_value("DramDensity", sizeof(old->DramDensity), + old->DramDensity, new->DramDensity); + fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal), + old->DramRonVal, new->DramRonVal); + fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal), + old->DramRttNomVal, new->DramRttNomVal); + fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal), + old->DramRttWrVal, new->DramRttWrVal); + fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed), + old->DramSpeed, new->DramSpeed); + fsp_display_upd_value("DramType", sizeof(old->DramType), + old->DramType, new->DramType); + fsp_display_upd_value("DramWidth", sizeof(old->DramWidth), + old->DramWidth, new->DramWidth); + fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize), + old->EccScrubBlkSize, new->EccScrubBlkSize); + fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval), + old->EccScrubInterval, new->EccScrubInterval); + fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags, + new->Flags); + fsp_display_upd_value("FspReservedMemoryLength", + sizeof(old->FspReservedMemoryLength), + old->FspReservedMemoryLength, new->FspReservedMemoryLength); + fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask, + new->RankMask); + fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress), + old->RmuBaseAddress, new->RmuBaseAddress); + fsp_display_upd_value("RmuLength", sizeof(old->RmuLength), + old->RmuLength, new->RmuLength); + fsp_display_upd_value("SerialPortBaseAddress", + sizeof(old->SerialPortBaseAddress), + old->SerialPortBaseAddress, new->SerialPortBaseAddress); + fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize), + old->SmmTsegSize, new->SmmTsegSize); + fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal), + old->SocRdOdtVal, new->SocRdOdtVal); + fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal), + old->SocWrRonVal, new->SocWrRonVal); + fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate), + old->SocWrSlewRate, new->SocWrSlewRate); + fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt, + new->SrInt); + fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp, + new->SrTemp); + fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL); + fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW); + fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS); + fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD); + fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR); } void soc_after_ram_init(struct romstage_params *params) diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h index 86f5487..2c7e812 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -85,29 +85,110 @@ typedef struct { UINT64 Revision; /** Offset 0x0028 **/ - UINT32 PcdRmuBinaryBaseAddress; + UINT32 RmuBaseAddress; /** Offset 0x002C **/ - UINT32 UnusedUpdSpace0; + UINT32 RmuLength; /** Offset 0x0030 **/ - UINT32 PcdSerialRegisterBase; + UINT32 SerialPortBaseAddress; /** Offset 0x0034 **/ - UINT8 PcdSmmTsegSize; -/** Offset 0x0035 + UINT32 tRAS; +/** Offset 0x0038 +**/ + UINT32 tWTR; +/** Offset 0x003C +**/ + UINT32 tRRD; +/** Offset 0x0040 +**/ + UINT32 tFAW; +/** Offset 0x0044 +**/ + UINT32 Flags; +/** Offset 0x0048 +**/ + UINT8 DramWidth; +/** Offset 0x0049 +**/ + UINT8 DramSpeed; +/** Offset 0x004A +**/ + UINT8 DramType; +/** Offset 0x004B +**/ + UINT8 RankMask; +/** Offset 0x004C +**/ + UINT8 ChanMask; +/** Offset 0x004D +**/ + UINT8 ChanWidth; +/** Offset 0x004E +**/ + UINT8 AddrMode; +/** Offset 0x004F +**/ + UINT8 SrInt; +/** Offset 0x0050 +**/ + UINT8 SrTemp; +/** Offset 0x0051 +**/ + UINT8 DramRonVal; +/** Offset 0x0052 **/ - UINT8 ReservedMemoryInitUpd[3]; + UINT8 DramRttNomVal; +/** Offset 0x0053 +**/ + UINT8 DramRttWrVal; +/** Offset 0x0054 +**/ + UINT8 SocRdOdtVal; +/** Offset 0x0055 +**/ + UINT8 SocWrRonVal; +/** Offset 0x0056 +**/ + UINT8 SocWrSlewRate; +/** Offset 0x0057 +**/ + UINT8 DramDensity; +/** Offset 0x0058 +**/ + UINT8 tCL; +/** Offset 0x0059 +**/ + UINT8 EccScrubInterval; +/** Offset 0x005A +**/ + UINT8 EccScrubBlkSize; +/** Offset 0x005B +**/ + UINT8 SmmTsegSize; +/** Offset 0x005C +**/ + UINT32 FspReservedMemoryLength; +/** Offset 0x0060 +**/ + UINT32 MrcDataPtr; +/** Offset 0x0064 +**/ + UINT32 MrcDataLength; +/** Offset 0x0068 +**/ + UINT8 ReservedMemoryInitUpd[8]; } MEMORY_INIT_UPD; typedef struct { -/** Offset 0x0038 +/** Offset 0x0070 **/ UINT64 Signature; -/** Offset 0x0040 +/** Offset 0x0078 **/ UINT64 Revision; -/** Offset 0x0048 +/** Offset 0x0080 **/ UINT16 PcdRegionTerminator; } SILICON_INIT_UPD; @@ -132,7 +213,7 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x0018 **/ MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0038 +/** Offset 0x0070 **/ SILICON_INIT_UPD SiliconInitUpd; } UPD_DATA_REGION;

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Patch merged into coreboot/master: siemens/mc_bdx1: Move SCI to IRQ 10
by gerrit＠coreboot.org 08 Jul '16

08 Jul '16

the following patch was just integrated into master: commit a845f427fee1f0870b7b673a0675ba04408bea57 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jul 7 07:10:50 2016 +0200 siemens/mc_bdx1: Move SCI to IRQ 10 IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/15563 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/15563 for details. -gerrit

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Patch set updated for coreboot: siemens/mc_bdx1: Move SCI to IRQ 10
by Werner Zeh 08 Jul '16

08 Jul '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15563 -gerrit commit 4105e2b15ce4517b89f17227fa446048fe066eb5 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Jul 7 07:10:50 2016 +0200 siemens/mc_bdx1: Move SCI to IRQ 10 IRQ 9 is used for different purpose on this board so move SCI away to IRQ10. Change-Id: I107bfb5ec8cd05f844ee75550779be7746e77a88 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/irqroute.h | 2 +- src/mainboard/siemens/mc_bdx1/mainboard.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.h b/src/mainboard/siemens/mc_bdx1/irqroute.h index c3911be..3b437fe 100644 --- a/src/mainboard/siemens/mc_bdx1/irqroute.h +++ b/src/mainboard/siemens/mc_bdx1/irqroute.h @@ -33,7 +33,7 @@ /* * Route each PIRQ[A-H] to a PIC IRQ[0-15] * Reserved: 0, 1, 2, 8, 13 - * ACPI/SCI: 9 + * ACPI/SCI: 10 */ #define PIRQ_PIC_ROUTES \ PIRQ_PIC(A, 5), \ diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index bad072b..8a5226b 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -32,6 +32,7 @@ #include <hwilib.h> #include <i210.h> #include <soc/pci_devs.h> +#include <soc/irq.h> #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -91,6 +92,18 @@ static void mainboard_enable(device_t dev) } +static void mainboard_init(void *chip_info) +{ + uint8_t actl = 0; + device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + /* Route SCI to IRQ 10 to free IRQ 9 slot. */ + actl = pci_read_config8(dev, ACPI_CNTL_OFFSET); + actl &= ~SCIS_MASK; + actl |= SCIS_IRQ10; + pci_write_config8(dev, ACPI_CNTL_OFFSET, actl); +} + static void mainboard_final(void *chip_info) { void *spi_base = NULL; @@ -183,5 +196,6 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .init = mainboard_init, .final = mainboard_final };

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Patch set updated for coreboot: soc/intel/apollolake: Add handler for SCI
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15578 -gerrit commit 2543380b0f66beadaa5e44646f0d82b875fd087f Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Thu Jul 7 14:48:21 2016 -0700 soc/intel/apollolake: Add handler for SCI This patch adds the handler to enable bit for gpio_tier1_sci_en. gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event and/or an SCI or SMI#. Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl index 4bf0442..7d115ed 100644 --- a/src/soc/intel/apollolake/acpi/gpio.asl +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -142,3 +142,9 @@ scope (\_SB) { } } } + +Scope(\_GPE) +{ + /* Dummy method for the Tier 1 GPIO SCI enable bit */ + Method(_L0F, 0) {} +}

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Patch set updated for coreboot: google/reef: Add GPE routing settings
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15556 -gerrit commit 308d80dca5892c27c5960e7db0aa56e57be99b12 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Jul 6 15:50:48 2016 -0700 google/reef: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 9 +++++++++ src/mainboard/google/reef/ec.h | 8 +++++--- src/mainboard/google/reef/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..f0fefd1 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,15 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 5a32697..3619c04 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,9 +18,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..eddefeb 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ + PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */

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Patch set updated for coreboot: google/reef: Add GPE routing settings
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15556 -gerrit commit e340c41f503a3fd52a9dd55724016bac34172630 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Jul 6 15:50:48 2016 -0700 google/reef: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: If258bece12768edb1e612c982514ce95c756c438 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/devicetree.cb | 9 +++++++++ src/mainboard/google/reef/ec.h | 8 +++++--- src/mainboard/google/reef/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..7f6d189 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,15 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., If this route changes then the affected GPE + # offset bits also needs to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 5a32697..3619c04 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,9 +18,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index 91e8bb1..eddefeb 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -283,7 +283,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI_APIC(GPIO_9, NONE, DEEP, LEVEL, NONE), /* dTPM IRQ */ PAD_CFG_GPI(GPIO_10, UP_20K, DEEP), /* unused */ - PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, LEVEL, NONE), /* EC SCI */ + PAD_CFG_GPI_SCI(GPIO_11, NONE, DEEP, EDGE_SINGLE, INVERT), /* EC SCI */ PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */ PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* unused */ PAD_CFG_GPI_APIC(GPIO_14, UP_20K, DEEP, LEVEL, NONE), /* FP IRQ */

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Patch set updated for coreboot: intel/amenia: Add GPE routing settings
by Shaunak Saha 08 Jul '16

08 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15325 -gerrit commit 52ca1bbc77ff614fd665b5f5df65501bdc30121b Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri Jun 10 19:36:49 2016 -0700 intel/amenia: Add GPE routing settings This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. EC_SCI_GPI is configured to proper value. BUG = chrome-os-partner:53438 TEST = Toggle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupt Change-Id: I3ae9ef7c6a3c8688bcb6cb4c73f5618e7cde342c Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 9 +++++++++ src/mainboard/intel/amenia/ec.h | 8 +++++--- src/mainboard/intel/amenia/gpio.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..427ceab 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,15 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/amenia/ec.h b/src/mainboard/intel/amenia/ec.h index 91890fd..ba3962a 100644 --- a/src/mainboard/intel/amenia/ec.h +++ b/src/mainboard/intel/amenia/ec.h @@ -20,9 +20,11 @@ #include <ec/google/chromeec/ec_commands.h> -/* This is the GPE status bit. - TODO: Fix this to proper bit matching GPE routing table */ -#define EC_SCI_GPI 15 +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/amenia/gpio.h b/src/mainboard/intel/amenia/gpio.h index 87d6190..a39cca3 100644 --- a/src/mainboard/intel/amenia/gpio.h +++ b/src/mainboard/intel/amenia/gpio.h @@ -239,7 +239,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ PAD_NC(GPIO_10, DN_20K), /* RSVD for MIPI (unused) */ - PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* SOC_WAKE_SCI_N */ PAD_NC(GPIO_12, DN_20K), PAD_NC(GPIO_13, DN_20K),

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coreboot-gerrit July 2016