coreboot-gerrit June 2016

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New patch to review for coreboot: libpayload: usb: xhci: Support rockchip xHCI controller
by Martin Roth 08 Jun '16

08 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15111 -gerrit commit 14ad5e41f989fdaf3893172e88a0ea74a83f9c65 Author: Liangfeng Wu <wulf(a)rock-chips.com> Date: Tue May 24 19:40:46 2016 +0800 libpayload: usb: xhci: Support rockchip xHCI controller 1. Make the xHCI driver to support xHCI controller v1.1 2. And a new function xhci_ring_doorbell(), it aims to add a memory barrier before ring the doorbell, ensure all TRB changes are written to memory. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB on Kevin rk3399 platform Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9 Original-Signed-off-by: Liangfeng Wu <wulf(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/346831 Original-Commit-Ready: Brian Norris <briannorris(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/usb/xhci.c | 19 ++++++++++++++----- payloads/libpayload/drivers/usb/xhci_private.h | 2 +- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index d223d0f..2e70316 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -197,7 +197,7 @@ xhci_init (unsigned long physical_bar) xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n", xhci->capreg->hciver_hi, xhci->capreg->hciver_lo); if ((xhci->capreg->hciversion < 0x96) || - (xhci->capreg->hciversion > 0x100)) { + (xhci->capreg->hciversion > 0x110)) { xhci_debug("Unsupported xHCI version\n"); goto _free_xhci; } @@ -534,6 +534,15 @@ xhci_enqueue_trb(transfer_ring_t *const tr) } static void +xhci_ring_doorbell(endpoint_t *const ep) +{ + /* Ensure all TRB changes are written to memory. */ + wmb(); + XHCI_INST(ep->dev->controller)->dbreg[ep->dev->address] = + xhci_ep_id(ep); +} + +static void xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, const int dalen, void *const data, const int dir) { @@ -670,7 +679,7 @@ xhci_control(usbdev_t *const dev, const direction_t dir, xhci_enqueue_trb(tr); /* Ring doorbell for EP0 */ - xhci->dbreg[dev->address] = 1; + xhci_ring_doorbell(&dev->endpoints[0]); /* Wait for transfer events */ int i, transferred = 0; @@ -745,7 +754,7 @@ xhci_bulk(endpoint_t *const ep, const int size, u8 *const src, const unsigned mps = EC_GET(MPS, epctx); const unsigned dir = (ep->direction == OUT) ? TRB_DIR_OUT : TRB_DIR_IN; xhci_enqueue_td(tr, ep_id, mps, size, data, dir); - xhci->dbreg[ep->dev->address] = ep_id; + xhci_ring_doorbell(ep); /* Wait for transfer event */ const int ret = xhci_wait_for_transfer(xhci, ep->dev->address, ep_id); @@ -852,7 +861,7 @@ xhci_create_intr_queue(endpoint_t *const ep, and ring the doorbell. */ for (i = 0; i < (reqcount - 1); ++i) xhci_enqueue_trb(tr); - xhci->dbreg[slot_id] = ep_id; + xhci_ring_doorbell(ep); return intrq; @@ -930,7 +939,7 @@ xhci_poll_intr_queue(void *const q) /* Enqueue the last (spare) TRB and ring doorbell */ xhci_enqueue_trb(tr); - xhci->dbreg[ep->dev->address] = ep_id; + xhci_ring_doorbell(ep); /* Reuse the current buffer for the next spare TRB */ xhci_clear_trb(tr->cur, tr->pcs); diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index f644425..47a464f 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -515,7 +515,7 @@ int xhci_cmd_stop_endpoint(xhci_t *, int slot_id, int ep); int xhci_cmd_set_tr_dq(xhci_t *, int slot_id, int ep, trb_t *, int dcs); static inline int xhci_ep_id(const endpoint_t *const ep) { - return ((ep->endpoint & 0x7f) << 1) + (ep->direction == IN); + return ((ep->endpoint & 0x7f) * 2) + (ep->direction != OUT); }

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New patch to review for coreboot: soc/apollolake: Include PCI _OSC method
by Hannah Williams 08 Jun '16

08 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15110 -gerrit commit 0e9ccb7d6e771c3397ff3bcf9db3ac609c5ee9ef Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:47:09 2016 -0700 soc/apollolake: Include PCI _OSC method Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/acpi/southbridge.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 44c440e..5b29abb 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -30,3 +30,6 @@ /* LPC */ #include "lpc.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl>

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Patch set updated for coreboot: soc/intel/common: Add _OSC method
by Hannah Williams 08 Jun '16

08 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15021 -gerrit commit 7356ed44cf3f312ff1c966406b8aed697f47b651 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:45:20 2016 -0700 soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/acpi/pci_osc.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/intel/common/acpi/pci_osc.asl b/src/soc/intel/common/acpi/pci_osc.asl new file mode 100644 index 0000000..4179e94 --- /dev/null +++ b/src/soc/intel/common/acpi/pci_osc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +}

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Patch set updated for coreboot: skylake: Support common LPSS I2C driver
by Duncan Laurie 08 Jun '16

08 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15105 -gerrit commit 44d7e32f39b0f376d6d468b9c7372ccb7dccc20d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 7 16:40:19 2016 -0700 skylake: Support common LPSS I2C driver Support the common Intel LPSS I2C driver for the 6 I2C bus controllers that are present on the Skylake-LP PCH with a 120 mHz clock. The required lpss_i2c_base_address() method is implemented separately for verstage/romstage and ramstage environments. This provides methods to convert to and from "struct device" and the I2C controller bus number for that device. These are used to provide support for the "I2C Bus Operations" that are present in the coreboot devicetree. To support the I2C controller before ramstage an early init function is provided to do minimal initializaiton of the PCI device and assign a temporary base address for use before memory. The final base address is assigned during device enumeration and used during ramstage. Because it is usually not necessary to enable I2C controllers before ramstage a config register for the devicetree is provided to perform early initialization of this controller. In addition the bus speed can be set in the devicetree and that speed will be applied when the device is initialized. If not provided the default speed is set to I2C_SPEED_FAST. This was tested with the google/chell mainboard by reading and writing from the trackpad and codec devices during both verstage and ramstage. Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 5 ++ src/soc/intel/skylake/chip.h | 5 ++ src/soc/intel/skylake/i2c.c | 50 ++++++++++++++ src/soc/intel/skylake/include/soc/iomap.h | 3 + src/soc/intel/skylake/include/soc/pci_devs.h | 29 +++++++++ src/soc/intel/skylake/include/soc/romstage.h | 1 + src/soc/intel/skylake/romstage/Makefile.inc | 2 + src/soc/intel/skylake/romstage/i2c.c | 97 ++++++++++++++++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 1 + 9 files changed, 193 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9278cf1..a134d1c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP @@ -72,6 +73,10 @@ config CPU_ADDR_BITS int default 36 +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + int + default 120 + config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1d3113f..fe03e59 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -20,6 +20,7 @@ #define _SOC_CHIP_H_ #include <arch/acpi_device.h> +#include <device/i2c.h> #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> @@ -39,6 +40,10 @@ enum skylake_i2c_voltage { struct skylake_i2c_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage voltage; + /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ + enum i2c_speed speed; + /* Bus should be enabled prior to ramstage with temporary base */ + int early_init; }; struct soc_intel_skylake_config { diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 76e7bf1..64d39cd 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -14,16 +14,66 @@ */ #include <device/device.h> +#include <device/i2c.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/intel/common/lpss_i2c.h> #include <soc/ramstage.h> +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + struct device *dev; + struct resource *res; + + /* bus -> devfn */ + devfn = i2c_bus_to_devfn(bus); + if (devfn >= 0) { + /* devfn -> dev */ + dev = dev_find_slot(0, devfn); + if (dev) { + /* dev -> bar0 */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + return res->base; + } + } + + return (uintptr_t)NULL; +} + +static int i2c_dev_to_bus(struct device *dev) +{ + return i2c_devfn_to_bus(dev->path.pci.devfn); +} + +/* + * The device should already be enabled and out of reset, + * either from early init in coreboot or SiliconInit in FSP. + */ +static void i2c_dev_init(struct device *dev) +{ + struct soc_intel_skylake_config *config = dev->chip_info; + int bus = i2c_dev_to_bus(dev); + + if (!config || bus < 0) + return; + + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +static struct i2c_bus_operations i2c_bus_ops = { + .dev_to_bus = &i2c_dev_to_bus, +}; + static struct device_operations i2c_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_smbus, .ops_pci = &soc_pci_ops, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 038fe7d..feba302 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -29,6 +29,9 @@ #define UART_DEBUG_BASE_ADDRESS 0xfe034000 #define UART_DEBUG_BASE_SIZE 0x1000 +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 74fd1c5..476e2c6 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -17,6 +17,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <device/pci_def.h> #include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) @@ -147,4 +148,32 @@ #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) +/* Convert I2C bus number to PCI device and function */ +static inline int i2c_bus_to_devfn(unsigned bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_I2C0; + case 1: return PCH_DEVFN_I2C1; + case 2: return PCH_DEVFN_I2C2; + case 3: return PCH_DEVFN_I2C3; + case 4: return PCH_DEVFN_I2C4; + case 5: return PCH_DEVFN_I2C5; + } + return -1; +} + +/* Convert PCI device and function to I2C bus number */ +static inline int i2c_devfn_to_bus(unsigned devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: return 0; + case PCH_DEVFN_I2C1: return 1; + case PCH_DEVFN_I2C2: return 2; + case PCH_DEVFN_I2C3: return 3; + case PCH_DEVFN_I2C4: return 4; + case PCH_DEVFN_I2C5: return 5; + } + return -1; +} + #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 7fab8ce..56bace1 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,6 +19,7 @@ #include <fsp/romstage.h> +void i2c_early_init(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 194091f..6ae8137 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,5 @@ verstage-y += cpu.c +verstage-y += i2c.c verstage-y += pch.c verstage-y += power_state.c verstage-y += report_platform.c @@ -9,6 +10,7 @@ verstage-y += systemagent.c verstage-y += uart.c romstage-y += cpu.c +romstage-y += i2c.c romstage-y += pch.c romstage-y += power_state.c romstage-y += report_platform.c diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c new file mode 100644 index 0000000..64e6924 --- /dev/null +++ b/src/soc/intel/skylake/romstage/i2c.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + pci_devfn_t dev; + unsigned devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +void i2c_early_init(void) +{ + int bus; + + /* Initialize I2C controllers that are enabled in devicetree */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 9c61095..8375ccd 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -64,6 +64,7 @@ void car_soc_post_console_init(void) report_platform_info(); set_max_freq(); pch_early_init(); + i2c_early_init(); } int get_sw_write_protect_state(void)

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New patch to review for coreboot: drivers/i2c/generic: Fix compile failure
by Duncan Laurie 08 Jun '16

08 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15109 -gerrit commit 95d0b0151b56e81cd1b35c6e88987610c93ce9d3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 8 13:49:40 2016 -0700 drivers/i2c/generic: Fix compile failure This variable name was changed in chip.h but not the consumer and it was submitted before it was caught. Change-Id: I7c492b588b2fd854a9eeac36029a46da324a7b1b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/generic/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 1c10b0e..62e2e9a 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -32,7 +32,7 @@ static void i2c_generic_fill_ssdt(struct device *dev) struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, - .speed = config->bus_speed ? : I2C_SPEED_FAST, + .speed = config->speed ? : I2C_SPEED_FAST, .resource = scope, };

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Patch set updated for coreboot: skylake: Support common LPSS I2C driver
by Duncan Laurie 08 Jun '16

08 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15105 -gerrit commit f6daa7cb09e18fd1822e7748883ab6116eb1b697 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 7 16:40:19 2016 -0700 skylake: Support common LPSS I2C driver Support the common Intel LPSS I2C driver for the 6 I2C bus controllers that are present on the Skylake-LP PCH with a 120 mHz clock. The required lpss_i2c_base_address() method is implemented separately for verstage/romstage and ramstage environments. This provides methods to convert to and from "struct device" and the I2C controller bus number for that device. These are used to provide support for the "I2C Bus Operations" that are present in the coreboot devicetree. To support the I2C controller before ramstage an early init function is provided to do minimal initializaiton of the PCI device and assign a temporary base address for use before memory. The final base address is assigned during device enumeration and used during ramstage. Because it is usually not necessary to enable I2C controllers before ramstage a config register for the devicetree is provided to perform early initialization of this controller. In addition the bus speed can be set in the devicetree and that speed will be applied when the device is initialized. If not provided the default speed is set to I2C_SPEED_FAST. This was tested with the google/chell mainboard by reading and writing from the trackpad and codec devices during both verstage and ramstage. Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 5 ++ src/soc/intel/skylake/chip.h | 5 ++ src/soc/intel/skylake/i2c.c | 50 ++++++++++++++ src/soc/intel/skylake/include/soc/iomap.h | 3 + src/soc/intel/skylake/include/soc/pci_devs.h | 29 +++++++++ src/soc/intel/skylake/include/soc/romstage.h | 1 + src/soc/intel/skylake/romstage/Makefile.inc | 2 + src/soc/intel/skylake/romstage/i2c.c | 97 ++++++++++++++++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 1 + 9 files changed, 193 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9278cf1..a134d1c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP @@ -72,6 +73,10 @@ config CPU_ADDR_BITS int default 36 +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + int + default 120 + config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1d3113f..f21bd1b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -20,6 +20,7 @@ #define _SOC_CHIP_H_ #include <arch/acpi_device.h> +#include <device/i2c.h> #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> @@ -39,6 +40,10 @@ enum skylake_i2c_voltage { struct skylake_i2c_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage voltage; + /* Bus speed in Hz, default is I2C_SPEED_FAST (400 kHz) */ + enum i2c_speed speed; + /* Bus should be enabled prior to ramstage with temporary base */ + int early_init; }; struct soc_intel_skylake_config { diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 76e7bf1..64d39cd 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -14,16 +14,66 @@ */ #include <device/device.h> +#include <device/i2c.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/intel/common/lpss_i2c.h> #include <soc/ramstage.h> +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + struct device *dev; + struct resource *res; + + /* bus -> devfn */ + devfn = i2c_bus_to_devfn(bus); + if (devfn >= 0) { + /* devfn -> dev */ + dev = dev_find_slot(0, devfn); + if (dev) { + /* dev -> bar0 */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + return res->base; + } + } + + return (uintptr_t)NULL; +} + +static int i2c_dev_to_bus(struct device *dev) +{ + return i2c_devfn_to_bus(dev->path.pci.devfn); +} + +/* + * The device should already be enabled and out of reset, + * either from early init in coreboot or SiliconInit in FSP. + */ +static void i2c_dev_init(struct device *dev) +{ + struct soc_intel_skylake_config *config = dev->chip_info; + int bus = i2c_dev_to_bus(dev); + + if (!config || bus < 0) + return; + + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +static struct i2c_bus_operations i2c_bus_ops = { + .dev_to_bus = &i2c_dev_to_bus, +}; + static struct device_operations i2c_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_smbus, .ops_pci = &soc_pci_ops, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 038fe7d..feba302 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -29,6 +29,9 @@ #define UART_DEBUG_BASE_ADDRESS 0xfe034000 #define UART_DEBUG_BASE_SIZE 0x1000 +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 74fd1c5..476e2c6 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -17,6 +17,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <device/pci_def.h> #include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) @@ -147,4 +148,32 @@ #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) +/* Convert I2C bus number to PCI device and function */ +static inline int i2c_bus_to_devfn(unsigned bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_I2C0; + case 1: return PCH_DEVFN_I2C1; + case 2: return PCH_DEVFN_I2C2; + case 3: return PCH_DEVFN_I2C3; + case 4: return PCH_DEVFN_I2C4; + case 5: return PCH_DEVFN_I2C5; + } + return -1; +} + +/* Convert PCI device and function to I2C bus number */ +static inline int i2c_devfn_to_bus(unsigned devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: return 0; + case PCH_DEVFN_I2C1: return 1; + case PCH_DEVFN_I2C2: return 2; + case PCH_DEVFN_I2C3: return 3; + case PCH_DEVFN_I2C4: return 4; + case PCH_DEVFN_I2C5: return 5; + } + return -1; +} + #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 7fab8ce..56bace1 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,6 +19,7 @@ #include <fsp/romstage.h> +void i2c_early_init(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 194091f..6ae8137 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,5 @@ verstage-y += cpu.c +verstage-y += i2c.c verstage-y += pch.c verstage-y += power_state.c verstage-y += report_platform.c @@ -9,6 +10,7 @@ verstage-y += systemagent.c verstage-y += uart.c romstage-y += cpu.c +romstage-y += i2c.c romstage-y += pch.c romstage-y += power_state.c romstage-y += report_platform.c diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c new file mode 100644 index 0000000..64e6924 --- /dev/null +++ b/src/soc/intel/skylake/romstage/i2c.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + pci_devfn_t dev; + unsigned devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Look up the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +void i2c_early_init(void) +{ + int bus; + + /* Initialize I2C controllers that are enabled in devicetree */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 9c61095..8375ccd 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -64,6 +64,7 @@ void car_soc_post_console_init(void) report_platform_info(); set_max_freq(); pch_early_init(); + i2c_early_init(); } int get_sw_write_protect_state(void)

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Patch merged into coreboot/master: rockchip: rk3399: Add support i2s
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 96fbc31027b8e208c264d96c04f45799cea3417e Author: Xing Zheng <zhengxing(a)rock-chips.com> Date: Thu May 19 11:39:20 2016 +0800 rockchip: rk3399: Add support i2s This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee(a)samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15034 for details. -gerrit

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Patch merged into coreboot/master: gru: kevin: enable EC SPI interface
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 8f8cf4d3369ef9d4391dc96215832aad1f5fda67 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun May 22 16:25:29 2016 -0700 gru: kevin: enable EC SPI interface This configures and enables SPI interface #5 used for EC communications on Gru/Kevin. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the appropriate depthcharge change it is possible to trigger booting Chrome OS from the SD card by pressing '^U' on Gru keyboard at the right time. Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: b5cc177 Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346632 Reviewed-on: https://review.coreboot.org/15032 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15032 for details. -gerrit

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Patch merged into coreboot/master: gru: kevin: configure board GPIOs
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 9ed93cb5d50f94f9c43db2eb29764cd6302b4bb0 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun May 22 16:09:54 2016 -0700 gru: kevin: configure board GPIOs Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15031 for details. -gerrit

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Patch merged into coreboot/master: veyron: Add exception_init() to romstage
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 221fdd8cce708f192a457f39a703e9a968b2f847 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jun 7 15:44:39 2016 -0700 veyron: Add exception_init() to romstage I'm not even sure how this slipped through... looks like it had never been there in the first place. Anyway, on ARM exceptions should always be reinitialized in all stages to make sure the handlers are still around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one). Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/15099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15099 for details. -gerrit

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coreboot-gerrit June 2016