coreboot-gerrit June 2016

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New patch to review for coreboot: soc/intel/quark: Switch to using C bootblock
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15134 -gerrit commit 7ca875a5766c30929c6944db33cb2f220075de7c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 14:07:05 2016 -0700 soc/intel/quark: Switch to using C bootblock Use the C_ENVIRONMENT_BOOTBLOCK and remove the junk. TEST=Build and run on Galileo Gen2 Change-Id: Ibcdf771bf63dd9c425a2b73b0b6104581158cfaf Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/romstage/Makefile.inc | 6 - src/soc/intel/quark/romstage/cache_as_ram.inc | 252 ------------- src/soc/intel/quark/romstage/esram_init.inc | 516 -------------------------- 4 files changed, 1 insertion(+), 774 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 3066c7b..dc33fec 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select C_ENVIRONMENT_BOOTBLOCK select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MTRRS diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 63836b1..391cda4 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,12 +13,6 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) -else -cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc -cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc -endif - romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc deleted file mode 100644 index a935bdf..0000000 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ /dev/null @@ -1,252 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * Copyright (C) 2015-2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * Replacement for cache_as_ram.inc when using the FSP binary. This code - * locates the FSP binary, initializes the cache as RAM and performs the - * first stage of initialization. Next this code switches the stack from - * the cache to RAM and then disables the cache as RAM. Finally this code - * performs the final stage of initialization. - */ - -#include <rules.h> - - /* - * eax: BIST value - */ - - movl %eax, %edi - -cache_as_ram: - post_code(0x20) - - /* - * edi: BIST value - */ - - /* - * Find the FSP binary in cbfs. - * Make a fake stack that has the return value back to this code. - */ - lea fake_fsp_stack, %esp - jmp find_fsp - -find_fsp_ret: - /* Save the FSP location */ - mov %eax, %ebp - - /* - * Only when a valid FSP binary is found at CONFIG_FSP_LOC is - * the returned FSP_INFO_HEADER structure address above the base - * address of FSP binary specified by the CONFIG_FSP_LOC value. - * All of the error values are in the 0x8xxxxxxx range which are - * below the CONFIG_FSP_LOC value. - */ - cmp $CONFIG_FSP_ESRAM_LOC, %eax - jbe halt1 - - post_code(POST_FSP_TEMP_RAM_INIT) - -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %al - orb $1, %al - movb %al, 0(%ebx) - jmp . -#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ - - /* Calculate entry into FSP */ - mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ - add 0x1c(%ebp), %eax /* add in the offset for FSP */ - - /* - * Pass early init variables on a fake stack (no memory yet) - * as well as the return location - */ - lea CAR_init_stack, %esp - - /* - * BIST value is zero - * eax: TempRamInitApi address - * ebp: FSP_INFO_HEADER address - * edi: BIST value - * esi: Not used - */ - - /* call FSP binary to setup temporary stack */ - jmp *%eax - -CAR_init_done: - addl $4, %esp - - /* - * ebp: FSP_INFO_HEADER address - * ecx: Temp RAM base - * edx: Temp RAM top - * edi: BIST value - */ - - cmp $0, %eax - jne halt2 - -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT) - movl %edx, %esi - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %al - orb $1, %al - movb %al, 0(%ebx) - movl %esi, %edx - jmp . -#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - - /* Set up bootloader stack */ - movl %edx, %esp - - /* - * eax: 0 - * ebp: FSP_INFO_HEADER address - * ecx: Temp RAM base - * edx: Temp RAM top - * edi: BIST value - * esp: Top of stack in temp RAM - */ - - /* Create cache_as_ram_params on stack */ - pushl %edx /* bootloader CAR end */ - pushl %ecx /* bootloader CAR begin */ - pushl %ebp /* FSP_INFO_HEADER */ - pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */ - /* TODO: Locate 64-bits of storage for initial TSC value */ - pushl $0 /* tsc[63:32] */ - pushl $0 /* tsc[31:0] */ - pushl %esp /* pointer to cache_as_ram_params */ - - /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx - - /* Coreboot assumes stack/heap region will be zero */ - cld - movl %ecx, %edi - neg %ecx - /* Only clear up to current stack value. */ - add %esp, %ecx - shrl $2, %ecx - xorl %eax, %eax - rep stosl - -before_romstage: - post_code(0x2A) - - /* Call cache_as_ram_main(struct cache_as_ram_params *) */ - call cache_as_ram_main - -/* One will never return from cache_as_ram_main() in verstage so there's - * no such thing as after ram init. */ -#if !ENV_VERSTAGE -#include "src/drivers/intel/fsp1_1/after_raminit.S" -#endif - - movb $0x69, %ah - jmp .Lhlt - -halt1: - /* - * Failures for postcode 0xBA - failed in fsp_fih_early_find() - * - * Values are: - * 0x01 - FV signature, "_FVH" not present - * 0x02 - FFS GUID not present - * 0x03 - FSP INFO Header not found - * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to - * a different location, or does it need to be? - * 0x05 - FSP INFO Header signature "FSPH" not found - * 0x06 - FSP Image ID is not the expected ID. - */ - movb $0xBA, %ah - jmp .Lhlt - -halt2: - /* - * Failures for postcode 0xBB - failed in the FSP: - * - * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. - * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. - * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. - * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked - */ - movb $0xBB, %ah - jmp .Lhlt - -#---------------------------------------------------------------------------- -# -# Procedure: .Lhlt -# -# Input: ah - Upper 8-bits of POST code -# al - Lower 8-bits of POST code -# -# Description: -# Infinite loop displaying alternating POST code values -# -#---------------------------------------------------------------------------- - -#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ -#define POST_DELAY 0x50 - -.Lhlt: - xchg %al, %ah - mov $POST_DELAY, %dh -#if IS_ENABLED(CONFIG_POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif -.flash_setup: - movl $FLASH_DELAY, %ecx -.flash_delay: - outb %al, $0xED - loop .flash_delay -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP) - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %dl - xorb $1, %dl - movb %dl, 0(%ebx) -#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */ - decb %dh - jnz .flash_setup - jmp .Lhlt - -/* - * esp is set to this location so that the call into and return from the FSP - * in find_fsp will work. - */ - .align 4 -fake_fsp_stack: - .long find_fsp_ret - .long CONFIG_FSP_ESRAM_LOC /* FSP base address */ - -CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ - .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ - .long CONFIG_ROM_SIZE /* Total Firmware Length */ - -CAR_init_stack: - .long CAR_init_done - .long CAR_init_params diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc deleted file mode 100644 index b899741..0000000 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ /dev/null @@ -1,516 +0,0 @@ -/** @file - * - * Copyright (C) 2015-2016, Intel Corporation - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * * Neither the name of Intel Corporation nor the names of its contributors may - * be used to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * -**/ - -#include <cpu/x86/cr.h> -#include <soc/QuarkNcSocId.h> - -.macro RET32 - jmp *%esp -.endm - -/* ROM/SPI/MEMORY Definitions */ -.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */ -.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */ -.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ - + QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */ -.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */ -.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */ -.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ - + QUARK_ESRAM_MEM_SIZE_BYTES \ - - QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */ -.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */ -.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ - + QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */ - -/* RTC/CMOS definitions */ -.equ RTC_INDEX, (0x70) -.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */ -.equ RTC_DATA, (0x71) - -/* PCI Configuration definitions (Datasheet 5.5.1) */ -.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */ -.equ PCI_ADDRESS_PORT, (0xCF8) -.equ PCI_DATA_PORT, (0xCFC) - -/* Quark PCI devices */ -.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */ -.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */ - -/* ILB PCI Config Registers */ -.equ BDE, (0x0D4) /* BIOS Decode Enable register */ -.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */ - -/* iLB Reset Register */ -.equ ILB_RESET_REG, (0x0CF9) -.equ CF9_WARM_RESET, (0x02) -.equ CF9_COLD_RESET, (0x08) - -/* Memory Arbiter Config Registers */ -.equ AEC_CTRL_OFFSET, (0x00) - -/* Host Bridge Config Registers */ -.equ HMBOUND_OFFSET, (0x08) -.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ - + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) -.equ HECREG_OFFSET, (0x09) -.equ EC_BASE, (0xE0000000) -.equ EC_ENABLE, (0x01) - -/* Memory Manager Config Registers */ -.equ ESRAM_ADDRESS_2G, (0x10000080) -.equ BIMRVCTL_OFFSET, (0x19) -.equ ENABLE_IMR_INTERRUPT, (0x80000000) - -/* SOC UNIT Debug Registers */ -.equ CFGSTICKY_W1_OFFSET, (0x50) -.equ FORCE_COLD_RESET, (0x00000001) -.equ CFGSTICKY_RW_OFFSET, (0x51) -.equ RESET_FOR_ESRAM_LOCK, (0x00000020) -.equ RESET_FOR_HMBOUND_LOCK, (0x00000040) -.equ CFGNONSTICKY_W1_OFFSET, (0x52) -.equ FORCE_WARM_RESET, (0x00000001) - -verify_bist: - cmp $0, %eax - je setup_esram - mov $POST_DEAD_CODE, %eax -#if IS_ENABLED(CONFIG_POST_IO) - outb %al, $CONFIG_POST_IO_PORT -#else - post_code(POST_DEAD_CODE) -#endif - jmp . - -setup_esram: - /* Ensure cache is disabled. */ - movl %cr0, %eax - orl $(CR0_CD | CR0_NW), %eax - invd - movl %eax, %cr0 - - /* - * Disable NMI operation - * Good convention suggests you should read back RTC data port after - * accessing the RTC index port. - */ - movb $(NMI_DISABLE), %al - movw $(RTC_INDEX), %dx - outb %al, %dx - movw $(RTC_DATA), %dx - inb %dx, %al - - /* Disable SMI (Disables SMI wire, not SMI messages) */ - movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx - leal L1, %esp - jmp stackless_SideBand_Read -L1: - andl $(~SMI_EN), %eax - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx - leal L2, %esp - jmp stackless_SideBand_Write -L2: - - /* - * Before we get going, check SOC Unit Registers to see if we are - * required to issue a warm/cold reset - */ - movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L3, %esp - jmp stackless_SideBand_Read -L3: - andl $(FORCE_WARM_RESET), %eax - jz TestForceColdReset /* No warm reset - branch */ - jmp IssueWarmReset - -TestForceColdReset: - movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L4, %esp - jmp stackless_SideBand_Read -L4: - andl $(FORCE_COLD_RESET), %eax - jz TestHmboundLock /* No cold reset - branch */ - jmp IssueColdReset - - /* Before setting HMBOUND, check it's not locked */ -TestHmboundLock: - movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L5, %esp - jmp stackless_SideBand_Read -L5: - andl $(HMBOUND_LOCK), %eax - jz ConfigHmbound /* Good configuration - branch */ - - /* Failed to config - store sticky bit debug */ - movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L6, %esp - jmp stackless_SideBand_Read -L6: - orl $(RESET_FOR_HMBOUND_LOCK), %eax - movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L7, %esp - jmp stackless_SideBand_Write -L7: - jmp IssueWarmReset - - /* Set up the HMBOUND register */ -ConfigHmbound: - movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */ - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L8, %esp - jmp stackless_SideBand_Write -L8: - - /* - * Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND - * violation occurs. - */ - movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */ - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L9, %esp - jmp stackless_SideBand_Write -L9: - - /* Move eSRAM memory to 2GB */ - movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */ - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \ - << QNC_MCR_REG_OFFSET)), %ecx - leal L10, %esp - jmp stackless_SideBand_Write -L10: - - /* Check that we're not blocked from setting the config that we want. */ - movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \ - << QNC_MCR_REG_OFFSET)), %ecx - leal L11, %esp - jmp stackless_SideBand_Read -L11: - andl $(BLOCK_ENABLE_PG), %eax - jnz ConfigPci /* Good configuration - branch */ - - /* Failed to config - store sticky bit debug */ - movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L12, %esp - jmp stackless_SideBand_Read -L12: - orl $(RESET_FOR_ESRAM_LOCK), %eax - movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L13, %esp - jmp stackless_SideBand_Write -L13: - jmp IssueWarmReset - - /* Enable PCIEXBAR */ -ConfigPci: - movl $(EC_BASE + EC_ENABLE), %eax /* Data */ - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L14, %esp - jmp stackless_SideBand_Write -L14: - - movl $(EC_BASE + EC_ENABLE), %eax /* Data */ - movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ - | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ - | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx - leal L15, %esp - jmp stackless_SideBand_Write -L15: - - /* Open up full 8MB SPI decode */ - movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */ - movl $(DECODE_ALL_REGIONS_ENABLE), %eax - leal L16, %esp - jmp stackless_PCIConfig_Write -L16: - - jmp esram_init_done - -IssueWarmReset: - /* Issue Warm Reset request to Remote Management Unit via iLB */ - movw $(CF9_WARM_RESET), %ax - movw $(ILB_RESET_REG), %dx - outw %ax, %dx - jmp . /* Stay here until we are reset. */ - -IssueColdReset: - /* Issue Cold Reset request to Remote Management Unit via iLB */ - movw $(CF9_COLD_RESET), %ax - movw $(ILB_RESET_REG), %dx - outw %ax, %dx - jmp . /* Stay here until we are reset. */ - -/* - *---------------------------------------------------------------------------- - * - * Procedure: stackless_SideBand_Read - * - * Input: esp - return address - * ecx[15:8] - Register offset - * ecx[23:16] - Port ID - * ecx[31:24] - Opcode - * - * Output: eax - Data read - * - * Destroys: eax - * ebx - * cl - * esi - * - * Description: - * Perform requested sideband read - *---------------------------------------------------------------------------- - */ - -stackless_SideBand_Read: - - movl %esp, %esi /* Save the return address */ - - /* Load the SideBand Packet Register to generate the transaction */ - movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx - movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */ - xchgl %ecx, %eax - leal L17, %esp - jmp stackless_PCIConfig_Write -L17: - xchgl %ecx, %eax - - /* Read the SideBand Data Register */ - movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx - leal L18, %esp - jmp stackless_PCIConfig_Read -L18: - - movl %esi, %esp /* Restore the return address */ - RET32 - -/* - *---------------------------------------------------------------------------- - * - * Procedure: stackless_SideBand_Write - * - * Input: esp - return address - * eax - Data - * ecx[15:8] - Register offset - * ecx[23:16] - Port ID - * ecx[31:24] - Opcode - * - * Output: None - * - * Destroys: ebx - * cl - * esi - * - * Description: - * Perform requested sideband write - * - *---------------------------------------------------------------------------- - */ - -stackless_SideBand_Write: - - movl %esp, %esi /* Save the return address */ - - /* Load the SideBand Data Register with the data */ - movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx - leal L19, %esp - jmp stackless_PCIConfig_Write -L19: - - /* Load the SideBand Packet Register to generate the transaction */ - movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx - movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */ - xchgl %ecx, %eax - leal L20, %esp - jmp stackless_PCIConfig_Write -L20: - xchgl %ecx, %eax - - movl %esi, %esp /* Restore the return address */ - RET32 - -/* - *---------------------------------------------------------------------------- - * - * Procedure: stackless_PCIConfig_Write - * - * Input: esp - return address - * eax - Data to write - * ebx - PCI Config Address - * - * Output: None - * - * Destroys: dx - * - * Description: - * Perform a DWORD PCI Configuration write - * - *---------------------------------------------------------------------------- - */ - -stackless_PCIConfig_Write: - - /* Write the PCI Config Address to the address port */ - xchgl %ebx, %eax - movw $(PCI_ADDRESS_PORT), %dx - outl %eax, %dx - xchgl %ebx, %eax - - /* Write the PCI DWORD Data to the data port */ - movw $(PCI_DATA_PORT), %dx - outl %eax, %dx - - RET32 - -/* - *---------------------------------------------------------------------------- - * - * Procedure: stackless_PCIConfig_Read - * - * Input: esp - return address - * ebx - PCI Config Address - * - * Output: eax - Data read - * - * Destroys: eax - * dx - * - * Description: - * Perform a DWORD PCI Configuration read - * - *---------------------------------------------------------------------------- - */ - -stackless_PCIConfig_Read: - - /* Write the PCI Config Address to the address port */ - xchgl %ebx, %eax - movw $(PCI_ADDRESS_PORT), %dx - outl %eax, %dx - xchgl %ebx, %eax - - /* Read the PCI DWORD Data from the data port */ - movw $(PCI_DATA_PORT), %dx - inl %dx, %eax - - RET32 - -/*----------------------------------------------------------------------------*/ - -esram_init_done: - -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) - - /* Copy FSP image to eSRAM and call it. */ - /* TODO: FSP location/size could be got in a routine. */ - cld - movl $(0x00040000), %ecx /* 256K DWORDs = 64K */ - shrl $2, %ecx - movl $CONFIG_FSP_LOC, %esi /* The source address. */ - movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */ - rep movsl -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ - -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) -sd_led: - -.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */ -.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */ -.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */ -.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) /* Base address in PCI config space */ -.equ SD_BASE_ADDR, (0xA0018000) /* SD controller's base address */ -.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) /* HOST_CTRL register */ - - /* Set the SDIO controller's base address */ - movl $(SD_BASE_ADDR), %eax - movl $(SD_CFG_ADDR), %ebx - leal L40, %esp - jmp stackless_PCIConfig_Write - -L40: - movl $(SD_CFG_ADDR), %ebx - leal L41, %esp - jmp stackless_PCIConfig_Read - -L41: - /* Enable the SDIO controller */ - movl $(SD_CFG_CMD), %ebx - leal L42, %esp - jmp stackless_PCIConfig_Read - -L42: - orl $2, %eax - movl $(SD_CFG_CMD), %ebx - leal L43, %esp - jmp stackless_PCIConfig_Write - -L43: - movl $(SD_CFG_CMD), %ebx - leal L44, %esp - jmp stackless_PCIConfig_Read - -L44: -#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) - /* Turn on SD LED to indicate ESRAM successfully initialized */ - movl $SD_HOST_CTRL, %ebx - movb 0(%ebx), %al - orb $1, %al - movb %al, 0(%ebx) - - /* Loop forever */ - jmp . -#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ -#endif /* CONFIG_ENABLE_DEBUG_LED */

1 0

New patch to review for coreboot: mainboard/intel/galileo: Support bootblock in C
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15133 -gerrit commit 4b745f6564bb61023fb02813fbcdfc446949c923 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 14:01:05 2016 -0700 mainboard/intel/galileo: Support bootblock in C Initialize the GPIOs during the boot block to properly route the SOC UART pins. TEST=Build and run on Galileo Gen2 Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/mainboard/intel/galileo/Makefile.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 83fb0db..cbcbf81 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -17,6 +17,11 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark endif +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += gpio.c +bootblock-y += reg_access.c +endif + romstage-y += gpio.c romstage-y += reg_access.c

1 0

New patch to review for coreboot: soc/intel/quark: Add C bootblock
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15132 -gerrit commit f0077d39bed88fe891bc0a38a08061bc2635dcd4 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 18:48:31 2016 -0700 soc/intel/quark: Add C bootblock Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 25 + src/soc/intel/quark/Makefile.inc | 7 + src/soc/intel/quark/bootblock/bootblock.c | 77 +++ .../intel/quark/bootblock/bootblock_save_bist.inc | 23 + .../quark/bootblock/bootblock_save_timestamp.inc | 36 ++ src/soc/intel/quark/bootblock/esram_init.S | 522 +++++++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 1 + src/soc/intel/quark/romstage/Makefile.inc | 3 + src/soc/intel/quark/romstage/bootblock_in_c.S | 75 +++ src/soc/intel/quark/romstage/romstage.c | 27 ++ 10 files changed, 796 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2c7ec64..3066c7b 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -261,4 +261,29 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +##### +# Bootblock +# The following options support the C_ENVIRONMENT_BOOTBLOCK. +##### + +config BOOTBLOCK_SAVE_BIST + string + default src/soc/intel/quark/bootblock/bootblock_save_bist.inc + +config BOOTBLOCK_SAVE_TIMESTAMP + string + default src/soc/intel/quark/bootblock/bootblock_save_timestamp.inc + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + +config ROMSTAGE_AFTER_CAR_STAGE_ENTRY + string + default "src/soc/intel/quark/romstage/bootblock_in_c.S + endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index d747079..b336fc7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -18,6 +18,13 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += bootblock/esram_init.S +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += bootblock/bootblock.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += i2c.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += reg_access.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += tsc_freq.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += uart_common.c + romstage-y += i2c.c romstage-y += memmap.c romstage-y += reg_access.c diff --git a/src/soc/intel/quark/bootblock/bootblock.c b/src/soc/intel/quark/bootblock/bootblock.c new file mode 100644 index 0000000..669cd47 --- /dev/null +++ b/src/soc/intel/quark/bootblock/bootblock.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <program_loading.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/reg_access.h> + +static const struct reg_script clear_smi_and_wake_events[] = { + /* Clear any SMI or wake events */ + REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S), + REG_GPE0_READ(R_QNC_GPE0BLK_SMIS), + REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL), + REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL), + REG_SCRIPT_END +}; + +static const struct reg_script legacy_gpio_init[] = { + /* Temporarily enable the legacy GPIO controller */ + REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID + | LEGACY_GPIO_BASE_ADDRESS), + /* Temporarily enable the GPE controller */ + REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID + | GPE0_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO), + REG_SCRIPT_END +}; + +static const struct reg_script i2c_gpio_controller_init[] = { + /* Temporarily enable the GPIO controller */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS), + REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +static const struct reg_script hsuart_init[] = { + /* Enable the HSUART */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS), + REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), + REG_SCRIPT_END +}; + +void bootblock_soc_early_init(void) +{ + /* Initialize the controllers */ + reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init); + reg_script_run_on_dev(LPC_BDF, legacy_gpio_init); + + /* Enable the HSUART */ + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) + reg_script_run_on_dev(HSUART0_BDF, hsuart_init); + if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1)) + reg_script_run_on_dev(HSUART1_BDF, hsuart_init); +} + +void platform_prog_run(struct prog *prog) +{ + /* Display the program entry point */ + printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name, + prog->entry, prog->arg); +} diff --git a/src/soc/intel/quark/bootblock/bootblock_save_bist.inc b/src/soc/intel/quark/bootblock/bootblock_save_bist.inc new file mode 100644 index 0000000..dc79028 --- /dev/null +++ b/src/soc/intel/quark/bootblock/bootblock_save_bist.inc @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Default BIST save routine. + */ + +.global save_bist + + /* No value to save since Quark does not generate a BIST value */ + +save_bist: diff --git a/src/soc/intel/quark/bootblock/bootblock_save_timestamp.inc b/src/soc/intel/quark/bootblock/bootblock_save_timestamp.inc new file mode 100644 index 0000000..7e9cde9 --- /dev/null +++ b/src/soc/intel/quark/bootblock/bootblock_save_timestamp.inc @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016, Intel Corporation + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Default timestamp save routine. + */ + +.global save_timestamp + + /* Get an early timestamp */ + rdtsc + + /* Save the timestamp value: + * eax: Low 32-bits of timestamp + * edx: High 32-bits of timestamp + */ + +save_timestamp: + movl %eax, %ebp + movl %edx, %edi + + /* Registers: + * ebp: Low 32-bits of timestamp + * edi: High 32-bits of timestamp + */ diff --git a/src/soc/intel/quark/bootblock/esram_init.S b/src/soc/intel/quark/bootblock/esram_init.S new file mode 100644 index 0000000..42ec9c0 --- /dev/null +++ b/src/soc/intel/quark/bootblock/esram_init.S @@ -0,0 +1,522 @@ +/** @file + * + * Copyright (C) 2015-2016, Intel Corporation + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * * Neither the name of Intel Corporation nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * +**/ + +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/QuarkNcSocId.h> + +.macro RET32 + jmp *%esp +.endm + +/* ROM/SPI/MEMORY Definitions */ +.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */ +.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */ +.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */ +.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */ +.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */ +.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_ESRAM_MEM_SIZE_BYTES \ + - QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */ +.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */ +.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \ + + QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */ + +/* RTC/CMOS definitions */ +.equ RTC_INDEX, (0x70) +.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */ +.equ RTC_DATA, (0x71) + +/* PCI Configuration definitions (Datasheet 5.5.1) */ +.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */ +.equ PCI_ADDRESS_PORT, (0xCF8) +.equ PCI_DATA_PORT, (0xCFC) + +/* Quark PCI devices */ +.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */ +.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */ + +/* ILB PCI Config Registers */ +.equ BDE, (0x0D4) /* BIOS Decode Enable register */ +.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */ + +/* iLB Reset Register */ +.equ ILB_RESET_REG, (0x0CF9) +.equ CF9_WARM_RESET, (0x02) +.equ CF9_COLD_RESET, (0x08) + +/* Memory Arbiter Config Registers */ +.equ AEC_CTRL_OFFSET, (0x00) + +/* Host Bridge Config Registers */ +.equ HMBOUND_OFFSET, (0x08) +.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \ + + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES) +.equ HECREG_OFFSET, (0x09) +.equ EC_BASE, (0xE0000000) +.equ EC_ENABLE, (0x01) + +/* Memory Manager Config Registers */ +.equ ESRAM_ADDRESS_2G, (0x10000080) +.equ BIMRVCTL_OFFSET, (0x19) +.equ ENABLE_IMR_INTERRUPT, (0x80000000) + +/* SOC UNIT Debug Registers */ +.equ CFGSTICKY_W1_OFFSET, (0x50) +.equ FORCE_COLD_RESET, (0x00000001) +.equ CFGSTICKY_RW_OFFSET, (0x51) +.equ RESET_FOR_ESRAM_LOCK, (0x00000020) +.equ RESET_FOR_HMBOUND_LOCK, (0x00000040) +.equ CFGNONSTICKY_W1_OFFSET, (0x52) +.equ FORCE_WARM_RESET, (0x00000001) + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + + /* Registers: + * ebp: Low 32-bits of timestamp + * edi: High 32-bits of timestamp + */ + +setup_esram: + /* Ensure cache is disabled. */ + movl %cr0, %eax + orl $(CR0_CD | CR0_NW), %eax + invd + movl %eax, %cr0 + + /* + * Disable NMI operation + * Good convention suggests you should read back RTC data port after + * accessing the RTC index port. + */ + movb $(NMI_DISABLE), %al + movw $(RTC_INDEX), %dx + outb %al, %dx + movw $(RTC_DATA), %dx + inb %dx, %al + + /* Disable SMI (Disables SMI wire, not SMI messages) */ + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L1, %esp + jmp stackless_SideBand_Read +L1: + andl $(~SMI_EN), %eax + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx + leal L2, %esp + jmp stackless_SideBand_Write +L2: + + /* + * Before we get going, check SOC Unit Registers to see if we are + * required to issue a warm/cold reset + */ + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L3, %esp + jmp stackless_SideBand_Read +L3: + andl $(FORCE_WARM_RESET), %eax + jz TestForceColdReset /* No warm reset - branch */ + jmp IssueWarmReset + +TestForceColdReset: + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L4, %esp + jmp stackless_SideBand_Read +L4: + andl $(FORCE_COLD_RESET), %eax + jz TestHmboundLock /* No cold reset - branch */ + jmp IssueColdReset + + /* Before setting HMBOUND, check it's not locked */ +TestHmboundLock: + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L5, %esp + jmp stackless_SideBand_Read +L5: + andl $(HMBOUND_LOCK), %eax + jz ConfigHmbound /* Good configuration - branch */ + + /* Failed to config - store sticky bit debug */ + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L6, %esp + jmp stackless_SideBand_Read +L6: + orl $(RESET_FOR_HMBOUND_LOCK), %eax + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L7, %esp + jmp stackless_SideBand_Write +L7: + jmp IssueWarmReset + + /* Set up the HMBOUND register */ +ConfigHmbound: + movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */ + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L8, %esp + jmp stackless_SideBand_Write +L8: + + /* + * Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND + * violation occurs. + */ + movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */ + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L9, %esp + jmp stackless_SideBand_Write +L9: + + /* Move eSRAM memory to 2GB */ + movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */ + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \ + << QNC_MCR_REG_OFFSET)), %ecx + leal L10, %esp + jmp stackless_SideBand_Write +L10: + + /* Check that we're not blocked from setting the config that we want. */ + movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \ + << QNC_MCR_REG_OFFSET)), %ecx + leal L11, %esp + jmp stackless_SideBand_Read +L11: + andl $(BLOCK_ENABLE_PG), %eax + jnz ConfigPci /* Good configuration - branch */ + + /* Failed to config - store sticky bit debug */ + movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L12, %esp + jmp stackless_SideBand_Read +L12: + orl $(RESET_FOR_ESRAM_LOCK), %eax + movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L13, %esp + jmp stackless_SideBand_Write +L13: + jmp IssueWarmReset + + /* Enable PCIEXBAR */ +ConfigPci: + movl $(EC_BASE + EC_ENABLE), %eax /* Data */ + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L14, %esp + jmp stackless_SideBand_Write +L14: + + movl $(EC_BASE + EC_ENABLE), %eax /* Data */ + movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \ + | (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \ + | (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx + leal L15, %esp + jmp stackless_SideBand_Write +L15: + + /* Open up full 8MB SPI decode */ + movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */ + movl $(DECODE_ALL_REGIONS_ENABLE), %eax + leal L16, %esp + jmp stackless_PCIConfig_Write +L16: + + jmp esram_init_done + +IssueWarmReset: + /* Issue Warm Reset request to Remote Management Unit via iLB */ + movw $(CF9_WARM_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . /* Stay here until we are reset. */ + +IssueColdReset: + /* Issue Cold Reset request to Remote Management Unit via iLB */ + movw $(CF9_COLD_RESET), %ax + movw $(ILB_RESET_REG), %dx + outw %ax, %dx + jmp . /* Stay here until we are reset. */ + +/* + *---------------------------------------------------------------------------- + * + * Procedure: stackless_SideBand_Read + * + * Input: esp - return address + * ecx[15:8] - Register offset + * ecx[23:16] - Port ID + * ecx[31:24] - Opcode + * + * Output: eax - Data read + * + * Destroys: eax + * ebx + * cl + * esi + * + * Description: + * Perform requested sideband read + *---------------------------------------------------------------------------- + */ + +stackless_SideBand_Read: + + movl %esp, %esi /* Save the return address */ + + /* Load the SideBand Packet Register to generate the transaction */ + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */ + xchgl %ecx, %eax + leal L17, %esp + jmp stackless_PCIConfig_Write +L17: + xchgl %ecx, %eax + + /* Read the SideBand Data Register */ + movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx + leal L18, %esp + jmp stackless_PCIConfig_Read +L18: + + movl %esi, %esp /* Restore the return address */ + RET32 + +/* + *---------------------------------------------------------------------------- + * + * Procedure: stackless_SideBand_Write + * + * Input: esp - return address + * eax - Data + * ecx[15:8] - Register offset + * ecx[23:16] - Port ID + * ecx[31:24] - Opcode + * + * Output: None + * + * Destroys: ebx + * cl + * esi + * + * Description: + * Perform requested sideband write + * + *---------------------------------------------------------------------------- + */ + +stackless_SideBand_Write: + + movl %esp, %esi /* Save the return address */ + + /* Load the SideBand Data Register with the data */ + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx + leal L19, %esp + jmp stackless_PCIConfig_Write +L19: + + /* Load the SideBand Packet Register to generate the transaction */ + movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx + movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */ + xchgl %ecx, %eax + leal L20, %esp + jmp stackless_PCIConfig_Write +L20: + xchgl %ecx, %eax + + movl %esi, %esp /* Restore the return address */ + RET32 + +/* + *---------------------------------------------------------------------------- + * + * Procedure: stackless_PCIConfig_Write + * + * Input: esp - return address + * eax - Data to write + * ebx - PCI Config Address + * + * Output: None + * + * Destroys: dx + * + * Description: + * Perform a DWORD PCI Configuration write + * + *---------------------------------------------------------------------------- + */ + +stackless_PCIConfig_Write: + + /* Write the PCI Config Address to the address port */ + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + /* Write the PCI DWORD Data to the data port */ + movw $(PCI_DATA_PORT), %dx + outl %eax, %dx + + RET32 + +/* + *---------------------------------------------------------------------------- + * + * Procedure: stackless_PCIConfig_Read + * + * Input: esp - return address + * ebx - PCI Config Address + * + * Output: eax - Data read + * + * Destroys: eax + * dx + * + * Description: + * Perform a DWORD PCI Configuration read + * + *---------------------------------------------------------------------------- + */ + +stackless_PCIConfig_Read: + + /* Write the PCI Config Address to the address port */ + xchgl %ebx, %eax + movw $(PCI_ADDRESS_PORT), %dx + outl %eax, %dx + xchgl %ebx, %eax + + /* Read the PCI DWORD Data from the data port */ + movw $(PCI_DATA_PORT), %dx + inl %dx, %eax + + RET32 + +/*----------------------------------------------------------------------------*/ + +esram_init_done: + +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) +sd_led: + +.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */ +.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */ +.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */ +.equ SD_CFG_ADDR, (SD_CFG_BASE+0x10) /* Base address in PCI config space */ +.equ SD_BASE_ADDR, (0xA0018000) /* SD controller's base address */ +.equ SD_HOST_CTRL, (SD_BASE_ADDR+0x28) /* HOST_CTRL register */ + + /* Set the SDIO controller's base address */ + movl $(SD_BASE_ADDR), %eax + movl $(SD_CFG_ADDR), %ebx + leal L40, %esp + jmp stackless_PCIConfig_Write + +L40: + movl $(SD_CFG_ADDR), %ebx + leal L41, %esp + jmp stackless_PCIConfig_Read + +L41: + /* Enable the SDIO controller */ + movl $(SD_CFG_CMD), %ebx + leal L42, %esp + jmp stackless_PCIConfig_Read + +L42: + orl $2, %eax + movl $(SD_CFG_CMD), %ebx + leal L43, %esp + jmp stackless_PCIConfig_Write + +L43: + movl $(SD_CFG_CMD), %ebx + leal L44, %esp + jmp stackless_PCIConfig_Read + +L44: +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM) + /* Turn on SD LED to indicate ESRAM successfully initialized */ + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %al + orb $1, %al + movb %al, 0(%ebx) + + /* Loop forever */ + jmp . +#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */ +#endif /* CONFIG_ENABLE_DEBUG_LED */ + + /* Registers: + * ebp: Low 32-bits of timestamp + * edi: High 32-bits of timestamp + */ + + /* Setup bootblock stack */ + movl $_car_stack_end, %esp + +before_carstage: + post_code(0x2b) + + /* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */ + push %ebp + push %edi + + /* We can call into C functions now */ + call bootblock_main_with_timestamp + + /* Never reached */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 3a9e7a8..47545ac 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -25,6 +25,7 @@ #include <fsp/romstage.h> #include <soc/reg_access.h> +asmlinkage void *car_state_c_entry(void); uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 6c92ac4..63836b1 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,8 +13,11 @@ # GNU General Public License for more details. # +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +else cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +endif romstage-y += mtrr.c romstage-y += pcie.c diff --git a/src/soc/intel/quark/romstage/bootblock_in_c.S b/src/soc/intel/quark/romstage/bootblock_in_c.S new file mode 100644 index 0000000..35b0639 --- /dev/null +++ b/src/soc/intel/quark/romstage/bootblock_in_c.S @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Replacement for cache_as_ram.inc when using the C environment boot block. + */ + +#include <rules.h> + + .global car_stage_entry + +car_stage_entry: + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call car_state_c_entry + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt + +#---------------------------------------------------------------------------- +# +# Procedure: .Lhlt +# +# Input: ah - Upper 8-bits of POST code +# al - Lower 8-bits of POST code +# +# Description: +# Infinite loop displaying alternating POST code values +# +#---------------------------------------------------------------------------- + +#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ +#define POST_DELAY 0x50 + +.Lhlt: + xchg %al, %ah + mov $POST_DELAY, %dh +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT +#else + post_code(POST_DEAD_CODE) +#endif +.flash_setup: + movl $FLASH_DELAY, %ecx +.flash_delay: + outb %al, $0xED + loop .flash_delay +#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) + movl $SD_HOST_CTRL, %ebx + movb 0(%ebx), %dl + xorb $1, %dl + movb %dl, 0(%ebx) +#endif /* CONFIG_ENABLE_DEBUG_LED */ + decb %dh + jnz .flash_setup + jmp .Lhlt diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index e27aa68..66853de 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -29,6 +29,7 @@ #include <soc/pm.h> #include <soc/romstage.h> #include <soc/reg_access.h> +#include <string.h> static const struct reg_script clear_smi_and_wake_events[] = { /* Clear any SMI or wake events */ @@ -65,6 +66,32 @@ static const struct reg_script hsuart_init[] = { REG_SCRIPT_END }; +asmlinkage void *car_state_c_entry(void) +{ + post_code(0x20); + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { + FSP_INFO_HEADER *fih; + struct cache_as_ram_params car_params; + void *top_of_stack; + + memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC, + 0x00040000); + + fih = find_fsp(CONFIG_FSP_ESRAM_LOC); + + car_params.tsc = 0; + car_params.bist = 0; + car_params.fih = fih; + car_params.bootloader_car_start = 0; + car_params.bootloader_car_end = 0; + post_code(0x2A); + top_of_stack = cache_as_ram_main(&car_params); + return top_of_stack; + } + + return NULL; +} + void car_soc_pre_console_init(void) { /* Initialize the controllers */

1 0

New patch to review for coreboot: lib: Build reg_script for bootblock
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15131 -gerrit commit f623cac38c633987bf64a0208b77cba1c67ff60f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 18:49:55 2016 -0700 lib: Build reg_script for bootblock Allow reg_script to be used during the bootblock. TEST=Build and run on Galileo Gen2 Change-Id: I55fe0be3f50116927b801ce67a3f23bb1931f6e7 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/lib/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index b446e10..49720a7 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -146,6 +146,7 @@ bootblock-y += hexdump.c ramstage-y += hexdump.c romstage-y += hexdump.c +bootblock-$(CONFIG_REG_SCRIPT) += reg_script.c verstage-$(CONFIG_REG_SCRIPT) += reg_script.c romstage-$(CONFIG_REG_SCRIPT) += reg_script.c ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c

1 0

New patch to review for coreboot: util/checklist: Add bootblock support
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15130 -gerrit commit 89c13146a85b692ad713489356c9b1b6cbb12dc1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 18:45:22 2016 -0700 util/checklist: Add bootblock support Scan the boot block when building it with C_ENVIRONMENT_BOOTBLOCK selected. TEST=Build and run with Galileo Gen2 Change-Id: I922f761c31e95efde0975d8572c47084b91b2879 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 ++-------------------- .../fsp/fsp1_1/checklist/bootblock_optional.dat | 6 ++ util/checklist/Makefile.inc | 3 + 3 files changed, 14 insertions(+), 72 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat index 8a4325f..4055a3c 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -1,77 +1,10 @@ -arch_segment_loaded -backup_top_of_ram +bootblock_c_entry bootblock_mainboard_early_init bootblock_mainboard_init +bootblock_main_with_timestamp +bootblock_pre_c_entry +bootblock_protected_mode_entry bootblock_soc_early_init bootblock_soc_init -boot_device_init -car_mainboard_post_console_init -car_mainboard_pre_console_init -car_soc_post_console_init -car_soc_pre_console_init -cbfs_master_header_locator -cbmem_fail_resume -clear_recovery_mode_switch -cpu_smi_handler -fill_power_state -fw_cfg_acpi_tables -get_sw_write_protect_state -get_top_of_ram -gpio_acpi_path -init_timer -lb_board -lb_framebuffer -mainboard_add_dimm_info -mainboard_check_ec_image -mainboard_io_trap_handler -mainboard_memory_init_params -mainboard_post -mainboard_romstage_entry -mainboard_save_dimm_info -mainboard_silicon_init_params -mainboard_smi_apmc -mainboard_smi_gpi -mainboard_smi_sleep -mainboard_suspend_resume -map_oprom_vendev -mirror_payload -mrc_cache_get_current -mrc_cache_stash_data -northbridge_smi_handler -nvm_mmio_to_flash_offset -platform_prog_run -platform_segment_loaded -raminit -ramstage_cache_invalid -report_memory_config -save_chromeos_gpios -setup_stack_and_mtrrs -smbios_mainboard_bios_version -smbios_mainboard_manufacturer -smbios_mainboard_product_name -smbios_mainboard_serial_number -smbios_mainboard_set_uuid -smbios_mainboard_version -smm_disable_busmaster -soc_after_ram_init -soc_after_silicon_init -soc_display_memory_init_params -soc_display_silicon_init_params -soc_fill_acpi_wake -soc_memory_init_params -soc_pre_ram_init -soc_silicon_init_params -soc_skip_ucode_update -southbridge_smi_handler -stage_cache_add -stage_cache_load_stage -timestamp_get -timestamp_tick_freq_mhz tsc_freq_mhz -vb2ex_hwcrypto_digest_extend -vb2ex_hwcrypto_digest_finalize -vb2ex_hwcrypto_digest_init -vboot_platform_prepare_reboot -verstage_mainboard_init -wifi_regulatory_domain -write_smp_table +uart_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat new file mode 100644 index 0000000..fc0e872 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_optional.dat @@ -0,0 +1,6 @@ +bootblock_c_entry +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +uart_init diff --git a/util/checklist/Makefile.inc b/util/checklist/Makefile.inc index f8e5ebd..e400725 100644 --- a/util/checklist/Makefile.inc +++ b/util/checklist/Makefile.inc @@ -182,6 +182,9 @@ percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lin # # Determine which HTML files to include into the webpage # +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +html_table_files += $(objcbfs)/bootblock.html +endif ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) html_table_files += $(objcbfs)/verstage.html endif

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New patch to review for coreboot: vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entry
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15129 -gerrit commit 6bcfa0285f91e14c436c9e183462f98de8cbbdc2 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 13:19:05 2016 -0700 vendorcode/intel/fsp1_1/checklist: romstage - Add car_stage_entry Add car_stage_entry as an optional routine in the checklist. TEST=Build and run on Galileo Gen2 Change-Id: I52f6aefc2566beac01373dbebf3a43d35032a0df Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat | 1 + src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat | 1 + 2 files changed, 2 insertions(+) diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat index e6bef6c..267673a 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -1,6 +1,7 @@ arch_segment_loaded backup_top_of_ram boot_device_init +car_stage_entry cbfs_master_header_locator cbmem_fail_resume clear_recovery_mode_switch diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat index 2634566..70f204d 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -1,6 +1,7 @@ arch_segment_loaded backup_top_of_ram boot_device_init +car_stage_entry cbmem_fail_resume clear_recovery_mode_switch cpu_smi_handler

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New patch to review for coreboot: arch/x86: Enable SSE in bootblock_crt0.S
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15128 -gerrit commit 4a59758e54b90e3eee880f3fa87a810b1e015fbe Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 07:11:48 2016 -0700 arch/x86: Enable SSE in bootblock_crt0.S Don't write reserved bits in the Quark platform. Follow the previous boot behavior and just enable SSE. TEST=Build and run on Galileo Gen2 Change-Id: Ib3143eff02b2610b595bd666c10d70e43103ccda Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/bootblock_crt0.S | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 1d66bdc..8ff95af 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -56,14 +56,10 @@ bootblock_protected_mode_entry: #include CONFIG_BOOTBLOCK_SAVE_TIMESTAMP #endif -#if !IS_ENABLED(CONFIG_SSE) +#if IS_ENABLED(CONFIG_SSE) enable_sse: - mov %cr0, %eax - and $~CR0_EM, %ax /* Clear coprocessor emulation CR0.EM */ - or $CR0_MP, %ax /* Set coprocessor monitoring CR0.MP */ - mov %eax, %cr0 mov %cr4, %eax - or $(CR4_OSFXSR | CR4_OSXMMEXCPT), %ax + or $CR4_OSFXSR, %ax mov %eax, %cr4 #endif /* IS_ENABLED(CONFIG_SSE) */

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New patch to review for coreboot: arch/x86: Add debug spinloop
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15127 -gerrit commit 152d830442ff958c0b41f15f950b3d96a5dd1a8c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jun 7 08:45:17 2016 -0700 arch/x86: Add debug spinloop Conditionally add a debug spinloop to enable easy connection of JTAG debuggers. TEST=Build and run on Galileo Gen2 with a JTAG debugger. Change-Id: I7a21f9e6bfb10912d06ce48447c61202553630d0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/bootblock_crt0.S | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index cdeb02d..8be7ac1 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -117,6 +117,13 @@ config PC80_SYSTEM bool default y if ARCH_X86 +config BOOTBLOCK_DEBUG_SPINLOOP + bool + default n + help + Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait + for a JTAG debugger to break into the execution sequence. + config BOOTBLOCK_MAINBOARD_INIT string diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 4e49bce..1d66bdc 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -32,6 +32,15 @@ #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> +#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP) + + /* Wait for a JTAG debugger to break in and set EBX non-zero */ + xor %ebx, %ebx + +debug_spinloop: + cmp $0, %ebx + jz debug_spinloop +#endif bootblock_protected_mode_entry:

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New patch to review for coreboot: arch/x86: Support "weak" BIST and TSC save routines
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15126 -gerrit commit 88fe4193a543aa662c46b19047dc59a453f07840 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 18:41:00 2016 -0700 arch/x86: Support "weak" BIST and TSC save routines Not all x86 architectures support the mm register set. Provide a "weak" routine that saves BIST in mm0 and a "weak" routine that saves the TSC value in mm2:mm1. Use the Kconfig value BOOTBLOCK_SAVE_BIST to specify the "weak" routine to save the BIST value. Use the Kconfig value BOOTBLOCK_SAVE_TIMESTAMP to specify the "weak" routine to get and save the TSC value as the early timestamp. TEST=Build and run on Amenia and Galileo Gen2. Change-Id: I8119e74664ac3522c011767d424d441cd62545ce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/arch/x86/Kconfig | 16 +++++++++++++++ src/arch/x86/bootblock_crt0.S | 19 ++++++++++++------ src/arch/x86/bootblock_save_bist.inc | 27 +++++++++++++++++++++++++ src/arch/x86/bootblock_save_timestamp.inc | 33 +++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 724c4db..cdeb02d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -126,6 +126,22 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config BOOTBLOCK_RESETS string +config BOOTBLOCK_SAVE_BIST + string + default src/arch/x86/bootblock_save_bist.inc + help + Specify the file to use to save the BIST value. The default file + uses register MM0. Another file is necessary when the CPU does not + support the MMx register set. + +config BOOTBLOCK_SAVE_TIMESTAMP + string + default src/arch/x86/bootblock_save_timestamp.inc + help + Specify the file to use to save the timestamp value. The default + file uses registers MM1 and MM2. Another file is necessary when + the CPU does not support the MMx register set. + config HAVE_CMOS_DEFAULT def_bool n diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 7292b8b..4e49bce 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -34,12 +34,18 @@ bootblock_protected_mode_entry: - /* Save BIST result */ - movd %eax, %mm0 - /* Save an early timestamp */ - rdtsc - movd %eax, %mm1 - movd %edx, %mm2 + + /* Save BIST result: + * eax: BIST result + */ +#ifdef CONFIG_BOOTBLOCK_SAVE_BIST +#include CONFIG_BOOTBLOCK_SAVE_BIST +#endif + + /* Save the timestamp value */ +#ifdef CONFIG_BOOTBLOCK_SAVE_TIMESTAMP +#include CONFIG_BOOTBLOCK_SAVE_TIMESTAMP +#endif #if !IS_ENABLED(CONFIG_SSE) enable_sse: @@ -53,4 +59,5 @@ enable_sse: #endif /* IS_ENABLED(CONFIG_SSE) */ /* We're done. Now it's up to platform-specific code */ +jump_to_soc_code: jmp bootblock_pre_c_entry diff --git a/src/arch/x86/bootblock_save_bist.inc b/src/arch/x86/bootblock_save_bist.inc new file mode 100644 index 0000000..6474a8c --- /dev/null +++ b/src/arch/x86/bootblock_save_bist.inc @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2016, Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Default BIST save routine. + */ + +.global save_bist + + /* Save BIST result: + * eax: BIST result + */ + +save_bist: + movd %eax, %mm0 diff --git a/src/arch/x86/bootblock_save_timestamp.inc b/src/arch/x86/bootblock_save_timestamp.inc new file mode 100644 index 0000000..d1cbe8a --- /dev/null +++ b/src/arch/x86/bootblock_save_timestamp.inc @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2016, Intel Corporation + + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Default timestamp save routine. + */ + +.global save_timestamp + + /* Get an early timestamp */ + rdtsc + + /* Save the timestamp value: + * eax: Low 32-bits of timestamp + * edx: High 32-bits of timestamp + */ + +save_timestamp: + movd %eax, %mm1 + movd %edx, %mm2 +

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New patch to review for coreboot: lib: Add asmlinkage attribute to bootblock_main_with_timestamp
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15125 -gerrit commit 84e8952d9326c7d809f9ab1ef3636f8a48e2f3fb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 17:20:17 2016 -0700 lib: Add asmlinkage attribute to bootblock_main_with_timestamp Add asmlinkage to bootblock_main_with_timestamp so that it may be called directly from the assembly code. TEST=Build for Amenia and Galileo Gen2 Change-Id: Iefb8e5c1ddce2ec495b9272966b595d5adcebc1c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/bootblock_common.h | 2 +- src/lib/bootblock.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index 8bef60a..9a321b4 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -43,6 +43,6 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp); * This function assumes that the timer has already been initialized, so it * does not call init_timer(). */ -void bootblock_main_with_timestamp(uint64_t base_timestamp); +void asmlinkage bootblock_main_with_timestamp(uint64_t base_timestamp); #endif /* __BOOTBLOCK_COMMON_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index f16cb44..9dece0c 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -29,7 +29,7 @@ __attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ } __attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ } -void bootblock_main_with_timestamp(uint64_t base_timestamp) +void asmlinkage bootblock_main_with_timestamp(uint64_t base_timestamp) { /* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */ if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)

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coreboot-gerrit June 2016