coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: bootblock: Declare common bootblock_pre_c_entry routine
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15124 -gerrit commit 1ea759c64d6f07359fdbd7f5b4712acde34c47e8 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jun 5 16:46:48 2016 -0700 bootblock: Declare common bootblock_pre_c_entry routine Enable uses of a common bootblock_pre_c_entry routine. Pass in TSC value as a uint64_t value. TEST=Build for amenia and Galileo Gen2 Change-Id: I8be2e079ababb2cf1f9b7e6293f93e7c778761a1 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/bootblock_common.h | 7 +++++++ src/soc/intel/apollolake/bootblock/bootblock.c | 8 ++++---- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 4 ++-- src/soc/intel/apollolake/include/soc/bootblock.h | 20 -------------------- 4 files changed, 13 insertions(+), 26 deletions(-) diff --git a/src/include/bootblock_common.h b/src/include/bootblock_common.h index b227cf4..8bef60a 100644 --- a/src/include/bootblock_common.h +++ b/src/include/bootblock_common.h @@ -16,6 +16,7 @@ #ifndef __BOOTBLOCK_COMMON_H #define __BOOTBLOCK_COMMON_H +#include <arch/cpu.h> #include <main_decl.h> #include <stdint.h> @@ -28,6 +29,12 @@ void bootblock_mainboard_early_init(void); void bootblock_mainboard_init(void); void bootblock_soc_early_init(void); void bootblock_soc_init(void); + +/* + * SOC specific C code entry point for the boot block. + */ +void asmlinkage bootblock_c_entry(uint64_t base_timestamp); + /* * This is a the same as the bootblock main(), with the difference that it does * not collect a timestamp. Instead it accepts the first timestamp as an diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 68ce7ab..ca402e9 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -19,7 +19,6 @@ #include <cpu/x86/mtrr.h> #include <device/pci.h> #include <lib.h> -#include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/cpu.h> #include <soc/gpio.h> @@ -54,7 +53,7 @@ static void enable_pm_timer(void) wrmsr(MSR_EMULATE_PM_TMR, msr); } -void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) +void asmlinkage bootblock_c_entry(uint64_t base_timestamp) { device_t dev = NB_DEV_ROOT; @@ -71,7 +70,8 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Decode the ACPI I/O port range for early firmware verification.*/ dev = PMC_DEV; @@ -80,7 +80,7 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) PCI_COMMAND_IO | PCI_COMMAND_MASTER); /* Call lib/bootblock.c main */ - bootblock_main_with_timestamp(((uint64_t)tsc_hi << 32) | tsc_lo); + bootblock_main_with_timestamp(base_timestamp); } static void cache_bios_region(void) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index f19cb71..8647206 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -130,10 +130,10 @@ before_carstage: post_code(0x2b) /* Restore the timestamp from bootblock_crt0.S (mm2:mm1) */ - movd %mm1, %eax - push %eax movd %mm2, %eax push %eax + movd %mm1, %eax + push %eax /* We can call into C functions now */ call bootblock_c_entry diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h deleted file mode 100644 index 9ce9231..0000000 --- a/src/soc/intel/apollolake/include/soc/bootblock.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_BOOTBLOCK_H_ -#define _SOC_APOLLOLAKE_BOOTBLOCK_H_ -#include <arch/cpu.h> - -void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo); -#endif

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Patch set updated for coreboot: mainboard: Support ROM_SIZE > 16 MiB
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15108 -gerrit commit 6c7319d954571847bac9373d94dc9d4f7b202b8b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 12:47:07 2016 -0700 mainboard: Support ROM_SIZE > 16 MiB Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size limitation of 16 MiB by specifying 16 MiB as the ROM size. TEST=Build and run on neoncity Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/arch/x86/smbios.c | 3 ++- src/mainboard/Kconfig | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7b6dda1..a1ea61e 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -292,7 +292,8 @@ static int smbios_write_type0(unsigned long *current, int handle) #endif #endif /* CONFIG_CHROMEOS */ - t->bios_rom_size = (CONFIG_ROM_SIZE / 65535) - 1; + t->bios_rom_size = (CONFIG_ROM_SIZE > (16 * 1024 * 1024)) + ? 255 : (CONFIG_ROM_SIZE / 65535) - 1; t->system_bios_major_release = 4; t->bios_characteristics = diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index ab8ee26..24c1fe3 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -28,6 +28,10 @@ config BOARD_ROMSIZE_KB_12288 bool config BOARD_ROMSIZE_KB_16384 bool +config BOARD_ROMSIZE_KB_32768 + bool +config BOARD_ROMSIZE_KB_65536 + bool # TODO: No help text possible for choice fields? choice @@ -42,6 +46,8 @@ choice default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 + default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 help Select the size of the ROM chip you intend to flash coreboot on. @@ -98,6 +104,16 @@ config COREBOOT_ROMSIZE_KB_16384 help Choose this option if you have a 16384 KB (16 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_32768 + bool "32768 KB (32 MB)" + help + Choose this option if you have a 32768 KB (32 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_65536 + bool "65536 KB (64 MB)" + help + Choose this option if you have a 65536 KB (64 MB) ROM chip. + endchoice # Map the config names to an integer (KB). @@ -113,6 +129,8 @@ config COREBOOT_ROMSIZE_KB default 8192 if COREBOOT_ROMSIZE_KB_8192 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 + default 32768 if COREBOOT_ROMSIZE_KB_32768 + default 65536 if COREBOOT_ROMSIZE_KB_65536 # Map the config names to a hex value (bytes). config ROM_SIZE @@ -127,6 +145,8 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL

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Patch set updated for coreboot: soc/intel/common/acpi: Add _PTS, _WAK methods
by Hannah Williams 08 Jun '16

08 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15121 -gerrit commit 205e7b2b8a65cb0d865153538399deac893f61ec Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Jun 8 14:29:47 2016 -0700 soc/intel/common/acpi: Add _PTS, _WAK methods Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/include/console/post_codes.h | 14 +++++++++++ src/soc/intel/common/acpi/platform.asl | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 4373c78..8e47905 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -245,6 +245,20 @@ #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 /** + * \brief Indicate OS _PTS entry + * + * Called from _PTS asl method + */ +#define POST_OS_ENTER_PTS 0x96 + +/** + * \brief Indicate OS _WAK entry + * + * Called from within _WAK method + */ +#define POST_OS_ENTER_WAKE 0x97 + +/** * \brief Entry into elf boot * * This POST code is called right before invoking jmp_to_elf_entry() diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl new file mode 100644 index 0000000..08fa134 --- /dev/null +++ b/src/soc/intel/common/acpi/platform.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2016 Intel Corp + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <include/console/post_codes.h> + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + Store(POST_OS_ENTER_PTS, DBG0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Store(POST_OS_ENTER_WAKE, DBG0) + Return(Package(){0,0}) +}

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New patch to review for coreboot: soc/apollolake: Set max snoop and non-snoop latency
by Hannah Williams 08 Jun '16

08 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15123 -gerrit commit eb1d3818dc68d358fc35468ee7016f07aa885000 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon May 2 10:08:09 2016 -0700 soc/apollolake: Set max snoop and non-snoop latency Change-Id: I712010d49ca5765503d9534d12b09facbfed0a3e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 6 ++ src/soc/intel/apollolake/pcie.c | 91 ++++++++++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 9e4e160..96be53f 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += uart.c ramstage-y += northbridge.c ramstage-y += spi.c ramstage-y += tsc_freq.c +ramstage-y += pcie.c ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += smi.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 0790c6e..c8f641b 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -25,6 +25,12 @@ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A0 0x5ad8 /* 00:13.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A1 0x5ad9 /* 00:13.1 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A2 0x5ada /* 00:13.2 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_A3 0x5adb /* 00:13.3 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_B0 0x5ad6 /* 00:14.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_PCIE_B1 0x5ad7 /* 00:14.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */ diff --git a/src/soc/intel/apollolake/pcie.c b/src/soc/intel/apollolake/pcie.c new file mode 100644 index 0000000..472f42f --- /dev/null +++ b/src/soc/intel/apollolake/pcie.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <delay.h> + +static void pch_pcie_init(struct device *dev) +{ + u16 reg16; + u32 reg32; + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Enable Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Set Cache Line Size to 0x10 */ + pci_write_config8(dev, 0x0c, 0x10); + + reg16 = pci_read_config16(dev, 0x3e); + reg16 &= ~(1 << 0); /* disable parity error response */ + reg16 |= (1 << 2); /* ISA enable */ + pci_write_config16(dev, 0x3e, reg16); + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, 0x06); + pci_write_config16(dev, 0x06, reg16); + reg16 = pci_read_config16(dev, 0x1e); + pci_write_config16(dev, 0x1e, reg16); +} + +static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) +{ + /* Set max snoop and non-snoop latency for the SOC */ + pci_mmio_write_config32(dev, off, 0x10031003); +} + +static struct pci_operations pcie_ops = { + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pch_pcie_init, + .enable = NULL, + .scan_bus = pciexp_scan_bridge, + .ops_pci = &pcie_ops, +}; + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_APOLLOLAKE_PCIE_A0, + PCI_DEVICE_ID_APOLLOLAKE_PCIE_A1, + PCI_DEVICE_ID_APOLLOLAKE_PCIE_A2, + PCI_DEVICE_ID_APOLLOLAKE_PCIE_A3, + PCI_DEVICE_ID_APOLLOLAKE_PCIE_B0, + PCI_DEVICE_ID_APOLLOLAKE_PCIE_B1, +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +};

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Patch set updated for coreboot: soc/intel/common: Add LPSS I2C driver
by Duncan Laurie 08 Jun '16

08 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15101 -gerrit commit da06db4d3a0c6273d298ec662fbeb7ec9f560c28 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 7 13:40:11 2016 -0700 soc/intel/common: Add LPSS I2C driver Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/common/Kconfig | 15 ++ src/soc/intel/common/Makefile.inc | 3 + src/soc/intel/common/lpss_i2c.c | 379 ++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/lpss_i2c.h | 41 +++++ 4 files changed, 438 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..cab6b46 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -41,6 +41,21 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool default n +config SOC_INTEL_COMMON_LPSS_I2C + bool + default n + help + This driver supports the Intel Low Power Subsystem (LPSS) I2C + controllers that are based on Synopsys DesignWare IP. + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + int + depends on SOC_INTEL_COMMON_LPSS_I2C + help + The clock speed that the I2C controller is running at, in MHz. + No default is set here as this is an SOC-specific value and must + be provided by the SOC when it selects this driver. + config SOC_SETS_MTRRS bool default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..0c02a75 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,8 +1,10 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c @@ -10,6 +12,7 @@ romstage-$(CONFIG_MMA) += mma.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c new file mode 100644 index 0000000..2ac8e66 --- /dev/null +++ b/src/soc/intel/common/lpss_i2c.c @@ -0,0 +1,379 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2009 Vipin Kumar, ST Microelectronics + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <timer.h> +#include "lpss_i2c.h" + +struct lpss_i2c_regs { + uint32_t control; + uint32_t target_addr; + uint32_t slave_addr; + uint32_t master_addr; + uint32_t cmd_data; + uint32_t ss_scl_hcnt; + uint32_t ss_scl_lcnt; + uint32_t fs_scl_hcnt; + uint32_t fs_scl_lcnt; + uint32_t hs_scl_hcnt; + uint32_t hs_scl_lcnt; + uint32_t intr_stat; + uint32_t intr_mask; + uint32_t raw_intr_stat; + uint32_t rx_thresh; + uint32_t tx_thresh; + uint32_t clear_intr; + uint32_t clear_rx_under_intr; + uint32_t clear_rx_over_intr; + uint32_t clear_tx_over_intr; + uint32_t clear_rd_req_intr; + uint32_t clear_tx_abrt_intr; + uint32_t clear_rx_done_intr; + uint32_t clear_activity_intr; + uint32_t clear_stop_det_intr; + uint32_t clear_start_det_intr; + uint32_t clear_gen_call_intr; + uint32_t enable; + uint32_t status; + uint32_t tx_level; + uint32_t rx_level; + uint32_t sda_hold; + uint32_t tx_abort_source; +} __attribute__((packed)); + +/* Use a ~2ms timeout for various operations */ +#define LPSS_I2C_TIMEOUT_US 2000 + +/* High and low times in different speed modes (in ns) */ +enum { + /* Standard Speed */ + MIN_SS_SCL_HIGHTIME = 4000, + MIN_SS_SCL_LOWTIME = 4700, + /* Fast/Fast+ Speed */ + MIN_FS_SCL_HIGHTIME = 600, + MIN_FS_SCL_LOWTIME = 1300, + /* High Speed */ + MIN_HS_SCL_HIGHTIME = 60, + MIN_HS_SCL_LOWTIME = 160, +}; + +/* Control register definitions */ +enum { + CONTROL_MASTER_MODE = (1 << 0), + CONTROL_SPEED_SS = (1 << 1), + CONTROL_SPEED_FS = (1 << 2), + CONTROL_SPEED_HS = (3 << 1), + CONTROL_SPEED_MASK = (3 << 1), + CONTROL_10BIT_SLAVE = (1 << 3), + CONTROL_10BIT_MASTER = (1 << 4), + CONTROL_RESTART_ENABLE = (1 << 5), + CONTROL_SLAVE_DISABLE = (1 << 6), +}; + +/* Command/Data register definitions */ +enum { + CMD_DATA_CMD = (1 << 8), + CMD_DATA_STOP = (1 << 9), +}; + +/* Status register definitions */ +enum { + STATUS_ACTIVITY = (1 << 0), + STATUS_TX_FIFO_NOT_FULL = (1 << 1), + STATUS_TX_FIFO_EMPTY = (1 << 2), + STATUS_RX_FIFO_NOT_EMPTY = (1 << 3), + STATUS_RX_FIFO_FULL = (1 << 4), + STATUS_MASTER_ACTIVITY = (1 << 5), + STATUS_SLAVE_ACTIVITY = (1 << 6), +}; + +/* Enable register definitions */ +enum { + ENABLE_CONTROLLER = (1 << 0), +}; + +/* Interrupt status register definitions */ +enum { + INTR_STAT_RX_UNDER = (1 << 0), + INTR_STAT_RX_OVER = (1 << 1), + INTR_STAT_RX_FULL = (1 << 2), + INTR_STAT_TX_OVER = (1 << 3), + INTR_STAT_TX_EMPTY = (1 << 4), + INTR_STAT_RD_REQ = (1 << 5), + INTR_STAT_TX_ABORT = (1 << 6), + INTR_STAT_RX_DONE = (1 << 7), + INTR_STAT_ACTIVITY = (1 << 8), + INTR_STAT_STOP_DET = (1 << 9), + INTR_STAT_START_DET = (1 << 10), + INTR_STAT_GEN_CALL = (1 << 11), +}; + +/* Enable this I2C controller */ +static void lpss_i2c_enable(struct lpss_i2c_regs *regs) +{ + uint32_t enable = read32(&regs->enable); + + if (!(enable & ENABLE_CONTROLLER)) + write32(&regs->enable, enable | ENABLE_CONTROLLER); +} + +/* Disable this I2C controller */ +static int lpss_i2c_disable(struct lpss_i2c_regs *regs) +{ + uint32_t enable = read32(&regs->enable); + + if (enable & ENABLE_CONTROLLER) { + struct stopwatch sw; + + write32(&regs->enable, enable & ~ENABLE_CONTROLLER); + + /* Wait for enable bit to clear */ + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + while (read32(&regs->enable) & ENABLE_CONTROLLER) + if (stopwatch_expired(&sw)) + return -1; + } + + return 0; +} + +/* Wait for this I2C controller to go idle for transmit */ +static int lpss_i2c_wait_for_bus_idle(struct lpss_i2c_regs *regs) +{ + struct stopwatch sw; + + /* Start timeout for up to 16 bytes in FIFO */ + stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); + + while (!stopwatch_expired(&sw)) { + uint32_t status = read32(&regs->status); + + /* Check for master activity and keep waiting */ + if (status & STATUS_MASTER_ACTIVITY) + continue; + + /* Check for TX FIFO empty to indicate TX idle */ + if (status & STATUS_TX_FIFO_EMPTY) + return 0; + } + + /* Timed out while waiting for bus to go idle */ + return -1; +} + +/* Transfer one byte of one segment, sending stop bit if requested */ +static int lpss_i2c_transfer_byte(struct lpss_i2c_regs *regs, + struct i2c_seg *segment, + size_t byte, int send_stop) +{ + struct stopwatch sw; + uint32_t cmd = CMD_DATA_CMD; /* Read op */ + + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + + if (!segment->read) { + /* Write op only: Wait for FIFO not full */ + while (!(read32(&regs->status) & STATUS_TX_FIFO_NOT_FULL)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C transmit timeout\n"); + return -1; + } + } + cmd = segment->buf[byte]; + } + + /* Send stop on last byte, if desired */ + if (send_stop && byte == segment->len - 1) + cmd |= CMD_DATA_STOP; + + write32(&regs->cmd_data, cmd); + + if (segment->read) { + /* Read op only: Wait for FIFO data and store it */ + while (!(read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C receive timeout\n"); + return -1; + } + } + segment->buf[byte] = read32(&regs->cmd_data); + } + + return 0; +} + +/* Global I2C bus handler, defined in include/i2c.h */ +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) +{ + struct stopwatch sw; + struct lpss_i2c_regs *regs; + size_t byte; + + if (count <= 0 || !segments) + return -1; + + regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); + if (!regs) { + printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); + return -1; + } + + if (!(read32(&regs->enable) & ENABLE_CONTROLLER)) { + printk(BIOS_ERR, "I2C bus %u not initialized\n", bus); + return -1; + } + + if (lpss_i2c_wait_for_bus_idle(regs)) { + printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); + return -1; + } + + /* Process each segment */ + while (count--) { + /* Set target slave address */ + write32(&regs->target_addr, segments->chip); + + /* Read or write each byte in segment */ + for (byte = 0; byte < segments->len; byte++) { + /* + * Set stop condition on final segment only. + * Repeated start will be automatically generated + * by the controller on R->W or W->R switch. + */ + if (lpss_i2c_transfer_byte(regs, segments, byte, + count == 0) < 0) { + printk(BIOS_ERR, "I2C %s failed: bus %u " + "addr 0x%02x\n", segments->read ? + "read" : "write", bus, segments->chip); + return -1; + } + } + segments++; + } + + /* Wait for interrupt status to indicate transfer is complete */ + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + while (!(read32(&regs->raw_intr_stat) & INTR_STAT_STOP_DET)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C stop bit not received\n"); + return -1; + } + } + + /* Read to clear INTR_STAT_STOP_DET */ + read32(&regs->clear_stop_det_intr); + + /* Wait for the bus to go idle */ + if (lpss_i2c_wait_for_bus_idle(regs)) { + printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); + return -1; + } + + /* Flush the RX FIFO in case it is not empty */ + stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); + while (read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n"); + return -1; + } + read32(&regs->cmd_data); + } + + return 0; +} + +static void lpss_i2c_set_speed(struct lpss_i2c_regs *regs, enum i2c_speed speed) +{ + const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ; + uint32_t control, hcnt_min, lcnt_min; + void *hcnt_reg, *lcnt_reg; + + /* Clock must be provided by Kconfig */ + if (!ic_clk || !speed) + return; + + control = read32(&regs->control); + control &= ~CONTROL_SPEED_MASK; + + if (speed >= I2C_SPEED_HIGH) { + /* High Speed */ + control |= CONTROL_SPEED_HS; + hcnt_reg = &regs->hs_scl_hcnt; + lcnt_reg = &regs->hs_scl_lcnt; + hcnt_min = MIN_HS_SCL_HIGHTIME; + lcnt_min = MIN_HS_SCL_LOWTIME; + } else if (speed >= I2C_SPEED_FAST) { + /* Fast Speed */ + control |= CONTROL_SPEED_FS; + hcnt_reg = &regs->fs_scl_hcnt; + lcnt_reg = &regs->fs_scl_lcnt; + hcnt_min = MIN_FS_SCL_HIGHTIME; + lcnt_min = MIN_FS_SCL_LOWTIME; + } else { + /* Standard Speed */ + control |= CONTROL_SPEED_SS; + hcnt_reg = &regs->ss_scl_hcnt; + lcnt_reg = &regs->ss_scl_lcnt; + hcnt_min = MIN_SS_SCL_HIGHTIME; + lcnt_min = MIN_SS_SCL_LOWTIME; + } + + /* Select this speed in the control register */ + write32(&regs->control, control); + + /* SCL count must be set after the speed is selected */ + write32(hcnt_reg, ic_clk * hcnt_min / KHz); + write32(lcnt_reg, ic_clk * lcnt_min / KHz); +} + +void lpss_i2c_init(unsigned bus, enum i2c_speed speed) +{ + struct lpss_i2c_regs *regs; + + regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); + if (!regs) { + printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); + return; + } + + if (lpss_i2c_disable(regs) < 0) { + printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); + return; + } + + /* Put controller in master mode with restart enabled */ + write32(&regs->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE | + CONTROL_RESTART_ENABLE); + + /* Set bus speed to FAST by default */ + lpss_i2c_set_speed(regs, speed ? : I2C_SPEED_FAST); + + /* Set RX/TX thresholds to smallest values */ + write32(&regs->rx_thresh, 0); + write32(&regs->tx_thresh, 0); + + /* Enable stop detection interrupt */ + write32(&regs->intr_mask, INTR_STAT_STOP_DET); + + lpss_i2c_enable(regs); + + printk(BIOS_INFO, "LPSS I2C bus %u at 0x%p (%u KHz)\n", + bus, regs, (speed ? : I2C_SPEED_FAST) / KHz); +} diff --git a/src/soc/intel/common/lpss_i2c.h b/src/soc/intel/common/lpss_i2c.h new file mode 100644 index 0000000..8259414 --- /dev/null +++ b/src/soc/intel/common/lpss_i2c.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_LPSS_I2C_H +#define SOC_INTEL_COMMON_LPSS_I2C_H + +#include <device/i2c.h> +#include <stdint.h> + +/* + * Return the base address for this bus controller. + * + * This function *must* be implemented by the SOC and return the appropriate + * base address for the I2C registers that correspond to the provided bus. + */ +uintptr_t lpss_i2c_base_address(unsigned bus); + +/* + * Initialize this bus controller and set the speed. + * + * The bus speed can be passed in Hz or using values from device/i2c.h and + * will default to I2C_SPEED_FAST if it is not provided. + * + * The SOC *must* define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK for the + * bus speed calculation to be correct. + */ +void lpss_i2c_init(unsigned bus, enum i2c_speed speed); + +#endif

1 0

Patch set updated for coreboot: i945: Enable changing VRAM size
by Arthur Heymans 08 Jun '16

08 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14819 -gerrit commit 2547f631ea1d0f9cf60724ec7aeee9de1ba79fc5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu May 19 16:06:09 2016 +0200 i945: Enable changing VRAM size On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/cmos.default | 1 + src/mainboard/apple/macbook21/cmos.layout | 11 ++++++++++- src/mainboard/getac/p470/cmos.layout | 11 ++++++++++- src/mainboard/ibase/mb899/cmos.layout | 12 +++++++++++- src/mainboard/intel/d945gclf/cmos.layout | 11 ++++++++++- src/mainboard/kontron/986lcd-m/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/t60/cmos.default | 1 + src/mainboard/lenovo/t60/cmos.layout | 12 +++++++++++- src/mainboard/lenovo/x60/cmos.default | 1 + src/mainboard/lenovo/x60/cmos.layout | 11 ++++++++++- src/mainboard/roda/rk886ex/cmos.layout | 12 +++++++++++- src/northbridge/intel/i945/early_init.c | 11 ++++++----- src/northbridge/intel/i945/gma.c | 12 +----------- src/northbridge/intel/i945/i945.h | 2 ++ src/northbridge/intel/i945/northbridge.c | 12 +----------- src/northbridge/intel/i945/ram_calc.c | 13 +++++++++++++ 16 files changed, 110 insertions(+), 35 deletions(-) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 37018a4..1cf350c 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -17,3 +17,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index c11997c..b56e5be 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -59,7 +59,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -124,6 +126,13 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index 023bdfa..d61f1b4 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -59,7 +59,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -112,6 +114,13 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index 1ef4361..0441036 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -159,6 +161,14 @@ enumerations #10 13 69/156 #10 14 72/161 #10 15 75/167 +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 31f2b20..c6cfec6 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -106,6 +108,13 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index f9fb424..db9dced 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -58,7 +58,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 12 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -164,6 +166,14 @@ enumerations #10 15 75/167 11 0 No 11 1 Yes +12 0 1M +12 1 4M +12 2 8M +12 3 16M +12 4 32M +12 5 48M +12 6 64M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index 5dd0c70..03b92e3 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -18,3 +18,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index e5879d6..ae38b21 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -57,7 +57,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -127,6 +129,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 3579757..4e72734 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -18,3 +18,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable +gfx_uma_size=8M \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 54a2799..3474050 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -57,7 +57,9 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -127,6 +129,13 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 023bdfa..ddb4dad 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -59,7 +59,10 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused + +# coreboot config options: northbridge +411 3 e 11 gfx_uma_size + # coreboot config options: bootloader 416 512 s 0 boot_devices @@ -112,6 +115,13 @@ enumerations 7 2 Keep 8 0 No 8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 475e88a..1e04879 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -22,6 +22,7 @@ #include <halt.h> #include <string.h> #include "i945.h" +#include <pc80/mc146818rtc.h> int i945_silicon_revision(void) { @@ -144,7 +145,7 @@ static void i945_detect_chipset(void) static void i945_setup_bars(void) { - u8 reg8; + u8 reg8, gfxsize; /* As of now, we don't have all the A0 workarounds implemented */ if (i945_silicon_revision() == 0) @@ -177,10 +178,10 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); - /* Hardware default is 8MB UMA. If someone wants to make this a - * CMOS or compile time option, send a patch. - * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); - */ + /* vram size from cmos option */ + if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) + gfxsize = 2; /* 2 for 8MB */ + pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, ((gfxsize + 1) << 4)); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index df13ef4..02caa0a 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -353,17 +353,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); uma_size = 0; if (!(reg16 & 2)) { - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } - + uma_size = decode_igd_memory_size((reg16 >> 4) & 7); printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); } diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 0536a36..a7a3c5c 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -364,6 +364,8 @@ void dump_pci_devices(void); void dump_spd_registers(void); void dump_mem(unsigned start, unsigned end); +u32 decode_igd_memory_size(u32 gms); + #endif /* __ACPI__ */ #endif /* NORTHBRIDGE_INTEL_I945_H */ diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 514f88c..719a795 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -104,18 +104,8 @@ static void pci_domain_set_resources(device_t dev) /* Note: subtract IGD device and TSEG */ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); if (!(reg16 & 2)) { - int uma_size = 0; printk(BIOS_DEBUG, "IGD decoded, subtracting "); - reg16 >>= 4; - reg16 &= 7; - switch (reg16) { - case 1: - uma_size = 1024; - break; - case 3: - uma_size = 8192; - break; - } + int uma_size = decode_igd_memory_size((reg16 >> 4) & 7); printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); tomk_stolen -= uma_size; diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index b161431..ef21315 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <cbmem.h> #include "i945.h" +#include <console/console.h> static uintptr_t smm_region_start(void) { @@ -56,3 +57,15 @@ void *cbmem_top(void) { return (void *) smm_region_start(); } + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + static const u16 ggc2uma[] = { 1, 4, 8, 16, 32, + 48, 64 }; + + if (gms > ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +}

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Patch set updated for coreboot: rockchip: rk3399: pass board specific message to BL31
by Martin Roth 08 Jun '16

08 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15116 -gerrit commit cc9634b50a142cf699923a10a94d073a3202b3a6 Author: Lin Huang <hl(a)rock-chips.com> Date: Tue May 17 15:45:05 2016 +0800 rockchip: rk3399: pass board specific message to BL31 Sometime we need to pass board specific message to BL31, with that BL31 can do board specific operate base on common code. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I096878699c6e6933debdf2fb3423734f538691ae Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: Original-Change-Id: Ib7585ce7d3bf01d3ce53b388bf9bd60f3b65f5f1 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349700 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/soc/rockchip/rk3399/Makefile.inc | 1 + src/soc/rockchip/rk3399/bl31_plat_params.c | 32 ++++++++++++++++++++++ .../rockchip/rk3399/include/soc/bl31_plat_params.h | 24 ++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 77958d5..9a4817f 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -68,6 +68,7 @@ ramstage-y += soc.c ramstage-y += timer.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c +ramstage-y += bl31_plat_params.c BL31_MAKEARGS += PLAT=rk3399 ################################################################################ diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c new file mode 100644 index 0000000..583eac8 --- /dev/null +++ b/src/soc/rockchip/rk3399/bl31_plat_params.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arm_tf.h> +#include <assert.h> +#include <soc/bl31_plat_params.h> + +static struct bl31_plat_param *plat_params; + +void register_bl31_param(struct bl31_plat_param *param) +{ + param->next = plat_params; + plat_params = param; +} + +void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +{ + return plat_params; +} diff --git a/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h b/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h new file mode 100644 index 0000000..c73d687 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __BL31_PLAT_PARAMS_H__ +#define __BL31_PLAT_PARAMS_H__ + +#include <arm-trusted-firmware/plat/rockchip/common/include/plat_params.h> + +void register_bl31_param(struct bl31_plat_param *param); + +#endif/* __BL31_PLAT_PARAMS_H__ */

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New patch to review for coreboot: 3rdparty/arm-trusted-firmware: Update to Jun 8, 2016 master
by Martin Roth 08 Jun '16

08 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15122 -gerrit commit 0da56caa88185f96bae733959e7032f792271e74 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jun 8 16:41:56 2016 -0600 3rdparty/arm-trusted-firmware: Update to Jun 8, 2016 master 90 patches pulled in. Change-Id: I3b893957cbd330e71d0f218262e768f577df4c66 Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/arm-trusted-firmware | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 32d4f82..e4f51ee 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 32d4f826875a49fe1c4632aa71d1c04372b386aa +Subproject commit e4f51eee91187e980f5e0e436c65f325fc35c94b

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Patch set updated for coreboot: Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices
by Martin Roth 08 Jun '16

08 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15113 -gerrit commit 7e44cf91a987baf3787f1186b3cda5a9642d3d7e Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jun 1 14:53:48 2016 -0700 Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devices The VBOOT_OPROM_MATTERS configuration option signals to vboot that the board can skip display initialization in the normal boot path. It's name is a left-over from a time when this could only happen by avoiding loading the VGA option ROM on x86 devices. Now we have other boards that can skip their native display initialization paths too, and the effect to vboot is the same. (Really, we should rename oprom_matters and oprom_loaded to display_skippable and display_initialized or something, but I don't think that's worth the amount of repositories this would need to touch.) The only effect this still has in today's vboot is to reboot and explicitly request display initialization for EC software sync on VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still, the vboot flag just declares the capability (for skipping display init), and it should be set correctly regardless of whether that actually makes a difference on a given platform (right now). This patch updates all boards/SoCs that have a conditional path based on display_init_required() accordingly. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak, confirmed that there's no notable boot time impact. Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348786 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 1 + src/soc/nvidia/tegra124/Kconfig | 3 +++ src/soc/nvidia/tegra132/Kconfig | 3 +++ src/soc/nvidia/tegra210/Kconfig | 1 + src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3399/Kconfig | 1 + src/vendorcode/google/chromeos/Kconfig | 9 +++++++-- 7 files changed, 17 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 34031bc..87849a3 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -36,6 +36,7 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select CHROMEOS_VBNV_FLASH select EC_SOFTWARE_SYNC + select VBOOT_OPROM_MATTERS select VIRTUAL_DEV_SWITCH config MAINBOARD_DIR diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index bd38d76..49929ad 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -16,6 +16,9 @@ config SOC_NVIDIA_TEGRA124 if SOC_NVIDIA_TEGRA124 +config CHROMEOS + select VBOOT_OPROM_MATTERS + config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index 08ed475..b470892 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -17,6 +17,9 @@ config SOC_NVIDIA_TEGRA132 if SOC_NVIDIA_TEGRA132 +config CHROMEOS + select VBOOT_OPROM_MATTERS + config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" depends on MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 2601c70..39c0152 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -19,6 +19,7 @@ if SOC_NVIDIA_TEGRA210 config CHROMEOS select CHROMEOS_RAMOOPS_NON_ACPI + select VBOOT_OPROM_MATTERS config MAINBOARD_DO_DSI_INIT bool "Use dsi graphics interface" diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 0f394b1..ea34bb9 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -32,6 +32,7 @@ config SOC_ROCKCHIP_RK3288 if SOC_ROCKCHIP_RK3288 config CHROMEOS + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK select SEPARATE_VERSTAGE select RETURN_FROM_VERSTAGE diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 38d0f00..63e343e 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -19,6 +19,7 @@ if SOC_ROCKCHIP_RK3399 config CHROMEOS select RETURN_FROM_VERSTAGE select SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_BOOTBLOCK config PMIC_BUS diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 7726895..269c176 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -111,11 +111,16 @@ config VBOOT_EC_SLOW_UPDATE screen that informs the user the update is happening. config VBOOT_OPROM_MATTERS - bool "Video option ROM matters" + bool "Video option ROM matters (= can skip display init)" default n depends on VBOOT_VERIFY_FIRMWARE help - Whether the video option ROM has run matters on this platform. + Set this option to indicate to vboot that this platform will skip its + display initialization on a normal (non-recovery, non-developer) boot. + Vboot calls this "oprom matters" because on x86 devices this + traditionally meant that the video option ROM will not be loaded, but + it works functionally the same for other platforms that can skip their + native display initialization code instead. config VIRTUAL_DEV_SWITCH bool "Virtual developer switch support"

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New patch to review for coreboot: soc/intel/apollolake: Add _PTS, _WAK and _SWS
by Hannah Williams 08 Jun '16

08 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15121 -gerrit commit 0fae848214e6ba92b5b7532ec9b01363d59bb7dc Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Jun 8 14:29:47 2016 -0700 soc/intel/apollolake: Add _PTS, _WAK and _SWS Change-Id: I72f894fd14bf0e333d9fda970397a3c82de598c3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/include/console/post_codes.h | 14 +++++++++ src/soc/intel/apollolake/acpi/platform.asl | 46 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index 4373c78..8e47905 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -245,6 +245,20 @@ #define POST_FSP_NOTIFY_BEFORE_FINALIZE 0x95 /** + * \brief Indicate OS _PTS entry + * + * Called from _PTS asl method + */ +#define POST_OS_ENTER_PTS 0x96 + +/** + * \brief Indicate OS _WAK entry + * + * Called from within _WAK method + */ +#define POST_OS_ENTER_WAKE 0x97 + +/** * \brief Entry into elf boot * * This POST code is called right before invoking jmp_to_elf_entry() diff --git a/src/soc/intel/apollolake/acpi/platform.asl b/src/soc/intel/apollolake/acpi/platform.asl new file mode 100644 index 0000000..7c0ac4a --- /dev/null +++ b/src/soc/intel/apollolake/acpi/platform.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2016 Intel Corp + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <include/console/post_codes.h> + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + Store(POST_OS_ENTER_PTS, DBG0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Store(POST_OS_ENTER_WAKE, DBG0) + Return(Package(){0,0}) +}

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coreboot-gerrit June 2016