coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: autoport: Add prompt for enabling unsafe inteltool glx option
by Chris Ching 08 Jun '16

08 Jun '16

Chris Ching (chingcodes(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14901 -gerrit commit c6902e37a4d584e672336842e76c0c9115ed09d9 Author: Chris Ching <chingcodes(a)google.com> Date: Tue May 17 11:56:03 2016 -0600 autoport: Add prompt for enabling unsafe inteltool glx option Change-Id: Ib674ab7ca8b6464de553a86536b1762fda98d94e Signed-off-by: Chris Ching <chingcodes(a)google.com> --- util/autoport/log_maker.go | 45 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/util/autoport/log_maker.go b/util/autoport/log_maker.go index bae24c8..50e0e65 100644 --- a/util/autoport/log_maker.go +++ b/util/autoport/log_maker.go @@ -1,6 +1,8 @@ package main import ( + "errors" + "fmt" "io" "io/ioutil" "log" @@ -45,13 +47,52 @@ func RunAndSave(output string, name string, arg ...string) { } } +const MAXPROMPTRETRY = 3 + +func PromptUser(prompt string, opts []string) (match string, err error) { + for i := 1; i < MAXPROMPTRETRY; i++ { + fmt.Println("%s. (%s) Default:%s", prompt, strings.Join(opts, "/"), opts[0]) + var usrInput string + fmt.Scanln(&usrInput) + + // Check for default entry + if usrInput == "" { + match = opts[0] + return + } + + for _, opt := range opts { + if opt == usrInput { + match = opt + return + } + } + } + err = errors.New("max retries exceeded") + fmt.Fprintln(os.Stderr, "ERROR: max retries exceeded") + return +} + func MakeLogs(outDir string) { os.MkdirAll(outDir, 0700) RunAndSave(outDir+"/lspci.log", "lspci", "-nnvvvxxxx") RunAndSave(outDir+"/dmidecode.log", "dmidecode") RunAndSave(outDir+"/acpidump.log", "acpidump") - /* FIXME:XX */ - RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", "-a") + + inteltoolArgs := "-a" + opt, err := PromptUser("WARNING: The following tool MAY cause your system to hang when it attempts "+ + "to probe for graphics registers. Having the graphics registers will help create a better port. "+ + "Should autoport probe these registers?", + []string{"y", "yes", "n", "no"}) + + // Continue even if there is an error + + switch opt { + case "y", "yes": + opt += " -f" + } + + RunAndSave(outDir+"/inteltool.log", "../inteltool/inteltool", inteltoolArgs) RunAndSave(outDir+"/ectool.log", "../ectool/ectool") SysDir := "/sys/class/sound/card0/"

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Patch merged into coreboot/master: inteltool: handle unsafe dumping of graphics registers
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 37fcd58ba6980222a5b51ea21ee266e5d34c04a2 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Tue May 10 23:16:33 2016 +0200 inteltool: handle unsafe dumping of graphics registers The current implementation from Vladimir simply dumps 1 MB of memory contents starting at the base address of the second PCI device (which most likely is the VGA controller on Intel systems). This locks up a number of different systems, e.g. my Ibex Peak-based T410s. This patch documents the issue and stops dumping the graphics registers for the -a/--all parameter. Change-Id: I581bdc63db60afaf4792bc11fbeed73aab57f63a Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: https://review.coreboot.org/14627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/14627 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 6a587343a96167c21d63ace1857ee2d55cdebfa0 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 30 18:05:57 2015 -0700 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/13331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13331 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: Add SOC specific c-state table
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 0f61da85820c518341240ce0b60ebfec70187fc0 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: Add SOC specific c-state table Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/15051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15051 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common: Add common code for acpi c/p/t-state entries
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit f8daa378614178263b705fbd9e1251bb4b8d148d Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/intel/common: Add common code for acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/15050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15050 for details. -gerrit

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Patch set updated for coreboot: gru: kevin: define GPIOs used on both platforms
by Martin Roth 08 Jun '16

08 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15029 -gerrit commit 1032c953ff94cef8e118bc76174dc47ac494e8b6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Sun May 22 15:53:37 2016 -0700 gru: kevin: define GPIOs used on both platforms The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: c587880 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> --- src/mainboard/google/gru/board.h | 30 ++++++++++++++++++++++++++++++ src/mainboard/google/gru/mainboard.c | 2 ++ 2 files changed, 32 insertions(+) diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h new file mode 100644 index 0000000..6d80cdf --- /dev/null +++ b/src/mainboard/google/gru/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H + +#include <gpio.h> + +#define GPIO_BACKLIGHT GPIO(1, C, 1) +#define GPIO_EC_IN_RW GPIO(3, B, 0) +#define GPIO_EC_IRQ GPIO(0, A, 1) +#define GPIO_RESET GPIO(0, B, 3) +#define GPIO_WP GPIO(1, C, 2) + +void setup_chromeos_gpios(void); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H */ diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 0ccedd3..54443bc 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -25,6 +25,8 @@ #include <soc/grf.h> #include <soc/i2c.h> +#include "board.h" + static void configure_emmc(void) { /* Host controller does not support programmable clock generator.

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Patch merged into coreboot/master: mainboard/intel/amenia: Enable VIRT_DEV_SWITCH
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 5f8cdc641bda2204bc7ea75c8b932e637a7f32b6 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed May 18 12:33:02 2016 -0700 mainboard/intel/amenia: Enable VIRT_DEV_SWITCH Enable virtual dev switch config. BUG=None TEST= On Dev FW screen, press SPACE key to boot to normal mode Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Reviewed-on: https://review.coreboot.org/15080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15080 for details. -gerrit

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Patch merged into coreboot/master: Intel/amenia: Make the device address more readable
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 1c6c5836bdecc03a126ed96e2b40aeca086172b7 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Mar 16 17:48:06 2016 -0700 Intel/amenia: Make the device address more readable Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/15083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15083 for details. -gerrit

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New patch to review for coreboot: mainboard: Support ROM_SIZE > 16 MiB
by Leroy P Leahy 08 Jun '16

08 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15108 -gerrit commit 42e95ef8c8248498363160836bcc85d17c75dccb Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jun 8 12:47:07 2016 -0700 mainboard: Support ROM_SIZE > 16 MiB Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size limitation of 16 MiB by specifying 16 MiB as the ROM size. TEST=Build and run on neoncity Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- src/arch/x86/smbios.c | 3 ++- src/mainboard/Kconfig | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7b6dda1..a1ea61e 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -292,7 +292,8 @@ static int smbios_write_type0(unsigned long *current, int handle) #endif #endif /* CONFIG_CHROMEOS */ - t->bios_rom_size = (CONFIG_ROM_SIZE / 65535) - 1; + t->bios_rom_size = (CONFIG_ROM_SIZE > (16 * 1024 * 1024)) + ? 255 : (CONFIG_ROM_SIZE / 65535) - 1; t->system_bios_major_release = 4; t->bios_characteristics = diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index ab8ee26..dade4a1 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -28,6 +28,10 @@ config BOARD_ROMSIZE_KB_12288 bool config BOARD_ROMSIZE_KB_16384 bool +config BOARD_ROMSIZE_KB_32768 + bool +config BOARD_ROMSIZE_KB_65536 + bool # TODO: No help text possible for choice fields? choice @@ -42,6 +46,8 @@ choice default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 + default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 help Select the size of the ROM chip you intend to flash coreboot on. @@ -98,6 +104,16 @@ config COREBOOT_ROMSIZE_KB_16384 help Choose this option if you have a 16384 KB (16 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_32768 + bool "32768 KB (32 MB)" + help + Choose this option if you have a 32768 KB (32 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_16384 + bool "65536 KB (64 MB)" + help + Choose this option if you have a 65536 KB (64 MB) ROM chip. + endchoice # Map the config names to an integer (KB). @@ -113,6 +129,8 @@ config COREBOOT_ROMSIZE_KB default 8192 if COREBOOT_ROMSIZE_KB_8192 default 12288 if COREBOOT_ROMSIZE_KB_12288 default 16384 if COREBOOT_ROMSIZE_KB_16384 + default 32768 if COREBOOT_ROMSIZE_KB_32768 + default 65536 if COREBOOT_ROMSIZE_KB_65536 # Map the config names to a hex value (bytes). config ROM_SIZE @@ -127,6 +145,8 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL

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New patch to review for coreboot: WIP: nb/intel/sandybridge: Implement dynamic PCI mmio size
by Patrick Rudolph 08 Jun '16

08 Jun '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15107 -gerrit commit bdca6dfcf1994a77fcf84fd82c3ab74eea936aa1 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Jun 6 19:30:37 2016 +0200 WIP: nb/intel/sandybridge: Implement dynamic PCI mmio size Verify that all PCI BARs fit into PCI mmio space. In case the space isn't sufficient or isn't used by PCI devices modify the mrc.cache to apply a different value on next boot. In case the PCI mmio space is to small initiate a reboot. Tested on Lenovo T520: The device reboots a single time to apply the new TOLUD and then successfully boots into GNU/Linux without the need to modify PCI mmio size by hand. Change-Id: Ibaafa46fd014c1a64775259cfd407c07e71350b4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/common/mrc_cache.c | 2 +- src/northbridge/intel/common/mrc_cache.h | 1 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/northbridge.c | 20 +++- src/northbridge/intel/sandybridge/raminit.c | 106 ++---------------- .../intel/sandybridge/raminit_memorymap.c | 68 ++++++++++++ .../intel/sandybridge/raminit_memorymap.h | 20 ++++ .../intel/sandybridge/raminit_private.h | 118 +++++++++++++++++++++ 8 files changed, 237 insertions(+), 99 deletions(-) diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index 4c3ee5d..a64d018 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -153,7 +153,7 @@ static struct mrc_data_container *find_next_mrc_cache return mrc_cache; } -static void update_mrc_cache(void *unused) +void update_mrc_cache(void *unused) { printk(BIOS_DEBUG, "Updating MRC cache data.\n"); struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA); diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index 1fb6667..decb84c 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -14,5 +14,6 @@ struct mrc_data_container { struct mrc_data_container *find_current_mrc_cache(void); struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length); +void update_mrc_cache(void *unused); #endif /* NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H */ diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index b1bc2ac..035e55b 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,6 +22,7 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c +ramstage-y += raminit_memorymap.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 53d93a2..1829782 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -33,6 +33,7 @@ #include "chip.h" #include "sandybridge.h" #include <cpu/intel/smm/gen1/smi.h> +#include "raminit_memorymap.h" static int bridge_revision_id = -1; @@ -141,7 +142,7 @@ static void add_fixed_resources(struct device *dev, int index) static void pci_domain_set_resources(device_t dev) { uint64_t tom, me_base, touud; - uint32_t tseg_base, uma_size, tolud; + uint32_t tseg_base, tseg_size, uma_size, tolud, tolud_used; uint16_t ggc; unsigned long long tomk; @@ -187,6 +188,23 @@ static void pci_domain_set_resources(device_t dev) printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom); + /* Top of Lower Usable DRAM */ + tolud = pci_read_config32(dev, TOLUD); + + /* Make sure all dynamic resources fit into PCI mmio space */ + tolud_used = dev_verify_resources(tolud); + if (tolud_used) { + printk(BIOS_DEBUG, "TOLUD required 0x%08x\n", tolud_used); + + northbridge_get_tseg_base_and_size(&tseg_base, &tseg_size); + + if (tolud_used < tolud) + dram_ddr3_set_tolud(tolud_used, 1); + /* FIXME: tseg alignment */ + else if ((tolud_used - tseg_size) > tolud) + dram_ddr3_set_tolud(tolud_used, 0); + } + /* ME UMA needs excluding if total memory <4GB */ me_base = pci_read_config32(dev, 0x74); me_base <<= 32; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6bb77b2..efd6c2d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -31,6 +31,7 @@ #include <memory_info.h> #include <smbios.h> #include "raminit_native.h" +#include "raminit_private.h" #include "sandybridge.h" #include <delay.h> #include <lib.h> @@ -94,101 +95,6 @@ #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) -#define NUM_CHANNELS 2 -#define NUM_SLOTRANKS 4 -#define NUM_SLOTS 2 -#define NUM_LANES 8 - -/* FIXME: Vendor BIOS uses 64 but our algorithms are less - performant and even 1 seems to be enough in practice. */ -#define NUM_PATTERNS 4 - -typedef struct odtmap_st { - u16 rttwr; - u16 rttnom; -} odtmap; - -typedef struct dimm_info_st { - dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; -} dimm_info; - -struct ram_rank_timings { - /* Register 4024. One byte per slotrank. */ - u8 val_4024; - /* Register 4028. One nibble per slotrank. */ - u8 val_4028; - - int val_320c; - - struct ram_lane_timings { - /* lane register offset 0x10. */ - u16 timA; /* bits 0 - 5, bits 16 - 18 */ - u8 rising; /* bits 8 - 14 */ - u8 falling; /* bits 20 - 26. */ - - /* lane register offset 0x20. */ - int timC; /* bit 0 - 5, 19. */ - u16 timB; /* bits 8 - 13, 15 - 17. */ - } lanes[NUM_LANES]; -}; - -struct ramctr_timing_st; - -typedef struct ramctr_timing_st { - u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; - int mobile; - - u16 cas_supported; - /* tLatencies are in units of ns, scaled by x256 */ - u32 tCK; - u32 tAA; - u32 tWR; - u32 tRCD; - u32 tRRD; - u32 tRP; - u32 tRAS; - u32 tRFC; - u32 tWTR; - u32 tRTP; - u32 tFAW; - /* Latencies in terms of clock cycles - * They are saved separately as they are needed for DRAM MRS commands*/ - u8 CAS; /* CAS read latency */ - u8 CWL; /* CAS write latency */ - - u32 tREFI; - u32 tMOD; - u32 tXSOffset; - u32 tWLO; - u32 tCKE; - u32 tXPDLL; - u32 tXP; - u32 tAONPD; - - u16 reg_5064b0; /* bits 0-11. */ - - u8 rankmap[NUM_CHANNELS]; - int ref_card_offset[NUM_CHANNELS]; - u32 mad_dimm[NUM_CHANNELS]; - int channel_size_mb[NUM_CHANNELS]; - u32 cmd_stretch[NUM_CHANNELS]; - - int reg_c14_offset; - int reg_320c_range_threshold; - - int edge_offset[3]; - int timC_offset[3]; - - int extended_temperature_range; - int auto_self_refresh; - - int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; - - struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; - - dimm_info info; -} ramctr_timing; - #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) #define NORTHBRIDGE PCI_DEV(0, 0x0, 0) #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) @@ -1103,8 +1009,14 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) mestolenbase = tom - me_uma_size; - toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, - tom - me_uma_size); + if (ctrl->pci_tolud_base) { + printk(BIOS_DEBUG, "Using mrc.cache TOLUD 0x%08x\n", ctrl->pci_tolud_base << 20); + + toludbase = MIN(ctrl->pci_tolud_base, tom - me_uma_size); + } + else + toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, + tom - me_uma_size); gfxstolenbase = toludbase - gfxstolen; gttbase = gfxstolenbase - gttsize; diff --git a/src/northbridge/intel/sandybridge/raminit_memorymap.c b/src/northbridge/intel/sandybridge/raminit_memorymap.c new file mode 100644 index 0000000..7c0bf67 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_memorymap.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <halt.h> +#include <stdint.h> +#include <stddef.h> +#include <northbridge/intel/common/mrc_cache.h> +#include <cbmem.h> +#include <console/console.h> +#include "raminit_private.h" +#include "raminit_memorymap.h" + +/* Store TOLUD base in mrc cache to allow dynamic PCI size changes. + * The caller might request a reboot to apply changes immediately. + */ +void dram_ddr3_set_tolud(u32 base, u8 reboot_now) +{ + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; + + if (!IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)) + return; + + /* try to find timings in MRC cache */ + mrc_cache = cbmem_find(CBMEM_ID_MRCDATA); + if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ramctr_timing))) { + printk(BIOS_ERR, "mrc.cache not found in CBMEM\n"); + return; + } + + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + + /* pci_tolud_base is in MiB */ + ctrl_cached->pci_tolud_base = base >> 20; + + printk(BIOS_INFO, "Writing new TOLUD 0x%08x to mrc.cache\n", base); + + /* update CRC */ + if (!store_current_mrc_cache(ctrl_cached, sizeof(ramctr_timing))) { + printk(BIOS_ERR, "failed to store mrc.cache\n"); + return; + } + + if (reboot_now) { + printk(BIOS_INFO, "Reboot now to apply new TOLUD !\n"); + + /* write mrc cache to flash */ + update_mrc_cache(NULL); + + /* Reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } +} + diff --git a/src/northbridge/intel/sandybridge/raminit_memorymap.h b/src/northbridge/intel/sandybridge/raminit_memorymap.h new file mode 100644 index 0000000..babbc45 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_memorymap.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SANDYBRIDGE_RAMINIT_MEMORYMAP_H +#define SANDYBRIDGE_RAMINIT_MEMORYMAP_H +void dram_ddr3_set_tolud(u32 base, u8 reboot_now); + +#endif diff --git a/src/northbridge/intel/sandybridge/raminit_private.h b/src/northbridge/intel/sandybridge/raminit_private.h new file mode 100644 index 0000000..5168e48 --- /dev/null +++ b/src/northbridge/intel/sandybridge/raminit_private.h @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SANDYBRIDGE_RAMINIT_PRIVATE_H +#define SANDYBRIDGE_RAMINIT_PRIVATE_H + +#include <device/dram/ddr3.h> + +#define NUM_CHANNELS 2 +#define NUM_SLOTRANKS 4 +#define NUM_SLOTS 2 +#define NUM_LANES 8 + +/* FIXME: Vendor BIOS uses 64 but our algorithms are less + performant and even 1 seems to be enough in practice. */ +#define NUM_PATTERNS 4 + +typedef struct odtmap_st { + u16 rttwr; + u16 rttnom; +} odtmap; + +typedef struct dimm_info_st { + dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; +} dimm_info; + +struct ram_rank_timings { + /* Register 4024. One byte per slotrank. */ + u8 val_4024; + /* Register 4028. One nibble per slotrank. */ + u8 val_4028; + + int val_320c; + + struct ram_lane_timings { + /* lane register offset 0x10. */ + u16 timA; /* bits 0 - 5, bits 16 - 18 */ + u8 rising; /* bits 8 - 14 */ + u8 falling; /* bits 20 - 26. */ + + /* lane register offset 0x20. */ + int timC; /* bit 0 - 5, 19. */ + u16 timB; /* bits 8 - 13, 15 - 17. */ + } lanes[NUM_LANES]; +}; + +struct ramctr_timing_st; + +typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; + int mobile; + + u16 cas_supported; + /* tLatencies are in units of ns, scaled by x256 */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; + /* Latencies in terms of clock cycles + * They are saved separately as they are needed for DRAM MRS commands*/ + u8 CAS; /* CAS read latency */ + u8 CWL; /* CAS write latency */ + + u32 tREFI; + u32 tMOD; + u32 tXSOffset; + u32 tWLO; + u32 tCKE; + u32 tXPDLL; + u32 tXP; + u32 tAONPD; + + u16 reg_5064b0; /* bits 0-11. */ + + u8 rankmap[NUM_CHANNELS]; + int ref_card_offset[NUM_CHANNELS]; + u32 mad_dimm[NUM_CHANNELS]; + int channel_size_mb[NUM_CHANNELS]; + u32 cmd_stretch[NUM_CHANNELS]; + + int reg_c14_offset; + int reg_320c_range_threshold; + + int edge_offset[3]; + int timC_offset[3]; + + int extended_temperature_range; + int auto_self_refresh; + + int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; + + struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; + + dimm_info info; + + u32 pci_tolud_base; +} ramctr_timing; + +#endif /* SANDYBRIDGE_RAMINIT_PRIVATE_H */

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coreboot-gerrit June 2016