coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cbfstool: Allow to easily build the individual tools
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 75c37058b3f339b9f9967a50c89b6529ec104df3 Author: Antonello Dettori <dettori.an(a)gmail.com> Date: Sun Jun 5 17:26:01 2016 +0200 cbfstool: Allow to easily build the individual tools Adds a label for each tool included in the cbfstool package in order to build them more easily through Make. Change-Id: Id1e5164240cd12d22cba18d7cc4571fbadad38af Signed-off-by: Antonello Dettori <dettori.an(a)gmail.com> Reviewed-on: https://review.coreboot.org/15075 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15075 for details. -gerrit

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Patch set updated for coreboot: soc/intel/common: Add LPSS I2C driver
by Duncan Laurie 08 Jun '16

08 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15101 -gerrit commit bb923a52ccff6115757a24311a615905868c8a7a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 7 13:40:11 2016 -0700 soc/intel/common: Add LPSS I2C driver Add a generic LPSS I2C driver for Intel SOCs that use the Synopsys DesignWare I2C block and have a similar configuration of that block. This driver is ported from the Chromium depthcharge project where it was ported from U-Boot originally, though it looks very different now. From depthcharge it has been modified to fit into the coreboot I2C driver model with platform_i2c_transfer() and use coreboot semantics throughout including the stopwatch API for timeouts. In order for this shared driver to work the SOC must: 1) Define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ to set the clock speed that the I2C controller core is running at. 2) Define the lpss_i2c_base_address() function to return the base address for the specified bus. This could be either done by looking up the PCI device or a static table if the controllers are not PCI devices and just have a static base address. The driver is usable in verstage/romstage/ramstage, though it does require early initialization of the controller to set a temporary base address if it is used outside of ramstage. This has been tested on Broadwell and Skylake SOCs in both pre-RAM and ramstage environments by reading and writing both single bytes across multiple segments as well as large blocks of data at once and with different configured bus speeds. While it does need specific configuration for each SOC this driver should be able to work on all Intel SOCs currently in src/soc/intel. Change-Id: Ibe492e53c45edb1d1745ec75e1ff66004081717e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/common/Kconfig | 15 ++ src/soc/intel/common/Makefile.inc | 3 + src/soc/intel/common/lpss_i2c.c | 381 ++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/lpss_i2c.h | 41 ++++ 4 files changed, 440 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..cab6b46 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -41,6 +41,21 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE bool default n +config SOC_INTEL_COMMON_LPSS_I2C + bool + default n + help + This driver supports the Intel Low Power Subsystem (LPSS) I2C + controllers that are based on Synopsys DesignWare IP. + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + int + depends on SOC_INTEL_COMMON_LPSS_I2C + help + The clock speed that the I2C controller is running at, in MHz. + No default is set here as this is an SOC-specific value and must + be provided by the SOC when it selects this driver. + config SOC_SETS_MTRRS bool default n diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..0c02a75 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,8 +1,10 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c @@ -10,6 +12,7 @@ romstage-$(CONFIG_MMA) += mma.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c new file mode 100644 index 0000000..40167d1 --- /dev/null +++ b/src/soc/intel/common/lpss_i2c.c @@ -0,0 +1,381 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2009 Vipin Kumar, ST Microelectronics + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <timer.h> +#include "lpss_i2c.h" + +struct lpss_i2c_regs { + uint32_t control; + uint32_t target_addr; + uint32_t slave_addr; + uint32_t master_addr; + uint32_t cmd_data; + uint32_t ss_scl_hcnt; + uint32_t ss_scl_lcnt; + uint32_t fs_scl_hcnt; + uint32_t fs_scl_lcnt; + uint32_t hs_scl_hcnt; + uint32_t hs_scl_lcnt; + uint32_t intr_stat; + uint32_t intr_mask; + uint32_t raw_intr_stat; + uint32_t rx_thresh; + uint32_t tx_thresh; + uint32_t clear_intr; + uint32_t clear_rx_under_intr; + uint32_t clear_rx_over_intr; + uint32_t clear_tx_over_intr; + uint32_t clear_rd_req_intr; + uint32_t clear_tx_abrt_intr; + uint32_t clear_rx_done_intr; + uint32_t clear_activity_intr; + uint32_t clear_stop_det_intr; + uint32_t clear_start_det_intr; + uint32_t clear_gen_call_intr; + uint32_t enable; + uint32_t status; + uint32_t tx_level; + uint32_t rx_level; + uint32_t sda_hold; + uint32_t tx_abort_source; +} __attribute__((packed)); + +/* Use a ~2ms timeout for various operations */ +#define LPSS_I2C_TIMEOUT_US 2000 + +/* High and low times in different speed modes (in ns) */ +enum { + /* Standard Speed */ + MIN_SS_SCL_HIGHTIME = 4000, + MIN_SS_SCL_LOWTIME = 4700, + /* Fast/Fast+ Speed */ + MIN_FS_SCL_HIGHTIME = 600, + MIN_FS_SCL_LOWTIME = 1300, + /* High Speed */ + MIN_HS_SCL_HIGHTIME = 60, + MIN_HS_SCL_LOWTIME = 160, +}; + +/* Control register definitions */ +enum { + CONTROL_MASTER_MODE = (1 << 0), + CONTROL_SPEED_SS = (1 << 1), + CONTROL_SPEED_FS = (1 << 2), + CONTROL_SPEED_HS = (3 << 1), + CONTROL_SPEED_MASK = (3 << 1), + CONTROL_10BIT_SLAVE = (1 << 3), + CONTROL_10BIT_MASTER = (1 << 4), + CONTROL_RESTART_ENABLE = (1 << 5), + CONTROL_SLAVE_DISABLE = (1 << 6), +}; + +/* Command/Data register definitions */ +enum { + CMD_DATA_CMD = (1 << 8), + CMD_DATA_STOP = (1 << 9), +}; + +/* Status register definitions */ +enum { + STATUS_ACTIVITY = (1 << 0), + STATUS_TX_FIFO_NOT_FULL = (1 << 1), + STATUS_TX_FIFO_EMPTY = (1 << 2), + STATUS_RX_FIFO_NOT_EMPTY = (1 << 3), + STATUS_RX_FIFO_FULL = (1 << 4), + STATUS_MASTER_ACTIVITY = (1 << 5), + STATUS_SLAVE_ACTIVITY = (1 << 6), +}; + +/* Enable register definitions */ +enum { + ENABLE_CONTROLLER = (1 << 0), +}; + +/* Interrupt status register definitions */ +enum { + INTR_STAT_RX_UNDER = (1 << 0), + INTR_STAT_RX_OVER = (1 << 1), + INTR_STAT_RX_FULL = (1 << 2), + INTR_STAT_TX_OVER = (1 << 3), + INTR_STAT_TX_EMPTY = (1 << 4), + INTR_STAT_RD_REQ = (1 << 5), + INTR_STAT_TX_ABORT = (1 << 6), + INTR_STAT_RX_DONE = (1 << 7), + INTR_STAT_ACTIVITY = (1 << 8), + INTR_STAT_STOP_DET = (1 << 9), + INTR_STAT_START_DET = (1 << 10), + INTR_STAT_GEN_CALL = (1 << 11), +}; + +/* Enable this I2C controller */ +static void lpss_i2c_enable(struct lpss_i2c_regs *regs) +{ + uint32_t enable = read32(&regs->enable); + + if (!(enable & ENABLE_CONTROLLER)) + write32(&regs->enable, enable | ENABLE_CONTROLLER); +} + +/* Disable this I2C controller */ +static int lpss_i2c_disable(struct lpss_i2c_regs *regs) +{ + uint32_t enable = read32(&regs->enable); + + if (enable & ENABLE_CONTROLLER) { + struct stopwatch sw; + + write32(&regs->enable, enable & ~ENABLE_CONTROLLER); + + /* Wait for enable bit to clear */ + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + while (read32(&regs->enable) & ENABLE_CONTROLLER) + if (stopwatch_expired(&sw)) + return -1; + } + + return 0; +} + +/* Wait for this I2C controller to go idle for transmit */ +static int lpss_i2c_wait_for_bus_idle(struct lpss_i2c_regs *regs) +{ + struct stopwatch sw; + + /* Start timeout for up to 16 bytes in FIFO */ + stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); + + while (!stopwatch_expired(&sw)) { + uint32_t status = read32(&regs->status); + + /* Check for master activity and keep waiting */ + if (status & STATUS_MASTER_ACTIVITY) + continue; + + /* Check for TX FIFO empty to indicate TX idle */ + if (status & STATUS_TX_FIFO_EMPTY) + return 0; + } + + /* Timed out while waiting for bus to go idle */ + return -1; +} + +/* Transfer one byte of one segment, sending stop bit if requested */ +static int lpss_i2c_transfer_byte(struct lpss_i2c_regs *regs, + struct i2c_seg *segment, + size_t byte, int send_stop) +{ + struct stopwatch sw; + uint32_t cmd = CMD_DATA_CMD; /* Read op */ + + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + + if (!segment->read) { + /* Write op only: Wait for FIFO not full */ + while (!(read32(&regs->status) & STATUS_TX_FIFO_NOT_FULL)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C transmit timeout\n"); + return -1; + } + } + cmd = segment->buf[byte]; + } + + /* Send stop on last byte, if desired */ + if (send_stop && byte == segment->len - 1) + cmd |= CMD_DATA_STOP; + + write32(&regs->cmd_data, cmd); + + if (segment->read) { + /* Read op only: Wait for FIFO data and store it */ + while (!(read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C receive timeout\n"); + return -1; + } + } + segment->buf[byte] = read32(&regs->cmd_data); + } + + return 0; +} + +/* Global I2C bus handler, defined in include/i2c.h */ +int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count) +{ + struct stopwatch sw; + struct lpss_i2c_regs *regs; + size_t byte; + + regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); + if (!regs) { + printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); + return -1; + } + + if (!(read32(&regs->enable) & ENABLE_CONTROLLER)) { + printk(BIOS_ERR, "I2C bus %u not initialized\n", bus); + return -1; + } + + if (lpss_i2c_wait_for_bus_idle(regs)) { + printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); + return -1; + } + + /* Process each segment */ + while (count--) { + /* Set target slave address */ + write32(&regs->target_addr, segments->chip); + + /* Read or write each byte in segment */ + for (byte = 0; byte < segments->len; byte++) { + /* + * Set stop condition on final segment only. + * Repeated start will be automatically generated + * by the controller on R->W or W->R switch. + */ + if (lpss_i2c_transfer_byte(regs, segments, byte, + count == 0) < 0) { + printk(BIOS_ERR, "I2C %s failed: bus %u " + "addr 0x%02x\n", segments->read ? + "read" : "write", bus, segments->chip); + return -1; + } + } + segments++; + } + + /* Wait for interrupt status to indicate transfer is complete */ + stopwatch_init_usecs_expire(&sw, LPSS_I2C_TIMEOUT_US); + while (!(read32(&regs->raw_intr_stat) & INTR_STAT_STOP_DET)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C stop bit not received\n"); + return -1; + } + } + + /* Read to clear INTR_STAT_STOP_DET */ + read32(&regs->clear_stop_det_intr); + + /* Wait for the bus to go idle */ + if (lpss_i2c_wait_for_bus_idle(regs)) { + printk(BIOS_ERR, "I2C timeout waiting for bus %u idle\n", bus); + return -1; + } + + /* Flush the RX FIFO in case it is not empty */ + stopwatch_init_usecs_expire(&sw, 16 * LPSS_I2C_TIMEOUT_US); + while (read32(&regs->status) & STATUS_RX_FIFO_NOT_EMPTY) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "I2C timeout flushing RX FIFO\n"); + return -1; + } + read32(&regs->cmd_data); + } + + return 0; +} + +static void lpss_i2c_set_speed(struct lpss_i2c_regs *regs, enum i2c_speed speed) +{ + const int ic_clk = CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ; + uint32_t control, hcnt_min, lcnt_min; + void *hcnt_reg, *lcnt_reg; + + /* Clock must be provided by Kconfig */ + if (!ic_clk || !speed) + return; + + control = read32(&regs->control); + control &= ~CONTROL_SPEED_MASK; + + if (speed >= I2C_SPEED_HIGH) { + /* High Speed */ + control |= CONTROL_SPEED_HS; + hcnt_reg = &regs->hs_scl_hcnt; + lcnt_reg = &regs->hs_scl_lcnt; + hcnt_min = MIN_HS_SCL_HIGHTIME; + lcnt_min = MIN_HS_SCL_LOWTIME; + } else if (speed >= I2C_SPEED_FAST) { + /* Fast Speed */ + control |= CONTROL_SPEED_FS; + hcnt_reg = &regs->fs_scl_hcnt; + lcnt_reg = &regs->fs_scl_lcnt; + hcnt_min = MIN_FS_SCL_HIGHTIME; + lcnt_min = MIN_FS_SCL_LOWTIME; + } else { + /* Standard Speed */ + control |= CONTROL_SPEED_SS; + hcnt_reg = &regs->ss_scl_hcnt; + lcnt_reg = &regs->ss_scl_lcnt; + hcnt_min = MIN_SS_SCL_HIGHTIME; + lcnt_min = MIN_SS_SCL_LOWTIME; + } + + /* Select this speed in the control register */ + write32(&regs->control, control); + + /* SCL count must be set after the speed is selected */ + write32(hcnt_reg, ic_clk * hcnt_min / 1000); + write32(lcnt_reg, ic_clk * lcnt_min / 1000); +} + +void lpss_i2c_init(unsigned bus, enum i2c_speed speed) +{ + struct lpss_i2c_regs *regs; + + regs = (struct lpss_i2c_regs *)lpss_i2c_base_address(bus); + if (!regs) { + printk(BIOS_ERR, "I2C bus %u base address not found\n", bus); + return; + } + + if (lpss_i2c_disable(regs) < 0) { + printk(BIOS_ERR, "I2C timeout disabling bus %u\n", bus); + return; + } + + /* Put controller in master mode with restart enabled */ + write32(&regs->control, CONTROL_MASTER_MODE | CONTROL_SLAVE_DISABLE | + CONTROL_RESTART_ENABLE); + + /* Set bus speed to FAST by default */ + lpss_i2c_set_speed(regs, speed ? : I2C_SPEED_FAST); + + /* Set RX/TX thresholds to smallest values */ + write32(&regs->rx_thresh, 0); + write32(&regs->tx_thresh, 0); + + /* Enable stop detection interrupt */ + write32(&regs->intr_mask, INTR_STAT_STOP_DET); + + lpss_i2c_enable(regs); + + printk(BIOS_INFO, "LPSS I2C bus %u at %p (%u kHz)\n", + bus, regs, speed / 1000); +} + +uintptr_t __attribute__((weak)) lpss_i2c_base_address(unsigned bus) +{ + printk(BIOS_ERR, "%s not implemented for bus %u\n", __func__, bus); + return (uintptr_t)NULL; +} diff --git a/src/soc/intel/common/lpss_i2c.h b/src/soc/intel/common/lpss_i2c.h new file mode 100644 index 0000000..8259414 --- /dev/null +++ b/src/soc/intel/common/lpss_i2c.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_LPSS_I2C_H +#define SOC_INTEL_COMMON_LPSS_I2C_H + +#include <device/i2c.h> +#include <stdint.h> + +/* + * Return the base address for this bus controller. + * + * This function *must* be implemented by the SOC and return the appropriate + * base address for the I2C registers that correspond to the provided bus. + */ +uintptr_t lpss_i2c_base_address(unsigned bus); + +/* + * Initialize this bus controller and set the speed. + * + * The bus speed can be passed in Hz or using values from device/i2c.h and + * will default to I2C_SPEED_FAST if it is not provided. + * + * The SOC *must* define CONFIG_SOC_INTEL_COMMON_LPSS_I2C_CLOCK for the + * bus speed calculation to be correct. + */ +void lpss_i2c_init(unsigned bus, enum i2c_speed speed); + +#endif

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Patch merged into coreboot/master: mainboard/google/reef: Configure sd card pins
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 00f21c77245864b50ec4218cf85d7c73755cb470 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue May 31 14:40:45 2016 -0700 mainboard/google/reef: Configure sd card pins Since the sd card cmd, data, cd lines are configured as native mode, allow the native controller to control the termination. Configure SDCARD_CLK_FB which is used for calibrating the timing of the actual clock buffer. BUG==chrome-os-partner:53747 TEST=verify sd card detection Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578 Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/348377 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/15096 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15096 for details. -gerrit

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Patch set updated for coreboot: buildgcc: Make package build() function more versatile
by Nico Huber 08 Jun '16

08 Jun '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13471 -gerrit commit b620765bf80f5138bcface99d431478618bc24af Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:09:31 2016 +0100 buildgcc: Make package build() function more versatile Refactor build() to make things more flexible: Add a parameter that tells if we build a package for the host or for a target architecture. This is just passed to the build_$package() function and can be used later to take different steps in each case (e.g. for bootstrapping a host gcc). Move .success files into the destination directory. That way we can tell that a package has been built even if the package build directory has been removed. Change-Id: I52a7245714a040d11f6e1ac8bdbff8057bb7f0a1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 50 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1e761da..b650c62 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -296,39 +296,57 @@ package_uses_targetarch() fi } -build() { +generic_build() +{ package=$1 + host_target=$2 + builddir=$3 + success=$4 fn_exists build_$package || return version="$(eval echo \$$package"_VERSION")" - package_uses_targetarch "$package" && \ - BUILDDIR=build-${TARGETARCH}-$package || \ - BUILDDIR=build-$package - mkdir -p ${BUILDDIR} + mkdir -p "$builddir" - is_package_enabled "$package" && \ - if [ -f ${BUILDDIR}/.success ]; then + if [ -f "$success" ]; then printf "Skipping $package as it is already built\n" else printf "Building $package $version ... " - DIR=$PWD - cd ${BUILDDIR} + DIR="$PWD" + cd "$builddir" rm -f .failed - build_${package} > build.log 2>&1 - cd $DIR/${BUILDDIR} - if [ ! -f .failed ]; then touch .success; fi - cd .. - - if [ -r "${BUILDDIR}/.failed" ]; then - printf "${RED}failed${NC}. Check ${BUILDDIR}/build.log.\n" + build_${package} $host_target > build.log 2>&1 + cd "$DIR" + if [ ! -f "$builddir/.failed" ]; then + touch "$success"; + else + printf "${RED}failed${NC}. Check $builddir/build.log.\n" exit 1 fi printf "${green}ok${NC}\n" fi } +build_for_host() +{ + generic_build $1 host build-$1 "${TARGETDIR}/.$1.success" +} + +build_for_target() +{ + generic_build $1 target build-${TARGETARCH}-$1 "${TARGETDIR}/.${TARGETARCH}-$1.success" +} + +build() +{ + if package_uses_targetarch $1; then + build_for_target $1 + else + build_for_host $1 + fi +} + cleanup() { if [ $SAVETEMPS -ne 0 ]; then

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Patch set updated for coreboot: buildgcc: Add option to bootstrap a host gcc
by Nico Huber 08 Jun '16

08 Jun '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit 1afe93291201a2ec92f6d58b43561faf1a42a6dd Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 buildgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. v3: Some library controversy: gcc likes the libraries it ships with most but we don't want to install shared libraries. So we build them static --disable-shared) and install only the minimum (libgcc, libada, libstdc++). However, as the code of these libraries might be used to build a shared library we have to compile them with `-fPIC`. v4: o Updated getopt strings. o The workaround for clang (-fbracket-depth=1024) isn't needed for bootstrapping and also breaks the build, as clang is only used for the first stage in that case and gcc doesn't know that option. So far build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Ubuntu 14.04 "Trusty Tahr" (i386) o Debian 8 "Jessie" (x86_64) (building python (-S) works too) o current Arch Linux (x86_64) o FreeBSD 10.3 (x86_64) (with gcc-aux package) and with clang host compiler, thus C only: `make BUILDGCC_OPTIONS="-b"` on o Debian 8 "Jessie" (x86_64) o FreeBSD 10.3 (x86_64) v5: Rebased after toolchain updates to GCC 5.3.0 etc. Build tested with `make BUILDGCC_OPTIONS="-b -l c,ada"` on o Debian 8 "Jessie" (x86_64) Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 ++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 6 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index b650c62..3791cc9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="April 16th, 2016" -CROSSGCC_VERSION="1.39" +CROSSGCC_DATE="June 7th, 2016" +CROSSGCC_VERSION="1.40" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -30,6 +30,7 @@ LANGUAGES=c DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -341,6 +342,9 @@ build_for_target() build() { if package_uses_targetarch $1; then + if [ $BOOTSTRAP -eq 1 -a ! -f "${TARGETDIR}/.GCC.success" ]; then + build_for_host GCC + fi build_for_target $1 else build_for_host $1 @@ -385,6 +389,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -497,8 +503,35 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } - -build_GCC() { +bootstrap_GCC() { + CC="$CC" \ + CFLAGS="$HOSTCFLAGS" \ + CFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + CXXFLAGS="$HOSTCFLAGS" \ + CXXFLAGS_FOR_BUILD="$HOSTCFLAGS" \ + CXXFLAGS_FOR_TARGET="$HOSTCFLAGS -fPIC" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$TARGETDIR --libexecdir=$TARGETDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-shared --disable-multilib \ + --disable-libssp --disable-libquadmath --disable-libcc1 \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ + --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-pkgversion="coreboot bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS BOOT_CFLAGS="$HOSTCFLAGS" BUILD_CONFIG="" bootstrap && \ + $MAKE install-gcc \ + install-target-libgcc \ + maybe-install-target-libada \ + maybe-install-target-libstdc++-v3 \ + DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$TARGETDIR/bin/cc || touch .failed +} + +build_cross_GCC() { # Work around crazy code generator in GCC that confuses CLANG. $CC --version | grep clang >/dev/null 2>&1 && \ HOSTCFLAGS="$HOSTCFLAGS -fbracket-depth=1024" @@ -536,6 +569,14 @@ build_GCC() { fi } +build_GCC() { + if [ "$1" = host ]; then + bootstrap_GCC + else + build_cross_GCC + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$TARGETDIR || touch .failed @@ -641,11 +682,11 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:p:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") eval set "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:p:l:P:j:D:tSys: $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys: $*) set -- $args fi @@ -661,6 +702,7 @@ while true ; do -c|--clean) shift; clean=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;;

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Patch merged into coreboot/master: lenovo/x60: add hda_verb.c
by gerrit＠coreboot.org 08 Jun '16

08 Jun '16

the following patch was just integrated into master: commit 7d38fafd96b8d7221d294933fb3ef5098f36e29f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jun 3 18:37:38 2016 +0200 lenovo/x60: add hda_verb.c This creates a config for the x60 audio based on values taken from vendor bios. The pin config is stored in (for linux 4.5 at least): /sys/class/sound/card0/hw*/init_pin_configs In the left column there is the pin number. In the right column there is the default configuration of that pin. (This has to be done while running the proprietary bios) More information on the sound card can be found in: /proc/asound/card0/codec#* This also hold the information of /sys/class/sound/ What is improved: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Before this had to be done manually in alsa or pulseaudio. TEST= check if internal microphone is used by default in pavucontrol if you are using pulseaudio. Plug in a jack with headphones and check if there is sound output through these and not the build-in speaker. Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/15063 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15063 for details. -gerrit

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Patch set updated for coreboot: soc/intel/common: Add common code for acpi c/p/t-state entries
by Hannah Williams 07 Jun '16

07 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit e18d75f75c35dd67f90361a15e742aefd68fa793 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/intel/common: Add common code for acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 55 +++++++ src/soc/intel/common/acpi/acpi.c | 297 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 357 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..3e0bed2 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,59 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI) + +/* + * cpu_get_bus_clock returns the bus clock frequency in KHz. + * This is the value the clock ratio is multiplied with. + */ +uint32_t cpu_get_bus_clock(void); + +/* + * cpu_get_coord_type returns coordination type (SW_ANY or SW_ALL or HW_ALL) + * which is used to populate _PSD object. + */ +int cpu_get_coord_type(void); + +/* + * cpu_config_tdp_levels returns the number of TDP levels supported + * by this processor + */ +int cpu_config_tdp_levels(void); + +/* + * cpu_get_min_ratio returns the minimum frequency ratio that is supported + * by this processor + */ +uint32_t cpu_get_min_ratio(void); + +/* + * cpu_get_max_ratio returns the nominal TDP ratio if available or the + * maximum non turbo frequency ratio for this processor + */ +uint32_t cpu_get_max_ratio(void); + +/* + * cpu_get_power_max calculates CPU TDP in mW + */ +uint32_t cpu_get_power_max(void); + +/* + * get_cstate_map returns a table of processor specific acpi_cstate_t entries + * and number of entries in the table + */ +acpi_cstate_t *soc_get_cstate_map(int *num_entries); + +/* + * get_soc_tss_table returns a table of processor specific acpi_tstate_t entries + * and number of entries in the table + */ +acpi_tstate_t *soc_get_tss_table(int *num_entries); + +/* + * soc_get_acpi_base_address returns the acpi base address for the SOC + */ +uint16_t soc_get_acpi_base_address(void); + +#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..3336e63 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return 0; +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock in KHz */ + return CPU_BCLK * 1000; +} + +__attribute__((weak)) uint32_t cpu_get_power_max(void) +{ + msr_t msr; + int power_unit; + + msr = rdmsr(MSR_RAPL_POWER_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_INFO); + return ((msr.lo & 0x7fff) / power_unit) * 1000; +} + +__attribute__((weak)) acpi_cstate_t *soc_get_cstate_map(int *entries) +{ + *entries = 0; + return NULL; +} + +__attribute__((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = 0; + return NULL; +} + +__attribute__((weak)) uint16_t soc_get_acpi_base_address(void) +{ +#define ACPI_BASE_ADDR 0x400 + return (ACPI_BASE_ADDR); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = (ratio_max * cpu_get_bus_clock()) / 1000; + + /* Calculate CPU TDP in mW */ + power_max = cpu_get_power_max(); + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * cpu_get_bus_clock()) / 1000; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = soc_get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = soc_get_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package(entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = soc_get_acpi_base_address(); + int plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores / cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +}

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Patch set updated for coreboot: skylake: gpio: Add support for setting 1.8V tolerant
by Duncan Laurie 07 Jun '16

07 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15103 -gerrit commit b76be46c2dbea466a3233f27903cfb9dc9e12b8b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 6 17:13:42 2016 -0700 skylake: gpio: Add support for setting 1.8V tolerant Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c --- src/mainboard/google/chell/gpio.h | 4 ++-- src/mainboard/google/glados/gpio.h | 4 ++-- src/mainboard/google/lars/gpio.h | 4 ++-- src/mainboard/intel/kunimitsu/gpio.h | 4 ++-- src/soc/intel/skylake/gpio.c | 19 ++++++++++++------- src/soc/intel/skylake/include/soc/gpio.h | 14 ++++++++++---- src/soc/intel/skylake/include/soc/gpio_defs.h | 5 +++++ 7 files changed, 35 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 05897eb..6f30e1e 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -192,8 +192,8 @@ static const struct pad_config gpio_table[] = { /* I2C2_SCL */ PAD_CFG_NC(GPP_F5), /* I2C3_SDA */ PAD_CFG_NC(GPP_F6), /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */ /* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index 5ea6691..8e5e162 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -189,8 +189,8 @@ static const struct pad_config gpio_table[] = { /* I2C2_SCL */ /* GPP_F5 */ /* I2C3_SDA */ /* GPP_F6 */ /* I2C3_SCL */ /* GPP_F7 */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ -/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */ +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */ /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ /* I2C5_SCL */ /* GPP_F11 */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), diff --git a/src/mainboard/google/lars/gpio.h b/src/mainboard/google/lars/gpio.h index e187795..40960a7 100644 --- a/src/mainboard/google/lars/gpio.h +++ b/src/mainboard/google/lars/gpio.h @@ -184,8 +184,8 @@ static const struct pad_config gpio_table[] = { /* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* I2C3_SDA */ /* GPP_F6 */ /* I2C3_SCL */ /* GPP_F7 */ -/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* I2C5_SCL */ PAD_CFG_NC(GPP_F11), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 3d9fcfc..473d9a0 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -193,8 +193,8 @@ static const struct pad_config gpio_table[] = { /* I2C2_SCL */ PAD_CFG_NC(GPP_F5), /* I2C3_SDA */ PAD_CFG_NC(GPP_F6), /* I2C3_SCL */ PAD_CFG_NC(GPP_F7), -/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index a7d8832..78495c6 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -305,9 +305,8 @@ static void gpio_configure_pad(const struct pad_config *cfg) { uint32_t *dw_regs; uint32_t reg; - uint32_t termination; uint32_t dw0; - const uint32_t termination_mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + uint32_t mask; dw_regs = gpio_dw_regs(cfg->pad); @@ -318,10 +317,16 @@ static void gpio_configure_pad(const struct pad_config *cfg) write32(&dw_regs[0], dw0); reg = read32(&dw_regs[1]); - reg &= ~termination_mask; - termination = cfg->attrs; - termination &= termination_mask; - reg |= termination; + + /* Apply termination field */ + mask = PAD_TERM_MASK << PAD_TERM_SHIFT; + reg &= ~mask; + reg |= cfg->attrs & mask; + + /* Apply voltage tolerance field */ + mask = PAD_TOL_MASK << PAD_TOL_SHIFT; + reg &= ~mask; + reg |= cfg->attrs & mask; write32(&dw_regs[1], reg); gpio_handle_pad_mode(cfg); @@ -329,7 +334,7 @@ static void gpio_configure_pad(const struct pad_config *cfg) if ((dw0 & PAD_FIELD(GPIROUTSMI, MASK)) == PAD_FIELD(GPIROUTSMI, YES)) gpi_enable_smi(cfg->pad); - if(gpio_debug) + if (gpio_debug) printk(BIOS_DEBUG, "Write Pad: Base(%p) - conf0 = %x conf1= %x pad # = %d\n", &dw_regs[0], dw0, reg, cfg->pad); diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index f2246e9..6733889 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) +/* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */ +#define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \ + _PAD_CFG_ATTRS(pad_, term_, \ + _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \ + NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8)) + /* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. */ #define PAD_CFG_NC(pad_) \ @@ -149,9 +155,9 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); NO, NO, YES, NO, GPIO, NO, YES), PAD_FIELD(HOSTSW, ACPI)) /* - * The 'attrs' field carries the termination in bits 13:10 to match up with - * thd DW1 pad configuration register. Additionally, other attributes can - * be applied such as the ones below. Bit allocation matters. + * The 'attrs' field carries the termination in bits 13:10 and tolerance in bit + * 25 to match up with thd DW1 pad configuration register. Additionally, other + * attributes can be applied such as the ones below. Bit allocation matters. */ #define HOSTSW_SHIFT 0 #define HOSTSW_MASK 1 @@ -160,7 +166,7 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); struct pad_config { uint16_t pad; - uint16_t attrs; + uint32_t attrs; uint32_t dw0; }; diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 6f9c111..4008dfe 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -495,6 +495,11 @@ #define PAD_TERM_20K_PU 12 #define PAD_TERM_667_PU 13 #define PAD_TERM_NATIVE 15 + /* TOL - voltage tolerance */ +#define PAD_TOL_SHIFT 25 +#define PAD_TOL_MASK 0x1 +#define PAD_TOL_3V3 0 /* 3.3V default */ +#define PAD_TOL_1V8 1 /* 1.8V tolerant */ #define GPI_GPE_STS_OFFSET 0x140 #define GPI_GPE_EN_OFFSET 0x160

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Patch set updated for coreboot: skylake: Move I2C bus configuration to separate structure
by Duncan Laurie 07 Jun '16

07 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15104 -gerrit commit 6c965f0be6b8ed8a5babd80dc28b3cfee25af77c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 6 17:21:00 2016 -0700 skylake: Move I2C bus configuration to separate structure Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e --- src/mainboard/google/chell/devicetree.cb | 5 ++--- src/mainboard/google/glados/devicetree.cb | 5 ++--- src/mainboard/google/lars/devicetree.cb | 3 ++- src/mainboard/intel/kunimitsu/devicetree.cb | 3 ++- src/soc/intel/skylake/chip.c | 5 +++-- src/soc/intel/skylake/chip.h | 16 ++++++++++++++-- 6 files changed, 25 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 428779a..349f724 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" - # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index c4b89af..6518dbf 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -153,6 +153,8 @@ chip soc/intel/skylake register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1 register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2 + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -168,9 +170,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoPci, }" - # I2C4 is 1.8V - register "SerialIoI2cVoltage[4]" = "1" - # PL2 override 15W register "tdp_pl2_override" = "15" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index 5607ec8..fce0495 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -149,7 +149,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 30039d8..b0d95f4 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -153,7 +153,8 @@ chip soc/intel/skylake register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2 register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card) register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board) - register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V + + register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index f990d2b..7bbf336 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -415,8 +415,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; params->SkipMpInit = config->FspSkipMpInit; - memcpy(params->SerialIoI2cVoltage, config->SerialIoI2cVoltage, - sizeof(params->SerialIoI2cVoltage)); + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage; /* * To disable Heci, the Psf needs to be left unlocked diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2db84b7..1d3113f 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -29,6 +29,18 @@ #include <soc/usb.h> #include <soc/vr_config.h> +#define SKYLAKE_I2C_DEV_MAX 6 + +enum skylake_i2c_voltage { + I2C_VOLTAGE_3V3, + I2C_VOLTAGE_1V8 +}; + +struct skylake_i2c_config { + /* Bus voltage level, default is 3.3V */ + enum skylake_i2c_voltage voltage; +}; + struct soc_intel_skylake_config { /* * Interrupt Routing configuration @@ -179,8 +191,8 @@ struct soc_intel_skylake_config { */ u8 SerialIoDevMode[PchSerialIoIndexMax]; - /* I2C voltage select. Value: 0: 3.3V , 1: 1.8V.*/ - u8 SerialIoI2cVoltage[6]; + /* I2C */ + struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX]; /* Camera */ u8 Cio2Enable;

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Patch set updated for coreboot: skylake: Support common LPSS I2C driver
by Duncan Laurie 07 Jun '16

07 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15105 -gerrit commit 33b97762fb8f4d66655699e11261c247259f5fa3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 7 16:40:19 2016 -0700 skylake: Support common LPSS I2C driver Support the common Intel LPSS I2C driver for the 6 I2C bus controllers that are present on the Skylake-LP PCH with a 120 mHz clock. The required lpss_i2c_base_address() method is implemented separately for verstage/romstage and ramstage environments. This provides methods to convert to and from "struct device" and the I2C controller bus number for that device. These are used to provide support for the "I2C Bus Operations" that are present in the coreboot devicetree. To support the I2C controller before ramstage an early init function is provided to do minimal initializaiton of the PCI device and assign a temporary base address for use before memory. The final base address is assigned during device enumeration and used during ramstage. Because it is usually not necessary to enable I2C controllers before ramstage a config register for the devicetree is provided to perform early initialization of this controller. In addition the bus speed can be set in the devicetree and that speed will be applied when the device is initialized. If not provided the default speed is set to I2C_SPEED_FAST. This was tested with the google/chell mainboard by reading and writing from the trackpad and codec devices during both verstage and ramstage. Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/Kconfig | 5 ++ src/soc/intel/skylake/chip.h | 5 ++ src/soc/intel/skylake/i2c.c | 50 +++++++++++++++ src/soc/intel/skylake/include/soc/iomap.h | 3 + src/soc/intel/skylake/include/soc/pci_devs.h | 29 +++++++++ src/soc/intel/skylake/include/soc/romstage.h | 1 + src/soc/intel/skylake/romstage/Makefile.inc | 2 + src/soc/intel/skylake/romstage/i2c.c | 96 ++++++++++++++++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 1 + 9 files changed, 192 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9278cf1..dfa871c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP @@ -72,6 +73,10 @@ config CPU_ADDR_BITS int default 36 +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK + int + default 120 + config DCACHE_RAM_BASE hex "Base address of cache-as-RAM" default 0xfef00000 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1d3113f..caded6c 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -20,6 +20,7 @@ #define _SOC_CHIP_H_ #include <arch/acpi_device.h> +#include <device/i2c.h> #include <stdint.h> #include <soc/gpio_defs.h> #include <soc/gpe.h> @@ -39,6 +40,10 @@ enum skylake_i2c_voltage { struct skylake_i2c_config { /* Bus voltage level, default is 3.3V */ enum skylake_i2c_voltage voltage; + /* Bus speed in Hz, default is I2C_SPEED_FAST (400 kHz) */ + enum i2c_speed speed; + /* Bus should be enabled in verstage with temporary base address */ + int early_init; }; struct soc_intel_skylake_config { diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 76e7bf1..e71113f 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -14,16 +14,66 @@ */ #include <device/device.h> +#include <device/i2c.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/intel/common/lpss_i2c.h> #include <soc/ramstage.h> +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + struct device *dev; + struct resource *res; + + /* bus -> devfn */ + devfn = i2cc_bus_to_devfn(bus); + if (devfn >= 0) { + /* devfn -> dev */ + dev = dev_find_slot(0, devfn); + if (dev) { + /* dev -> bar0 */ + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res) + return res->base; + } + } + + return (uintptr_t)NULL; +} + +static int i2c_dev_to_bus(struct device *dev) +{ + return i2c_devfn_to_bus(dev->path.pci.devfn); +} + +/* + * The device should already be enabled and out of reset, + * either from early init in coreboot or SiliconInit in FSP. + */ +static void i2c_dev_init(struct device *dev) +{ + struct soc_intel_skylake_config *config = dev->chip_info; + int bus = i2c_dev_to_bus(dev); + + if (!config || bus < 0) + return; + + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +static struct i2c_bus_operations i2c_bus_ops = { + .dev_to_bus = &i2c_dev_to_bus, +}; + static struct device_operations i2c_dev_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .scan_bus = &scan_smbus, .ops_pci = &soc_pci_ops, + .ops_i2c_bus = &i2c_bus_ops, + .init = &i2c_dev_init, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index 038fe7d..feba302 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -29,6 +29,9 @@ #define UART_DEBUG_BASE_ADDRESS 0xfe034000 #define UART_DEBUG_BASE_SIZE 0x1000 +#define EARLY_I2C_BASE_ADDRESS 0xfe040000 +#define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x1000 * (x))) + #define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE 0x8000 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 74fd1c5..476e2c6 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -17,6 +17,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <device/pci_def.h> #include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) @@ -147,4 +148,32 @@ #define PCH_DEV_SPI _PCH_DEV(LPC, 5) #define PCH_DEV_GBE _PCH_DEV(LPC, 6) +/* Convert I2C bus number to PCI device and function */ +static inline int i2c_bus_to_devfn(unsigned bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_I2C0; + case 1: return PCH_DEVFN_I2C1; + case 2: return PCH_DEVFN_I2C2; + case 3: return PCH_DEVFN_I2C3; + case 4: return PCH_DEVFN_I2C4; + case 5: return PCH_DEVFN_I2C5; + } + return -1; +} + +/* Convert PCI device and function to I2C bus number */ +static inline int i2c_devfn_to_bus(unsigned devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: return 0; + case PCH_DEVFN_I2C1: return 1; + case PCH_DEVFN_I2C2: return 2; + case PCH_DEVFN_I2C3: return 3; + case PCH_DEVFN_I2C4: return 4; + case PCH_DEVFN_I2C5: return 5; + } + return -1; +} + #endif diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 7fab8ce..56bace1 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,6 +19,7 @@ #include <fsp/romstage.h> +void i2c_early_init(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void); diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 194091f..6ae8137 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,5 @@ verstage-y += cpu.c +verstage-y += i2c.c verstage-y += pch.c verstage-y += power_state.c verstage-y += report_platform.c @@ -9,6 +10,7 @@ verstage-y += systemagent.c verstage-y += uart.c romstage-y += cpu.c +romstage-y += i2c.c romstage-y += pch.c romstage-y += power_state.c romstage-y += report_platform.c diff --git a/src/soc/intel/skylake/romstage/i2c.c b/src/soc/intel/skylake/romstage/i2c.c new file mode 100644 index 0000000..c33e977 --- /dev/null +++ b/src/soc/intel/skylake/romstage/i2c.c @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/i2c.h> +#include <device/pci_def.h> +#include <soc/intel/common/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <soc/serialio.h> +#include "chip.h" + +uintptr_t lpss_i2c_base_address(unsigned bus) +{ + unsigned devfn; + pci_devfn_t dev; + + /* Find device+function for this controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return 0; + + /* Form a PCI address for this device */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + + /* Read the first base address for this device */ + return pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf; +} + +static void i2c_early_init_bus(unsigned bus) +{ + ROMSTAGE_CONST struct soc_intel_skylake_config *config; + ROMSTAGE_CONST struct device *tree_dev; + pci_devfn_t dev; + unsigned devfn; + uintptr_t base; + uint32_t value; + void *reg; + + /* Find the PCI device for this bus controller */ + devfn = i2c_bus_to_devfn(bus); + if (devfn < 0) + return; + + /* Lookup the controller device in the devicetree */ + dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); + tree_dev = dev_find_slot(0, devfn); + if (!tree_dev || !tree_dev->enabled) + return; + + /* Skip if not enabled for early init */ + config = tree_dev->chip_info; + if (!config) + return; + if (!config->i2c[bus].early_init) + return; + + /* Prepare early base address for access before memory */ + base = EARLY_I2C_BASE(bus); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Take device out of reset */ + reg = (void *)(base + SIO_REG_PPR_RESETS); + value = read32(reg); + value |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB | + SIO_REG_PPR_RESETS_IDMA; + write32(reg, value); + + /* Initialize the controller */ + lpss_i2c_init(bus, config->i2c[bus].speed ? : I2C_SPEED_FAST); +} + +void i2c_early_init(void) +{ + int bus; + + /* Go through all I2C controllers to find the enabled ones */ + for (bus = 0; bus < SKYLAKE_I2C_DEV_MAX; bus++) + i2c_early_init_bus(bus); +} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 9c61095..8375ccd 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -64,6 +64,7 @@ void car_soc_post_console_init(void) report_platform_info(); set_max_freq(); pch_early_init(); + i2c_early_init(); } int get_sw_write_protect_state(void)

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coreboot-gerrit June 2016