coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: mainboard/google/reef: Configure sd card pins
by Aaron Durbin 07 Jun '16

07 Jun '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15096 -gerrit commit 19f4f9f705bee931fc9803bd392b35e079ef1aee Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Tue May 31 14:40:45 2016 -0700 mainboard/google/reef: Configure sd card pins Since the sd card cmd, data, cd lines are configured as native mode, allow the native controller to control the termination. Configure SDCARD_CLK_FB which is used for calibrating the timing of the actual clock buffer. BUG==chrome-os-partner:53747 TEST=verify sd card detection Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578 Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/348377 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/gpio.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index c429935..506633b 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -52,14 +52,15 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ /* SDCARD */ - PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ - PAD_CFG_NF(GPIO_173, DN_20K, DEEP, NF1), /* SDCARD_D0 */ - PAD_CFG_NF(GPIO_174, DN_20K, DEEP, NF1), /* SDCARD_D1 */ - PAD_CFG_NF(GPIO_175, DN_20K, DEEP, NF1), /* SDCARD_D2 */ - PAD_CFG_NF(GPIO_176, DN_20K, DEEP, NF1), /* SDCARD_D3 */ - PAD_CFG_NF(GPIO_177, DN_20K, DEEP, NF1), /* SDCARD_CD_N */ - PAD_CFG_NF(GPIO_178, DN_20K, DEEP, NF1), /* SDCARD_CMD */ - PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1), /* SDCARD_LVL_WP */ + PAD_CFG_NF(GPIO_172, NATIVE, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, NATIVE, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, NATIVE, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, NATIVE, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, NATIVE, DEEP, NF1), /* SDCARD_D3 */ + PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, NATIVE, DEEP, NF1), /* SDCARD_CMD */ + PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_NF(GPIO_186, NATIVE, DEEP, NF1), /* SDCARD_LVL_WP */ /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */

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Patch set updated for coreboot: soc/intel/apollolake: Add EMMC DLL API
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084 -gerrit commit bc0044edc1dc981a3a1e33ae4776abf0c0360543 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:01:34 2016 -0700 soc/intel/apollolake: Add EMMC DLL API Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 --- src/soc/intel/apollolake/chip.c | 3 +++ src/soc/intel/apollolake/chip.h | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 17bceec..95f1286 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -115,6 +115,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + if (cfg->emmc_tx_data_cntl1 != 0) + silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; + /* Our defaults may not match FSP defaults, so set them explicitly */ silconfig->AcpiBase = ACPI_PMIO_BASE; /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3d9f5bd..ef82c53 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -40,6 +40,40 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_cmd_cntl; + + /* [14:8] HS400 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_data_cntl1; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_tx_data_cntl2; + + /* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. + * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. + * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_cmd_data_cntl1; + + /* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. + * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_strobe_cntl; + + /* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. + * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. + */ + uint32_t emmc_rx_cmd_data_cntl2; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode;

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit 31333f0581a1c0b5a867b8d4a246a18327046c98 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..8128c71 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -10,6 +10,11 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + # EMMC TX DATA Delay 1# + # 0x1A[14:8] stands for 26*125 = 3250 pSec delay for HS400 + # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit d41b38f8a3e198867032ee2a24c1a357cb7d5c85 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..7f48e0d 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -10,6 +10,11 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + # EMMC TX DATA Delay 1# + # 0x1A[14:8] stands for 26*125 = 3250 psecs delay for HS400 + # 0x1A[6:0] stands for 26*125 = 3250 psecs delay for SDR104/HS200 + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit 23e23a57768350eb1b01004c58e34ee628acbbf2 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..623e1eb 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -9,6 +9,11 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + + # EMMC TX DATA Delay 1# + # 0x1A[14:8] stands for 26*125 = 3250 psecs delay for HS400 + # 0x1A[6:0] stands for 26*125 = 3250 psecs delay for SDR104/HS200 + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required device domain 0 on device pci 00.0 on end # - Host Bridge

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit 666a38897bf0d9651bd09d8c7533f47112aba600 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..5f4c6a8 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/apollolake +6:0chip soc/intel/apollolake device cpu_cluster 0 on device lapic 0 on end @@ -9,6 +9,11 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + + # EMMC TX DATA Delay 1# + # 0x1A[14:8] stands for 26*125 = 3250 psec delay for HS400 + # 0x1A[6:0] stands for 26*125 = 3250 psec delay for SDR104/HS200 + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required device domain 0 on device pci 00.0 on end # - Host Bridge

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Patch set updated for coreboot: soc/intel/apollolake: Add EMMC DLL API
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084 -gerrit commit 4a56c1e144a9b7384866854c929c02802797600b Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:01:34 2016 -0700 soc/intel/apollolake: Add EMMC DLL API Starting from 136_30,FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 --- src/soc/intel/apollolake/chip.c | 3 +++ src/soc/intel/apollolake/chip.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 17bceec..95f1286 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -115,6 +115,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + if (cfg->emmc_tx_data_cntl1 != 0) + silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; + /* Our defaults may not match FSP defaults, so set them explicitly */ silconfig->AcpiBase = ACPI_PMIO_BASE; /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3d9f5bd..a84eba1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -40,6 +40,13 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + uint32_t emmc_tx_cmd_cntl; + uint32_t emmc_tx_data_cntl1; + uint32_t emmc_tx_data_cntl2; + uint32_t emmc_rx_cmd_data_cntl1; + uint32_t emmc_rx_strobe_cntl; + uint32_t emmc_rx_cmd_data_cntl2; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode;

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit 44eb5db2347a10acf86ce68eb219fe33f8869948 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7373 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7586 --- src/mainboard/intel/amenia/devicetree.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..5f4c6a8 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/apollolake +6:0chip soc/intel/apollolake device cpu_cluster 0 on device lapic 0 on end @@ -9,6 +9,11 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + + # EMMC TX DATA Delay 1# + # 0x1A[14:8] stands for 26*125 = 3250 psec delay for HS400 + # 0x1A[6:0] stands for 26*125 = 3250 psec delay for SDR104/HS200 + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required device domain 0 on device pci 00.0 on end # - Host Bridge

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Patch set updated for coreboot: intel/amenia: Program EMMC dll setting
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15092 -gerrit commit 1d3437d2739f398d1fa942dcb1506d9a9be9dc9c Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:26:18 2016 -0700 intel/amenia: Program EMMC dll setting EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7373 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7586 --- src/mainboard/intel/amenia/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index af06848..6b934c4 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -9,6 +9,7 @@ chip soc/intel/apollolake # Integrated Sensor Hub register "integrated_sensor_hub_enable" = "0" + register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required device domain 0 on device pci 00.0 on end # - Host Bridge

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Patch set updated for coreboot: soc/intel/apollolake: Add EMMC DLL API
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084 -gerrit commit b4b6de6b495de74d28b0fab66e94a1b6d3bdca76 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:01:34 2016 -0700 soc/intel/apollolake: Add EMMC DLL API Newer FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 --- src/soc/intel/apollolake/chip.c | 3 +++ src/soc/intel/apollolake/chip.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 17bceec..95f1286 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -115,6 +115,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + if (cfg->emmc_tx_data_cntl1 != 0) + silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; + /* Our defaults may not match FSP defaults, so set them explicitly */ silconfig->AcpiBase = ACPI_PMIO_BASE; /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3d9f5bd..a84eba1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -40,6 +40,13 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + uint32_t emmc_tx_cmd_cntl; + uint32_t emmc_tx_data_cntl1; + uint32_t emmc_tx_data_cntl2; + uint32_t emmc_rx_cmd_data_cntl1; + uint32_t emmc_rx_strobe_cntl; + uint32_t emmc_rx_cmd_data_cntl2; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode;

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coreboot-gerrit June 2016