coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

Patch set updated for coreboot: soc/intel/apollolake: Add EMMC DLL API
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15084 -gerrit commit fea687bea516180e1d290a010588538010fbebdd Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue May 17 19:01:34 2016 -0700 soc/intel/apollolake: Add EMMC DLL API Newer FSP supports to update all the SDIO DLL programming value through silicon init upd. Implement the interface to pass board specific programming value to fsp silicon init. Change-Id: Ifd901148f3f7f89f966217491c661ec346337c38 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7372 Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7585 --- src/soc/intel/apollolake/chip.c | 4 ++++ src/soc/intel/apollolake/chip.h | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 17bceec..286a91d 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -115,6 +115,10 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; + if (cfg->emmc_tx_data_cntl1 != 0) { + silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; + } + /* Our defaults may not match FSP defaults, so set them explicitly */ silconfig->AcpiBase = ACPI_PMIO_BASE; /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3d9f5bd..a84eba1 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -40,6 +40,13 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + uint32_t emmc_tx_cmd_cntl; + uint32_t emmc_tx_data_cntl1; + uint32_t emmc_tx_data_cntl2; + uint32_t emmc_rx_cmd_data_cntl1; + uint32_t emmc_rx_strobe_cntl; + uint32_t emmc_rx_cmd_data_cntl2; + /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode;

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Patch set updated for coreboot: Intel/amenia: Make the device address more readable
by Lijian Zhao 07 Jun '16

07 Jun '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15083 -gerrit commit cfe6e121630ef59d291185bbaf7200abb971dac4 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Mar 16 17:48:06 2016 -0700 Intel/amenia: Make the device address more readable Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/mainboard/intel/amenia/acpi/mainboard.asl | 4 ++-- src/mainboard/intel/amenia/on_board.h | 27 +++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl index 09ef9b4..be6e8b3 100644 --- a/src/mainboard/intel/amenia/acpi/mainboard.asl +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -14,7 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <soc/gpio_defs.h> +#include <on_board.h> Scope (\_SB.PCI0.I2C4) { @@ -48,7 +48,7 @@ Scope (\_SB.PCI0.I2C4) ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - GPIO_18_IRQ + TOUCHPAD_INT } }) diff --git a/src/mainboard/intel/amenia/on_board.h b/src/mainboard/intel/amenia/on_board.h new file mode 100644 index 0000000..ab9bba3 --- /dev/null +++ b/src/mainboard/intel/amenia/on_board.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#ifndef _ON_BOARD_H_ +#define _ON_BOARD_H_ + +#include <soc/gpio_defs.h> + +#define TOUCHPAD_INT GPIO_18_IRQ +#define TOUCHSCREEN_INT GPIO_21_IRQ + + +#endif /* _ON_BOARD_H_ */

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Patch merged into coreboot/master: intel/amenia: Add asl code to enable google ChromeEC
by gerrit＠coreboot.org 07 Jun '16

07 Jun '16

the following patch was just integrated into master: commit f7f1244bc64cc45b732e0fdc1fcb528e45f62e19 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri May 27 01:13:16 2016 -0700 intel/amenia: Add asl code to enable google ChromeEC This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/14987 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/14987 for details. -gerrit

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Patch merged into coreboot/master: google/reef: Add asl code to enable google ChromeEC
by gerrit＠coreboot.org 07 Jun '16

07 Jun '16

the following patch was just integrated into master: commit f6118c62a46b661175130f28d108f610db90ff2a Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri Jun 3 17:11:12 2016 -0700 google/reef: Add asl code to enable google ChromeEC This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/15069 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/15069 for details. -gerrit

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Patch merged into coreboot/master: Kevin/Gru : Update Board ID table.
by gerrit＠coreboot.org 07 Jun '16

07 Jun '16

the following patch was just integrated into master: commit d841da851205be103ad7de10c9604e853d844e55 Author: jongpil19.jung <jongpil19.jung(a)samsung.com> Date: Thu May 19 12:40:00 2016 +0900 Kevin/Gru : Update Board ID table. Add board id table as kevin/gru configuration. BUG=chrome-os-partner:53519 BRANCH=chromeos-2016.02 TEST=check boot on Kevin board. Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43 Original-Signed-off-by: jongpil19.jung <jongpil19.jung(a)samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345736 Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://review.coreboot.org/15028 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15028 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Add missing DRAM density constants
by gerrit＠coreboot.org 07 Jun '16

07 Jun '16

the following patch was just integrated into master: commit e3a8f46c0eb8d563341404f42626b002d74593bb Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 3 07:14:12 2016 -0700 soc/intel/apollolake: Add missing DRAM density constants Add missing constants for DRAM density. This resolves boot issue, because misconfigured density results in incorrect memory mapping. Change-Id: I3bad911bf406bfc5677059490d0e89fcbf735b70 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/15059 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/15059 for details. -gerrit

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Patch set updated for coreboot: Kevin/Gru : Update Board ID table.
by Martin Roth 07 Jun '16

07 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15028 -gerrit commit e94c386353c8a0cd9109ef63695ab77361c79e8b Author: jongpil19.jung <jongpil19.jung(a)samsung.com> Date: Thu May 19 12:40:00 2016 +0900 Kevin/Gru : Update Board ID table. Add board id table as kevin/gru configuration. BUG=chrome-os-partner:53519 BRANCH=chromeos-2016.02 TEST=check boot on Kevin board. Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43 Original-Signed-off-by: jongpil19.jung <jongpil19.jung(a)samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345736 Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/mainboard/google/gru/boardid.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index 5f030ad..1d37a86 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -19,10 +19,11 @@ #include <soc/saradc.h> /* - * This matches two Kevin prototypes, needs to be sorted out with HW engs to - * have more regular mapping between the voltage and board ID. + * This matches Kevin/Gru ADC value for board id. */ -static const int board_id_readings[] = { 42, 120 }; +static const int board_id_readings[] = { 42, 120, 181, 242, 307, 378, 444, + 511, 581, 646, 704, 763, 828, + 895, 956, 1023 }; /* * The ADC produces a 10 bit value, the resistor accuracy is 1%, let's leave

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Patch merged into coreboot/master: rockchip: gru: update the hynix lpddr3 config to run at 928MHz
by gerrit＠coreboot.org 07 Jun '16

07 Jun '16

the following patch was just integrated into master: commit 0d9839b3334d7769e1d89ebc68e01d91e5672c74 Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Wed May 11 15:18:17 2016 +0800 rockchip: gru: update the hynix lpddr3 config to run at 928MHz Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber(a)chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/15027 for details. -gerrit

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New patch to review for coreboot: amd/olivehillplus: Fix PCIe lane number comments.
by Derek Waldner 07 Jun '16

07 Jun '16

Derek Waldner (derek.waldner.os(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15095 -gerrit commit 8e7337a2e34fabe4026a4f72ab8831db0285fe8e Author: Derek Waldner <derek.waldner.os(a)gmail.com> Date: Mon Jun 6 13:54:26 2016 -0500 amd/olivehillplus: Fix PCIe lane number comments. Correct the GPP PCIe lane number comments so that they match the code. Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25 Signed-off-by: Derek Waldner <derek.waldner.os(a)gmail.com> --- src/mainboard/amd/olivehillplus/OemCustomize.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mainboard/amd/olivehillplus/OemCustomize.c b/src/mainboard/amd/olivehillplus/OemCustomize.c index 06a8f3d..ac60c42 100644 --- a/src/mainboard/amd/olivehillplus/OemCustomize.c +++ b/src/mainboard/amd/olivehillplus/OemCustomize.c @@ -18,6 +18,7 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { + /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), @@ -27,7 +28,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x01, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), @@ -37,7 +38,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x02, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), @@ -47,7 +48,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x03, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), @@ -57,7 +58,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),

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Patch set updated for coreboot: intel/amenia: Enable DPTF for intel amenia
by Shaunak Saha 07 Jun '16

07 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15094 -gerrit commit 2222fc01af0596fbeb25674a849cddb8cacb5304 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 00:29:48 2016 -0700 intel/amenia: Enable DPTF for intel amenia This patch enables DPTF support for intel amenia platform.It adds the ASL settings specific to aminia boards. Change-Id: I400e2312a20870058f3a386004fad748d3ee4460 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/intel/amenia/acpi/dptf.asl | 129 +++++++++++++++++++++++++++++++ src/mainboard/intel/amenia/dsdt.asl | 3 + 2 files changed, 132 insertions(+) diff --git a/src/mainboard/intel/amenia/acpi/dptf.asl b/src/mainboard/intel/amenia/acpi/dptf.asl new file mode 100644 index 0000000..bb757eb --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/dptf.asl @@ -0,0 +1,129 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +#ifdef DPTF_ENABLE_FAN_CONTROL +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {100, 0xFFFFFFFF, 4986, 220, 2200}, + Package () {90, 0xFFFFFFFF, 4804, 180, 1800}, + Package () {80, 0xFFFFFFFF, 4512, 145, 1450}, + Package () {70, 0xFFFFFFFF, 4204, 115, 1150}, + Package () {60, 0xFFFFFFFF, 3838, 90, 900}, + Package () {50, 0xFFFFFFFF, 3402, 65, 650}, + Package () {40, 0xFFFFFFFF, 2904, 45, 450}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 90, 80, 70, 60, 0, 0, + 0, 0, 0 + } +}) +#endif + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/apollolake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..9001fb5 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -30,6 +30,9 @@ DefinitionBlock( #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" } /* Mainboard Specific devices */ #include "acpi/mainboard.asl"

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coreboot-gerrit June 2016