coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: WIP: southbridge/intel/bd82x6x: Changes needed for kontron/come-bip2
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14408 -gerrit commit 813071138556619db32fd8d42c4c35cda4649f3a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 18:03:45 2016 -0700 WIP: southbridge/intel/bd82x6x: Changes needed for kontron/come-bip2 This needs further investigation, but without this patch, the Kontron COMe bIP2 dies at random places later on in the code. Change-Id: Ic33fa980d383e02e3851c50d8e53e81576f9f45d Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/intel/bd82x6x/lpc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 1106912..b57a16d 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -367,7 +367,9 @@ static void ppt_pm_init(struct device *dev) RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); RCBA32(0x3a28) = 0x01010000; RCBA32(0x3a2c) = 0x01010404; +#if 0 // FIXME This breaks Kontron's COMe board RCBA32(0x3a80) = 0x01040000; +#endif RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ @@ -411,7 +413,6 @@ static void enable_clock_gating(device_t dev) pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); - reg32 = RCBA32(CG); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); @@ -423,7 +424,9 @@ static void enable_clock_gating(device_t dev) reg32 |= (1 << 23); reg32 &= ~(1 << 20); reg32 |= (1 << 19); +#if 0 // breaks Kontron COMe board reg32 |= (1 << 0); +#endif reg32 |= (0xf << 1); RCBA32(CG) = reg32;

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New patch to review for coreboot: WIP: program to create coreboot GPIO config from inteltool
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14407 -gerrit commit 750cab0e0168940504bca988b98e5683d2ef4790 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 18:03:01 2016 -0700 WIP: program to create coreboot GPIO config from inteltool Change-Id: I03f3ae904c79405d33feb306c5a73ffa7f21730b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/gengpio.c | 170 ++++++++++++++++++++++++++++++ 1 file changed, 170 insertions(+) diff --git a/src/mainboard/kontron/come-bip2/gengpio.c b/src/mainboard/kontron/come-bip2/gengpio.c new file mode 100644 index 0000000..5f25300 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/gengpio.c @@ -0,0 +1,170 @@ +#include <stdio.h> + +typedef unsigned int u32; + +u32 GPIO_USE_SEL=0x3f7fedff; +u32 GPIO_USE_SEL_DIFF=0x86144c00; + +u32 GP_IO_SEL=0x98c82aff; +u32 GP_IO_SEL_DIFF=0x76374400; + +u32 GP_LVL=0xe4c83aff; +u32 GP_LVL_DIFF=0xe6363bff; + +u32 GPI_INV=0x000028f0; +u32 GPI_INV_DIFF=0x000028f0; + + +u32 GPIO_USE_SEL2=0x13ffb6fa; +u32 GPIO_USE_SEL2_DIFF=0x11fcb604; + +u32 GP_IO_SEL2=0x0fcbfff8; +u32 GP_IO_SEL2_DIFF=0x109c000c; + +u32 GP_LVL2=0xb90a0dcc; +u32 GP_LVL2_DIFF=0x1da00dcb; + + +u32 GPIO_USE_SEL3=0x000002fe; +u32 GPIO_USE_SEL3_DIFF=0x000002ce; + +u32 GP_IO_SEL3=0x00000d00; +u32 GP_IO_SEL3_DIFF=0x000002f0; + +u32 GP_LVL3=0x00000731; +u32 GP_LVL3_DIFF=0x000007f1; + +int main(void) +{ + int i; + + printf("/*\n" +" * This file is part of the coreboot project.\n" +" *\n" +" * Copyright (C) 2011 Google Inc.\n" +" *\n" +" * This program is free software; you can redistribute it and/or modify\n" +" * it under the terms of the GNU General Public License as published by\n" +" * the Free Software Foundation; version 2 of the License.\n" +" *\n" +" * This program is distributed in the hope that it will be useful,\n" +" * but WITHOUT ANY WARRANTY; without even the implied warranty of\n" +" * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n" +" * GNU General Public License for more details.\n" +" */\n" +"\n" +"#ifndef BOARD_GPIO_H\n" +"#define BOARD_GPIO_H\n" +"\n" +"#include <southbridge/intel/common/gpio.h>\n" +"\n" +); + + printf("const struct pch_gpio_set1 pch_gpio_set1_mode = {\n"); + for (i=0; i<32; i++) { + if (GPIO_USE_SEL_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i, (GPIO_USE_SEL & (1 << i))?"GPIO_MODE_GPIO":"GPIO_MODE_NATIVE"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set1 pch_gpio_set1_direction = {\n"); + for (i=0; i<32; i++) { + if (GP_IO_SEL_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i, (GP_IO_SEL & (1 << i))?"GPIO_DIR_INPUT":"GPIO_DIR_OUTPUT"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set1 pch_gpio_set1_level = {\n"); + for (i=0; i<32; i++) { + if (GP_LVL_DIFF & (1 << i) && GPIO_USE_SEL & (1 << i)) + printf(" .gpio%d = %s,\n", + i, (GP_LVL & (1 << i))?"GPIO_LEVEL_HIGH":"GPIO_LEVEL_LOW"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set1 pch_gpio_set1_invert = {\n"); + for (i=0; i<32; i++) { + if (GPI_INV_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i, (GPI_INV & (1 << i))?"GPIO_INVERT":"GPIO_???"); + } + printf("};\n\n"); + + + + + printf("const struct pch_gpio_set2 pch_gpio_set2_mode = {\n"); + for (i=0; i<32; i++) { + if (GPIO_USE_SEL2_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i+32, (GPIO_USE_SEL2 & (1 << i))?"GPIO_MODE_GPIO":"GPIO_MODE_NATIVE"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set2 pch_gpio_set2_direction = {\n"); + for (i=0; i<32; i++) { + if (GP_IO_SEL2_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i+32, (GP_IO_SEL2 & (1 << i))?"GPIO_DIR_INPUT":"GPIO_DIR_OUTPUT"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set2 pch_gpio_set2_level = {\n"); + for (i=0; i<32; i++) { + if (GP_LVL2_DIFF & (1 << i) && GPIO_USE_SEL2 & (1 << i)) + printf(" .gpio%d = %s,\n", + i+32, (GP_LVL2 & (1 << i))?"GPIO_LEVEL_HIGH":"GPIO_LEVEL_LOW"); + } + printf("};\n\n"); + + + + printf("const struct pch_gpio_set3 pch_gpio_set3_mode = {\n"); + for (i=0; i<32; i++) { + if (GPIO_USE_SEL3_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i+64, (GPIO_USE_SEL3 & (1 << i))?"GPIO_MODE_GPIO":"GPIO_MODE_NATIVE"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set3 pch_gpio_set3_direction = {\n"); + for (i=0; i<32; i++) { + if (GP_IO_SEL3_DIFF & (1 << i)) + printf(" .gpio%d = %s,\n", + i+64, (GP_IO_SEL3 & (1 << i))?"GPIO_DIR_INPUT":"GPIO_DIR_OUTPUT"); + } + printf("};\n\n"); + + printf("const struct pch_gpio_set3 pch_gpio_set3_level = {\n"); + for (i=0; i<32; i++) { + if (GP_LVL3_DIFF & (1 << i) && GPIO_USE_SEL3 & (1 << i)) + printf(" .gpio%d = %s,\n", + i+64, (GP_LVL3 & (1 << i))?"GPIO_LEVEL_HIGH":"GPIO_LEVEL_LOW"); + } + printf("};\n\n"); + +printf( +"const struct pch_gpio_map mainboard_gpio_map = {\n" +" .set1 = {\n" +" .mode = &pch_gpio_set1_mode,\n" +" .direction = &pch_gpio_set1_direction,\n" +" .level = &pch_gpio_set1_level,\n" +" .invert = &pch_gpio_set1_invert,\n" +" },\n" +" .set2 = {\n" +" .mode = &pch_gpio_set2_mode,\n" +" .direction = &pch_gpio_set2_direction,\n" +" .level = &pch_gpio_set2_level,\n" +" },\n" +" .set3 = {\n" +" .mode = &pch_gpio_set3_mode,\n" +" .direction = &pch_gpio_set3_direction,\n" +" .level = &pch_gpio_set3_level,\n" +" },\n" +"};\n" +"#endif\n"); + + return 0; +}

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New patch to review for coreboot: kontron/come-bip2: Configure device tree correctly
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14406 -gerrit commit 15882ea6e21461068ace3cc74971f4d05b63aae5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 18:01:55 2016 -0700 kontron/come-bip2: Configure device tree correctly Change-Id: I19b3acedebcbf82aa3fd60cd702394099050cd30 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/devicetree.cb | 99 ++++++++++++++++----------- 1 file changed, 58 insertions(+), 41 deletions(-) diff --git a/src/mainboard/kontron/come-bip2/devicetree.cb b/src/mainboard/kontron/come-bip2/devicetree.cb index 437b3cb..5e4e6b6 100644 --- a/src/mainboard/kontron/come-bip2/devicetree.cb +++ b/src/mainboard/kontron/come-bip2/devicetree.cb @@ -1,24 +1,7 @@ chip northbridge/intel/sandybridge # IGD Displays - register "gfx.ndid" = "1" - register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as eDP and configure power delays - register "gpu_panel_port_select" = "1" # eDP_A - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" - - register "max_mem_clock_mhz" = "666" + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 @@ -39,8 +22,8 @@ chip northbridge/intel/sandybridge end device domain 0 on - subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge + device pci 01.0 on end # PCIe Bridge x16 device pci 02.0 on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH @@ -48,19 +31,18 @@ chip northbridge/intel/sandybridge # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0100" + register "alt_gp_smi_en" = "0x0000" register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "sata_port_map" = "0x1" - + # Enable all SATA ports 0-5 + register "sata_port_map" = "0x3f" register "sata_port0_gen3_tx" = "0x00880a7f" - # EC range is 0x800-0x9ff # Please note: you MUST not change this unless # you also change romstage.c:pch_enable_lpc - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" + register "gen1_dec" = "0x00040291" + register "gen2_dec" = "0x007c0a81" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" @@ -68,31 +50,66 @@ chip northbridge/intel/sandybridge register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" + device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet + device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) - device pci 1c.1 off end # PCIe Port #2 + device pci 1c.0 on end # PCIe Port #1 (WLAN remapped) + device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on end # PCIe Port #3 (WLAN actual) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge + device pci 1e.0 on end # PCI bridge device pci 1f.0 on - chip ec/google/chromeec - # We only have one init function that - # we need to call to initialize the - # keyboard part of the EC. - device pnp ff.1 on # dummy address + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + end + device pnp 2e.1 off # Parallel Port + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST end - end + end # superio/winbond/w83627dhg end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on end # SMBus

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New patch to review for coreboot: kontron/come-bip2: Fix GPIO settings
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14405 -gerrit commit 615fdcede1f4e38e6c217657f8150f83f7f715b2 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 18:00:04 2016 -0700 kontron/come-bip2: Fix GPIO settings These are the GPIO settings for the Kontron comE bIP2 board as provided by inteltool run on the vendor BIOS. Change-Id: Ib0385a0922acb5fd6c73cc960dc3b4435b814634 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/gpio.c | 132 +++++++++++++++++++++------------ 1 file changed, 86 insertions(+), 46 deletions(-) diff --git a/src/mainboard/kontron/come-bip2/gpio.c b/src/mainboard/kontron/come-bip2/gpio.c index dcd29a3..3ee8456 100644 --- a/src/mainboard/kontron/come-bip2/gpio.c +++ b/src/mainboard/kontron/come-bip2/gpio.c @@ -13,89 +13,129 @@ * GNU General Public License for more details. */ -#ifndef LINK_GPIO_H -#define LINK_GPIO_H +#ifndef BOARD_GPIO_H +#define BOARD_GPIO_H #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { - .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ - .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ - .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ - .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ - .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ - .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ - .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ - .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ - .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ - .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ - .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ - .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ - .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ - .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, }; const struct pch_gpio_set1 pch_gpio_set1_direction = { - .gpio0 = GPIO_DIR_INPUT, - .gpio3 = GPIO_DIR_INPUT, - .gpio5 = GPIO_DIR_INPUT, - .gpio7 = GPIO_DIR_INPUT, - .gpio8 = GPIO_DIR_INPUT, - .gpio9 = GPIO_DIR_INPUT, - .gpio10 = GPIO_DIR_INPUT, - .gpio11 = GPIO_DIR_INPUT, - .gpio12 = GPIO_DIR_INPUT, - .gpio14 = GPIO_DIR_INPUT, - .gpio15 = GPIO_DIR_INPUT, - .gpio21 = GPIO_DIR_INPUT, - .gpio24 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, }; const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, .gpio6 = GPIO_LEVEL_HIGH, - .gpio24 = GPIO_LEVEL_LOW, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_LOW, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, }; const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, .gpio7 = GPIO_INVERT, - .gpio8 = GPIO_INVERT, - .gpio12 = GPIO_INVERT, - .gpio14 = GPIO_INVERT, - .gpio15 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, }; const struct pch_gpio_set2 pch_gpio_set2_mode = { - .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ - .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ - .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ - .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ - .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ - .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ + .gpio34 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, }; const struct pch_gpio_set2 pch_gpio_set2_direction = { - .gpio36 = GPIO_DIR_OUTPUT, - .gpio41 = GPIO_DIR_INPUT, - .gpio42 = GPIO_DIR_INPUT, - .gpio43 = GPIO_DIR_INPUT, - .gpio57 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_INPUT, .gpio60 = GPIO_DIR_OUTPUT, }; const struct pch_gpio_set2 pch_gpio_set2_level = { - .gpio36 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_HIGH, .gpio60 = GPIO_LEVEL_HIGH, }; const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, }; const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio73 = GPIO_DIR_OUTPUT, }; const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_HIGH, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio73 = GPIO_LEVEL_HIGH, }; const struct pch_gpio_map mainboard_gpio_map = {

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New patch to review for coreboot: kontron/come-bip2: Expose HWM in ACPI
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14404 -gerrit commit 92d3ea153ab37dfb66c988c79431c1180d48c181 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 17:59:25 2016 -0700 kontron/come-bip2: Expose HWM in ACPI Change-Id: I4801795786373f4e9d1b1179ad3cefb563cafdf5 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/acpi/superio.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/kontron/come-bip2/acpi/superio.asl b/src/mainboard/kontron/come-bip2/acpi/superio.asl index c3ad655..1153c04 100644 --- a/src/mainboard/kontron/come-bip2/acpi/superio.asl +++ b/src/mainboard/kontron/come-bip2/acpi/superio.asl @@ -15,10 +15,12 @@ #define SUPERIO_DEV SIO0 #define SUPERIO_PNP_BASE 0x2e + #define W83627DHG_SHOW_UARTA // UARTA will be exposed #define W83627DHG_SHOW_UARTB #define W83627DHG_SHOW_KBC // #define W83627DHG_SHOW_PS2M +#define W83627DHG_SHOW_HWMON /* ACPI code for SuperIO functions */ #include <superio/winbond/w83627dhg/acpi/superio.asl>

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New patch to review for coreboot: kontron/come-bip2: Add initial CPLD support
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14403 -gerrit commit 40b037b78d6394db34e740a91cf0a9f689262ced Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Apr 18 17:56:43 2016 -0700 kontron/come-bip2: Add initial CPLD support This adds support for talking to the Kontron CPLD. Right now, the only supported function is to dump the CPLD's registers. Change-Id: I2721346e2dadc0f30795f395902994773e730bbf Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/Makefile.inc | 1 + src/mainboard/kontron/come-bip2/cpld.c | 74 ++++++++++++++++++++++++++++ src/mainboard/kontron/come-bip2/cpld.h | 29 +++++++++++ src/mainboard/kontron/come-bip2/romstage.c | 4 ++ 4 files changed, 108 insertions(+) diff --git a/src/mainboard/kontron/come-bip2/Makefile.inc b/src/mainboard/kontron/come-bip2/Makefile.inc index 5aaf562..413cc80 100644 --- a/src/mainboard/kontron/come-bip2/Makefile.inc +++ b/src/mainboard/kontron/come-bip2/Makefile.inc @@ -20,3 +20,4 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c romstage-y += gpio.c +romstage-y += cpld.c diff --git a/src/mainboard/kontron/come-bip2/cpld.c b/src/mainboard/kontron/come-bip2/cpld.c new file mode 100644 index 0000000..d7b8453 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/cpld.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <lib.h> +#include <arch/io.h> +#include <console/console.h> +#include "cpld.h" + +#define CPLD_IDX 0xa80 +#define CPLD_DATA 0xa81 + +u8 cpld_read8(u8 idx) +{ + outb(idx, CPLD_IDX); + return inb(CPLD_DATA); +} + +u16 cpld_read16(u8 idx) +{ + return cpld_read8(idx) | (cpld_read8(idx + 1) << 8); +} + +u32 cpld_read32(u8 idx) +{ + return cpld_read16(idx) | (cpld_read16(idx + 2) << 16); +} + +void cpld_write8(u8 idx, u8 value) +{ + outb(idx, CPLD_IDX); + outb(value, CPLD_DATA); +} + +void cpld_write16(u8 idx, u16 value) +{ + cpld_write8(idx, (u8)value); + cpld_write8(idx + 1, (u8)(value >> 8)); +} + +void cpld_write32(u8 idx, u32 value) +{ + cpld_write16(idx, (u16)value); + cpld_write16(idx + 2, (u16)(value >> 16)); +} + +void cpld_dump(void) +{ + u8 data[256]; + int i; + + for (i = 0; i <= 0xff; i++) + data[i] = cpld_read8(i); + + printk(BIOS_DEBUG, "CPLD registers:\n"); + hexdump(data, 256); + printk(BIOS_DEBUG, "\n\n"); + + cpld_write8(0x08, 0x00); +} + + diff --git a/src/mainboard/kontron/come-bip2/cpld.h b/src/mainboard/kontron/come-bip2/cpld.h new file mode 100644 index 0000000..6e8ae4a --- /dev/null +++ b/src/mainboard/kontron/come-bip2/cpld.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CPLD_H__ +#define __CPLD_H__ + +#include <stdint.h> + +u8 cpld_read8(u8 idx); +u16 cpld_read16(u8 idx); +u32 cpld_read32(u8 idx); +void cpld_write8(u8 idx, u8 value); +void cpld_write16(u8 idx, u16 value); +void cpld_write32(u8 idx, u32 value); +void cpld_dump(void); + +#endif diff --git a/src/mainboard/kontron/come-bip2/romstage.c b/src/mainboard/kontron/come-bip2/romstage.c index fcdeb3c..84fc4b9 100644 --- a/src/mainboard/kontron/come-bip2/romstage.c +++ b/src/mainboard/kontron/come-bip2/romstage.c @@ -37,6 +37,7 @@ #include <halt.h> #include <tpm.h> #include <cbfs.h> +#include "cpld.h" #include <southbridge/intel/bd82x6x/chip.h> @@ -170,6 +171,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; + + // + cpld_dump(); } const struct southbridge_usb_port mainboard_usb_ports[] = {

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New patch to review for coreboot: COMe-bIP2: Update board_info.txt
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14402 -gerrit commit 6b8741763edd0a21bab263f26be896a21753da81 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Mar 21 22:54:24 2016 -0700 COMe-bIP2: Update board_info.txt Change-Id: I577c3610ad2656380216dac1682a469c5a9431b2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/board_info.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/kontron/come-bip2/board_info.txt b/src/mainboard/kontron/come-bip2/board_info.txt index f8aa153..c519bab 100644 --- a/src/mainboard/kontron/come-bip2/board_info.txt +++ b/src/mainboard/kontron/come-bip2/board_info.txt @@ -1,6 +1,6 @@ -Board name: Chromebook Pixel -Category: laptop -Board URL: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel +Board name: Kontron COMe-bIP2 +Category: COMe +Board URL: http://www.kontron.com ROM package: SOIC-8 ROM protocol: SPI ROM socketed: n

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New patch to review for coreboot: COMe-bIP2: Initial take at getting the board to compile
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14401 -gerrit commit 6e0e5a91d1e5fce89eb0085b7a64a13ff94ca757 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Mar 21 22:53:14 2016 -0700 COMe-bIP2: Initial take at getting the board to compile Change-Id: Ib66dd38993b70b3114ae52a1a186f28122994e43 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/Kconfig | 22 ++--- src/mainboard/kontron/come-bip2/Kconfig.name | 4 +- src/mainboard/kontron/come-bip2/Makefile.inc | 23 ----- src/mainboard/kontron/come-bip2/acpi/ec.asl | 9 +- src/mainboard/kontron/come-bip2/acpi/mainboard.asl | 62 ------------ src/mainboard/kontron/come-bip2/acpi/platform.asl | 14 --- src/mainboard/kontron/come-bip2/acpi/superio.asl | 17 ++-- src/mainboard/kontron/come-bip2/acpi/thermal.asl | 31 +----- src/mainboard/kontron/come-bip2/acpi_tables.c | 6 -- src/mainboard/kontron/come-bip2/chromeos.c | 109 --------------------- src/mainboard/kontron/come-bip2/chromeos.fmd | 38 ------- src/mainboard/kontron/come-bip2/dsdt.asl | 3 - src/mainboard/kontron/come-bip2/ec.c | 47 --------- src/mainboard/kontron/come-bip2/ec.h | 58 ----------- .../kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/mainboard.c | 56 ++--------- src/mainboard/kontron/come-bip2/mainboard_smi.c | 70 ------------- .../come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/onboard.h | 32 ------ src/mainboard/kontron/come-bip2/romstage.c | 43 ++------ .../come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex | 32 ------ src/mainboard/kontron/come-bip2/thermal.h | 4 +- 22 files changed, 35 insertions(+), 709 deletions(-) diff --git a/src/mainboard/kontron/come-bip2/Kconfig b/src/mainboard/kontron/come-bip2/Kconfig index e61bba0..bd77158 100644 --- a/src/mainboard/kontron/come-bip2/Kconfig +++ b/src/mainboard/kontron/come-bip2/Kconfig @@ -1,4 +1,4 @@ -if BOARD_GOOGLE_LINK +if BOARD_KONTRON_COME_BIP2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -7,30 +7,24 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_IVYBRIDGE select SOUTHBRIDGE_INTEL_C216 select BOARD_ROMSIZE_KB_8192 - select EC_GOOGLE_CHROMEEC + select SUPERIO_WINBOND_W83627DHG select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT -config CHROMEOS - select CHROMEOS_VBNV_CMOS - select LID_SWITCH - config MAINBOARD_DIR string - default google/link + default kontron/come-bip2 config MAINBOARD_PART_NUMBER string - default "Link" + default "COMe-bIP2" config MMCONF_BASE_ADDRESS hex - default 0xf8000000 + default 0xf0000000 config MAX_CPUS int @@ -40,8 +34,4 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config GBB_HWID - string - depends on CHROMEOS - default "X86 LINK TEST 6638" -endif # BOARD_GOOGLE_LINK +endif # BOARD_KONTRON_COME_BIP2 diff --git a/src/mainboard/kontron/come-bip2/Kconfig.name b/src/mainboard/kontron/come-bip2/Kconfig.name index 289164b..5d4917b 100644 --- a/src/mainboard/kontron/come-bip2/Kconfig.name +++ b/src/mainboard/kontron/come-bip2/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_GOOGLE_LINK - bool "Link" +config BOARD_KONTRON_COME_BIP2 + bool "COMe-bIP2" diff --git a/src/mainboard/kontron/come-bip2/Makefile.inc b/src/mainboard/kontron/come-bip2/Makefile.inc index b79e4d3..5aaf562 100644 --- a/src/mainboard/kontron/come-bip2/Makefile.inc +++ b/src/mainboard/kontron/come-bip2/Makefile.inc @@ -13,33 +13,10 @@ ## GNU General Public License for more details. ## -ramstage-y += ec.c - -romstage-y += chromeos.c -ramstage-y += chromeos.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -SPD_SOURCES = elpida_4Gb_1600_x16 -SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 -SPD_SOURCES += micron_4Gb_1600_1.35v_x16 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd romstage-y += gpio.c diff --git a/src/mainboard/kontron/come-bip2/acpi/ec.asl b/src/mainboard/kontron/come-bip2/acpi/ec.asl index 2e898ed..b5b8e2b 100644 --- a/src/mainboard/kontron/come-bip2/acpi/ec.asl +++ b/src/mainboard/kontron/come-bip2/acpi/ec.asl @@ -13,11 +13,4 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "../ec.h" - -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - -/* ACPI code for EC functions */ -#include <ec/google/chromeec/acpi/ec.asl> +/* NONE */ diff --git a/src/mainboard/kontron/come-bip2/acpi/mainboard.asl b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl index 01e99fa..817c2a8 100644 --- a/src/mainboard/kontron/come-bip2/acpi/mainboard.asl +++ b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl @@ -14,71 +14,9 @@ * GNU General Public License for more details. */ -#include <mainboard/google/link/onboard.h> - Scope (\_SB) { - Device (LID0) - { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) - { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) - } - - // EC_LID_OUT is GPIO15 - Name(_PRW, Package(){0x1f, 0x05}) - } - Device (PWRB) { Name(_HID, EisaId("PNP0C0C")) } - - Device (TPAD) - { - Name (_ADR, 0x0) - Name (_UID, 1) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) - - // Trackpad Wake is GPIO12 - Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) - - Name(_CRS, ResourceTemplate() - { - // PIRQE -> GSI20 - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } - - // SMBUS Address 0x4b - VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } - }) - } - - Device (TSCR) - { - Name (_ADR, 0x0) - Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name(_HID, EisaId("PNP0C0E")) - - // Touchscreen Wake is GPIO14 - Name(_PRW, Package(){0x1e, 0x03}) - - Name(_CRS, ResourceTemplate() - { - // PIRQG -> GSI22 - Interrupt (ResourceConsumer, Edge, ActiveLow) {22} - - // SMBUS Address 0x4a - VendorShort (ADDR) {0x4a} - }) - } } diff --git a/src/mainboard/kontron/come-bip2/acpi/platform.asl b/src/mainboard/kontron/come-bip2/acpi/platform.asl index c84736a..3639db7 100644 --- a/src/mainboard/kontron/come-bip2/acpi/platform.asl +++ b/src/mainboard/kontron/come-bip2/acpi/platform.asl @@ -27,19 +27,5 @@ Method(_PTS,1) Method(_WAK,1) { - /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) - Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) - } - - /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) - Notify (\_SB.LID0, 0x80) - } - Return(Package(){0,0}) } diff --git a/src/mainboard/kontron/come-bip2/acpi/superio.asl b/src/mainboard/kontron/come-bip2/acpi/superio.asl index 266a67c..c3ad655 100644 --- a/src/mainboard/kontron/come-bip2/acpi/superio.asl +++ b/src/mainboard/kontron/come-bip2/acpi/superio.asl @@ -13,13 +13,12 @@ * GNU General Public License for more details. */ -/* mainboard configuration */ -#include "../ec.h" +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define W83627DHG_SHOW_UARTA // UARTA will be exposed +#define W83627DHG_SHOW_UARTB +#define W83627DHG_SHOW_KBC // +#define W83627DHG_SHOW_PS2M -#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources -#define SIO_EC_HOST_ENABLE // EC Host Interface Resources -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 - -/* ACPI code for EC SuperIO functions */ -#include "../../../../ec/google/chromeec/acpi/superio.asl" +/* ACPI code for SuperIO functions */ +#include <superio/winbond/w83627dhg/acpi/superio.asl> diff --git a/src/mainboard/kontron/come-bip2/acpi/thermal.asl b/src/mainboard/kontron/come-bip2/acpi/thermal.asl index 9163493..8c084bf 100644 --- a/src/mainboard/kontron/come-bip2/acpi/thermal.asl +++ b/src/mainboard/kontron/come-bip2/acpi/thermal.asl @@ -14,7 +14,7 @@ */ // Thermal Zone - +#if 0 Scope (\_TZ) { ThermalZone (CRIT) @@ -41,34 +41,8 @@ Scope (\_TZ) Method (_TMP, 0, Serialized) { - // Get CPU Temperature from TIN9/PECI via EC - Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) - - // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { - Return (CTOK(0)) - } - - // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { - Return (CTOK(0)) - } - - // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { - Return (CTOK(0)) - } - - // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { - Return (CTOK(0)) - } - - // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + // TODO: Get CPU Temperature from TIN9/PECI via SuperIO - // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) Return (Local0) } } @@ -217,3 +191,4 @@ Scope (\_TZ) } } } +#endif diff --git a/src/mainboard/kontron/come-bip2/acpi_tables.c b/src/mainboard/kontron/come-bip2/acpi_tables.c index a7f2c50..16e9be9 100644 --- a/src/mainboard/kontron/come-bip2/acpi_tables.c +++ b/src/mainboard/kontron/come-bip2/acpi_tables.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <vendorcode/google/chromeos/gnvs.h> -#include <ec/google/chromeec/ec.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> @@ -60,11 +59,6 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->s5u0 = 0; gnvs->s5u1 = 0; -#if CONFIG_CHROMEOS - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; -#endif - acpi_update_thermal_table(gnvs); // the lid is open by default. diff --git a/src/mainboard/kontron/come-bip2/chromeos.c b/src/mainboard/kontron/come-bip2/chromeos.c deleted file mode 100644 index d07e851..0000000 --- a/src/mainboard/kontron/come-bip2/chromeos.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <bootmode.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/pci.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> -#include "ec.h" -#include <ec/google/chromeec/ec.h> - -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - -#define GPIO_COUNT 6 - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - /* Write Protect: GPIO57 = PCH_SPI_WP_D */ - gpios->gpios[0].port = 57; - gpios->gpios[0].polarity = ACTIVE_HIGH; - gpios->gpios[0].value = get_write_protect_state(); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); - /* Recovery: the "switch" comes from the EC */ - gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - - /* Lid: the "switch" comes from the EC */ - gpios->gpios[2].port = -1; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = get_lid_switch(); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); - - /* Power Button: hard-coded as not pressed; we'll detect later presses - * via SMI. */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_HIGH; - gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); - - /* Developer: a tricky case on Link, there is no switch */ - gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = get_developer_mode_switch(); - strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH); - - /* Did we load the VGA Option ROM? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = gfx_get_init_done(); - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); -} -#endif - -int get_write_protect_state(void) -{ - return get_gpio(57); -} - -int get_lid_switch(void) -{ - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - - return !!(ec_switches & EC_SWITCH_LID_OPEN); -} - -/* The dev-switch is virtual on Link (and so handled elsewhere). */ -int get_developer_mode_switch(void) -{ - return 0; -} - -/* There are actually two recovery switches. One is the magic keyboard chord, - * the other is driven by Servo. */ -int get_recovery_mode_switch(void) -{ - u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); - u32 ec_events; - - /* If a switch is set, we don't need to look at events. */ - if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) - return 1; - - /* Else check if the EC has posted the keyboard recovery event. */ - ec_events = google_chromeec_get_events_b(); - - return !!(ec_events & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); -} diff --git a/src/mainboard/kontron/come-bip2/chromeos.fmd b/src/mainboard/kontron/come-bip2/chromeos.fmd deleted file mode 100644 index 21b39c0..0000000 --- a/src/mainboard/kontron/come-bip2/chromeos.fmd +++ /dev/null @@ -1,38 +0,0 @@ -FLASH@0xff800000 0x800000 { - SI_ALL@0x0 0x200000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0x200000 0x600000 { - RW_SECTION_A@0x0 0xf0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xdffc0 - RW_FWID_A@0xeffc0 0x40 - } - RW_SECTION_B@0xf0000 0xf0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xdffc0 - RW_FWID_B@0xeffc0 0x40 - } - RW_MRC_CACHE@0x1e0000 0x10000 - RW_ELOG@0x1f0000 0x4000 - RW_SHARED@0x1f4000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x1f8000 0x2000 - RW_UNUSED@0x1fa000 0x6000 - RW_LEGACY@0x200000 0x200000 - WP_RO@0x400000 0x200000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 - } - } - } -} diff --git a/src/mainboard/kontron/come-bip2/dsdt.asl b/src/mainboard/kontron/come-bip2/dsdt.asl index be6a412..5aad74c 100644 --- a/src/mainboard/kontron/come-bip2/dsdt.asl +++ b/src/mainboard/kontron/come-bip2/dsdt.asl @@ -50,9 +50,6 @@ DefinitionBlock( } } - #include "acpi/chromeos.asl" - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/kontron/come-bip2/ec.c b/src/mainboard/kontron/come-bip2/ec.c deleted file mode 100644 index acf1185..0000000 --- a/src/mainboard/kontron/come-bip2/ec.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> -#include <types.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -void link_ec_init(void) -{ - printk(BIOS_DEBUG, "link_ec_init\n"); - post_code(0xf0); - - /* Restore SCI event mask on resume. */ - if (acpi_is_wakeup_s3()) { - google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S3_WAKE_EVENTS); - - /* Disable SMI and wake events */ - google_chromeec_set_smi_mask(0); - - /* Clear pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); - } else { - google_chromeec_log_events(LINK_EC_LOG_EVENTS | - LINK_EC_S5_WAKE_EVENTS); - } - - /* Clear wake events, these are enabled on entry to sleep */ - google_chromeec_set_wake_mask(0); - - post_code(0xf1); -} diff --git a/src/mainboard/kontron/come-bip2/ec.h b/src/mainboard/kontron/come-bip2/ec.h deleted file mode 100644 index af06772..0000000 --- a/src/mainboard/kontron/come-bip2/ec.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_EC_H -#define LINK_EC_H - -#include <ec/google/chromeec/ec_commands.h> - -#define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */ -#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ - -#define LINK_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) - -#define LINK_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define LINK_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* EC can wake from S3 with lid or power button or key press */ -#define LINK_EC_S3_WAKE_EVENTS \ - (LINK_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) - -/* Log EC wake events plus EC shutdown events */ -#define LINK_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) - -#ifndef __ACPI__ -extern void link_ec_init(void); -#endif - -#endif // LINK_EC_H diff --git a/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex deleted file mode 100644 index ef36c39..0000000 --- a/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 10 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 81 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 42 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 02 fe 00 -11 52 00 00 00 07 7f 37 -45 42 4a 32 30 55 47 36 -45 42 55 30 2d 47 4e 2d -46 20 30 20 02 fe 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/mainboard.c b/src/mainboard/kontron/come-bip2/mainboard.c index 922061f..e1e4a7c 100644 --- a/src/mainboard/kontron/come-bip2/mainboard.c +++ b/src/mainboard/kontron/come-bip2/mainboard.c @@ -29,27 +29,10 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include "onboard.h" -#include "ec.h" #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <smbios.h> #include <device/pci.h> -#include <ec/google/chromeec/ec.h> - -/* placeholder for evenual link post. Not sure what we'll - * do but it will look nice - */ -void mainboard_post(u8 value) -{ - /* - * What you DO NOT want to do: push every post to the EC backlight. - * it seems cute but in practice it looks like a hardware failure. - * I'm leaving this here so we don't make this mistake again later. - * And it seems to break the SMP startup. - * google_chromeec_post(value); - */ -} #if CONFIG_VGA_ROM_RUN static int int15_handler(void) @@ -142,25 +125,16 @@ static int int15_handler(void) static void mainboard_init(device_t dev) { - /* Initialize the Embedded Controller */ - link_ec_init(); - - if (google_chromeec_get_board_version() == 0) { - /* If running on proto1 - enable reversion of gpio11. */ - u32 gpio_inv; - u16 gpio_base = pci_read_config16 - (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & - 0xfffc; - u16 gpio_inv_addr = gpio_base + GPI_INV; - gpio_inv = inl(gpio_inv_addr); - outl(gpio_inv | (1 << 11), gpio_inv_addr); - } + /* TBD */ } -static int link_onboard_smbios_data(device_t dev, int *handle, +static int onboard_smbios_data(device_t dev, int *handle, unsigned long *current) { int len = 0; +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 0 len += smbios_write_type41( current, handle, @@ -171,24 +145,6 @@ static int link_onboard_smbios_data(device_t dev, int *handle, 0, /* device */ 0); /* function */ - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - 0, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - 0, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - 0, /* device */ - 0); /* function */ - return len; } @@ -198,7 +154,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = link_onboard_smbios_data; + dev->ops->get_smbios_data = onboard_smbios_data; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/kontron/come-bip2/mainboard_smi.c b/src/mainboard/kontron/come-bip2/mainboard_smi.c index d281742..c4221ab 100644 --- a/src/mainboard/kontron/come-bip2/mainboard_smi.c +++ b/src/mainboard/kontron/come-bip2/mainboard_smi.c @@ -23,74 +23,12 @@ #include <cpu/intel/model_206ax/model_206ax.h> #include <elog.h> -/* Include EC functions */ -#include <ec/google/chromeec/ec.h> -#include "ec.h" - -static u8 mainboard_smi_ec(void) -{ - u8 cmd = google_chromeec_get_event(); - u32 pm1_cnt; - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - switch (cmd) { - case EC_HOST_EVENT_LID_CLOSED: - printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); - - /* Go to S5 */ - pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); - pm1_cnt |= (0xf << 10); - outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); - break; - } - - return cmd; -} - void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } } void mainboard_smi_sleep(u8 slp_typ) { - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - if (smm_get_gnvs()->s3u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s3u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - case 5: - if (smm_get_gnvs()->s5u0 == 0) - google_chromeec_set_usb_charge_mode( - 0, USB_CHARGE_MODE_DISABLED); - if (smm_get_gnvs()->s5u1 == 0) - google_chromeec_set_usb_charge_mode( - 1, USB_CHARGE_MODE_DISABLED); - break; - } - - /* Disable SCI and SMI events */ - google_chromeec_set_smi_mask(0); - google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - while (google_chromeec_get_event() != 0); - - /* Enable wake events */ - google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS); } #define APMC_ACPI_EN 0xe1 @@ -100,16 +38,8 @@ int mainboard_smi_apmc(u8 apmc) { switch (apmc) { case APMC_ACPI_EN: - google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); break; case APMC_ACPI_DIS: - google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - while (google_chromeec_get_event() != 0); - google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); break; } return 0; diff --git a/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex deleted file mode 100644 index 7ed2663..0000000 --- a/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 05 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 2c 00 -00 00 00 00 00 00 ad 75 -34 4b 54 46 32 35 36 36 -34 48 5a 2d 31 47 36 45 -31 20 45 31 80 2c 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/kontron/come-bip2/onboard.h b/src/mainboard/kontron/come-bip2/onboard.h deleted file mode 100644 index 7bc213b..0000000 --- a/src/mainboard/kontron/come-bip2/onboard.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef LINK_ONBOARD_H -#define LINK_ONBOARD_H - -#define BOARD_LIGHTSENSOR_NAME "lightsensor" -#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 -#define BOARD_LIGHTSENSOR_IRQ 0 - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_I2C_ADDR 0x4b -#define BOARD_TRACKPAD_IRQ 20 -#define BOARD_TRACKPAD_WAKE_GPIO 0x1c - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a -#define BOARD_TOUCHSCREEN_IRQ 22 - -#endif diff --git a/src/mainboard/kontron/come-bip2/romstage.c b/src/mainboard/kontron/come-bip2/romstage.c index 8142845..fcdeb3c 100644 --- a/src/mainboard/kontron/come-bip2/romstage.c +++ b/src/mainboard/kontron/come-bip2/romstage.c @@ -31,7 +31,7 @@ #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> -#include "ec/google/chromeec/ec.h" +#include <superio/winbond/w83627dhg/w83627dhg.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <halt.h> @@ -115,28 +115,10 @@ void rcba_config(void) RCBA32(FD) = reg32; } -static uint8_t *locate_spd(void) +void mainboard_get_spd(spd_raw_data *spd) { - const int gpio_vector[] = {41, 42, 43, 10, -1}; - uint8_t *spd_file; - size_t spd_file_len; - int spd_index = get_gpios(gpio_vector); - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < ((spd_index + 1) * 256)) { - printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); } void mainboard_fill_pei_data(struct pei_data *pei_data) @@ -157,9 +139,10 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) .thermalbase = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 }, .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .ddr3lv_support = 1, + .ec_present = 0, + .ddr3lv_support = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel @@ -187,8 +170,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) }, }; *pei_data = pei_data_template; - memcpy(pei_data->spd_data[0], locate_spd(), - sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -209,18 +190,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 0, 0, -1 }, /* P13: Empty */ }; -void mainboard_get_spd(spd_raw_data *spd) { - memcpy(&spd[0], locate_spd(), 128); -} - void mainboard_early_init(int s3resume) { - if (!s3resume) { - /* This is the fastest way to let users know - * the Intel CPU is now alive. - */ - google_chromeec_kbbacklight(100); - } } int mainboard_should_reset_usb(int s3resume) diff --git a/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex deleted file mode 100644 index 5beb5fc..0000000 --- a/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 11 0b 03 04 19 02 02 -03 11 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -f0 0a 3c 3c 01 40 83 01 -00 80 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ce 01 -00 00 00 00 00 00 6a 04 -4d 34 37 31 42 35 36 37 -34 42 48 30 2d 59 4b 30 -20 20 00 00 80 ce 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/thermal.h b/src/mainboard/kontron/come-bip2/thermal.h index 4a1f31b..af71849 100644 --- a/src/mainboard/kontron/come-bip2/thermal.h +++ b/src/mainboard/kontron/come-bip2/thermal.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef LINK_THERMAL_H -#define LINK_THERMAL_H +#ifndef MAINBOARD_THERMAL_H +#define MAINBOARD_THERMAL_H /* Config TDP Sensor ID */ #define CTDP_SENSOR_ID 9 /* PECI */

1 0

New patch to review for coreboot: kontron/come-bip2: make a copy of google/link
by Stefan Reinauer 18 Apr '16

18 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14400 -gerrit commit 478421e04e31d7a070022bbb0285c07a438437cf Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Mar 21 22:42:21 2016 -0700 kontron/come-bip2: make a copy of google/link Change-Id: I5b3b9ad31c16a5dba49e78755b3a87ebe414acf2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/kontron/come-bip2/Kconfig | 47 +++ src/mainboard/kontron/come-bip2/Kconfig.name | 2 + src/mainboard/kontron/come-bip2/Makefile.inc | 45 +++ src/mainboard/kontron/come-bip2/acpi/chromeos.asl | 19 ++ src/mainboard/kontron/come-bip2/acpi/ec.asl | 23 ++ .../kontron/come-bip2/acpi/ivybridge_pci_irqs.asl | 64 ++++ src/mainboard/kontron/come-bip2/acpi/mainboard.asl | 84 +++++ src/mainboard/kontron/come-bip2/acpi/platform.asl | 45 +++ .../come-bip2/acpi/sandybridge_pci_irqs.asl | 64 ++++ src/mainboard/kontron/come-bip2/acpi/superio.asl | 25 ++ src/mainboard/kontron/come-bip2/acpi/thermal.asl | 219 ++++++++++++ src/mainboard/kontron/come-bip2/acpi_tables.c | 72 ++++ src/mainboard/kontron/come-bip2/board_info.txt | 7 + src/mainboard/kontron/come-bip2/chromeos.c | 109 ++++++ src/mainboard/kontron/come-bip2/chromeos.fmd | 38 +++ src/mainboard/kontron/come-bip2/cmos.layout | 124 +++++++ src/mainboard/kontron/come-bip2/devicetree.cb | 103 ++++++ src/mainboard/kontron/come-bip2/dsdt.asl | 58 ++++ src/mainboard/kontron/come-bip2/ec.c | 47 +++ src/mainboard/kontron/come-bip2/ec.h | 58 ++++ .../kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex | 32 ++ src/mainboard/kontron/come-bip2/gpio.c | 119 +++++++ src/mainboard/kontron/come-bip2/hda_verb.c | 136 ++++++++ src/mainboard/kontron/come-bip2/i915.c | 374 +++++++++++++++++++++ src/mainboard/kontron/come-bip2/i915io.c | 355 +++++++++++++++++++ src/mainboard/kontron/come-bip2/i915io.h | 82 +++++ src/mainboard/kontron/come-bip2/intel_dp.c | 166 +++++++++ src/mainboard/kontron/come-bip2/mainboard.c | 210 ++++++++++++ src/mainboard/kontron/come-bip2/mainboard_smi.c | 116 +++++++ .../come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex | 32 ++ src/mainboard/kontron/come-bip2/onboard.h | 32 ++ src/mainboard/kontron/come-bip2/romstage.c | 233 +++++++++++++ .../come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex | 32 ++ src/mainboard/kontron/come-bip2/thermal.h | 39 +++ 34 files changed, 3211 insertions(+) diff --git a/src/mainboard/kontron/come-bip2/Kconfig b/src/mainboard/kontron/come-bip2/Kconfig new file mode 100644 index 0000000..e61bba0 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/Kconfig @@ -0,0 +1,47 @@ +if BOARD_GOOGLE_LINK + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select CPU_INTEL_SOCKET_RPGA989 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SOUTHBRIDGE_INTEL_C216 + select BOARD_ROMSIZE_KB_8192 + select EC_GOOGLE_CHROMEEC + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + select SERIRQ_CONTINUOUS_MODE + select MAINBOARD_HAS_NATIVE_VGA_INIT + +config CHROMEOS + select CHROMEOS_VBNV_CMOS + select LID_SWITCH + +config MAINBOARD_DIR + string + default google/link + +config MAINBOARD_PART_NUMBER + string + default "Link" + +config MMCONF_BASE_ADDRESS + hex + default 0xf8000000 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config GBB_HWID + string + depends on CHROMEOS + default "X86 LINK TEST 6638" +endif # BOARD_GOOGLE_LINK diff --git a/src/mainboard/kontron/come-bip2/Kconfig.name b/src/mainboard/kontron/come-bip2/Kconfig.name new file mode 100644 index 0000000..289164b --- /dev/null +++ b/src/mainboard/kontron/come-bip2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_LINK + bool "Link" diff --git a/src/mainboard/kontron/come-bip2/Makefile.inc b/src/mainboard/kontron/come-bip2/Makefile.inc new file mode 100644 index 0000000..b79e4d3 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/Makefile.inc @@ -0,0 +1,45 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ec.c + +romstage-y += chromeos.c +ramstage-y += chromeos.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +SPD_BIN = $(obj)/spd.bin + +# Order of names in SPD_SOURCES is important! +SPD_SOURCES = elpida_4Gb_1600_x16 +SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 +SPD_SOURCES += micron_4Gb_1600_1.35v_x16 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd +romstage-y += gpio.c diff --git a/src/mainboard/kontron/come-bip2/acpi/chromeos.asl b/src/mainboard/kontron/come-bip2/acpi/chromeos.asl new file mode 100644 index 0000000..eec650a --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/chromeos.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(OIPG, Package() { + Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button + Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect +}) diff --git a/src/mainboard/kontron/come-bip2/acpi/ec.asl b/src/mainboard/kontron/come-bip2/acpi/ec.asl new file mode 100644 index 0000000..2e898ed --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/kontron/come-bip2/acpi/ivybridge_pci_irqs.asl b/src/mainboard/kontron/come-bip2/acpi/ivybridge_pci_irqs.asl new file mode 100644 index 0000000..2b61cf1 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/ivybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 20 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 21 }, + Package() { 0x001fffff, 1, 0, 22 }, + Package() { 0x001fffff, 2, 0, 23 }, + Package() { 0x001fffff, 3, 0, 16 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} diff --git a/src/mainboard/kontron/come-bip2/acpi/mainboard.asl b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl new file mode 100644 index 0000000..01e99fa --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/mainboard.asl @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/link/onboard.h> + +Scope (\_SB) { + Device (LID0) + { + Name(_HID, EisaId("PNP0C0D")) + Method(_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + + // EC_LID_OUT is GPIO15 + Name(_PRW, Package(){0x1f, 0x05}) + } + + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } + + Device (TPAD) + { + Name (_ADR, 0x0) + Name (_UID, 1) + + // Report as a Sleep Button device so Linux will + // automatically enable it as a wake source + Name(_HID, EisaId("PNP0C0E")) + + // Trackpad Wake is GPIO12 + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) + + Name(_CRS, ResourceTemplate() + { + // PIRQE -> GSI20 + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + + // SMBUS Address 0x4b + VendorShort (ADDR) { BOARD_TRACKPAD_I2C_ADDR } + }) + } + + Device (TSCR) + { + Name (_ADR, 0x0) + Name (_UID, 2) + + // Report as a Sleep Button device so Linux will + // automatically enable it as a wake source + Name(_HID, EisaId("PNP0C0E")) + + // Touchscreen Wake is GPIO14 + Name(_PRW, Package(){0x1e, 0x03}) + + Name(_CRS, ResourceTemplate() + { + // PIRQG -> GSI22 + Interrupt (ResourceConsumer, Edge, ActiveLow) {22} + + // SMBUS Address 0x4a + VendorShort (ADDR) {0x4a} + }) + } +} diff --git a/src/mainboard/kontron/come-bip2/acpi/platform.asl b/src/mainboard/kontron/come-bip2/acpi/platform.asl new file mode 100644 index 0000000..c84736a --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/platform.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + /* Disable WWAN */ + Store (Zero, GP36) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Update AC status */ + Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) + if (LNotEqual (Local0, \PWRS)) { + Store (Local0, \PWRS) + Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) + } + + /* Update LID status */ + Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) + if (LNotEqual (Local0, \LIDS)) { + Store (Local0, \LIDS) + Notify (\_SB.LID0, 0x80) + } + + Return(Package(){0,0}) +} diff --git a/src/mainboard/kontron/come-bip2/acpi/sandybridge_pci_irqs.asl b/src/mainboard/kontron/come-bip2/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..6aebd13 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 19 }, + Package() { 0x001cffff, 1, 0, 20 }, + Package() { 0x001cffff, 2, 0, 17 }, + Package() { 0x001cffff, 3, 0, 18 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, + Package() { 0x001fffff, 1, 0, 23 }, + Package() { 0x001fffff, 2, 0, 16 }, + Package() { 0x001fffff, 3, 0, 18 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/kontron/come-bip2/acpi/superio.asl b/src/mainboard/kontron/come-bip2/acpi/superio.asl new file mode 100644 index 0000000..266a67c --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 + +/* ACPI code for EC SuperIO functions */ +#include "../../../../ec/google/chromeec/acpi/superio.asl" diff --git a/src/mainboard/kontron/come-bip2/acpi/thermal.asl b/src/mainboard/kontron/come-bip2/acpi/thermal.asl new file mode 100644 index 0000000..9163493 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi/thermal.asl @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (CRIT) + { + // Thermal zone polling frequency: 5 seconds + Name (_TZP, 50) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + Method (_TMP, 0, Serialized) + { + // Get CPU Temperature from TIN9/PECI via EC + Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) + + // Check for sensor not calibrated + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (CTOK(0)) + } + + // Check for sensor not present + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (CTOK(0)) + } + + // Check for sensor not powered + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (CTOK(0)) + } + + // Check for sensor bad reading + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (CTOK(0)) + } + + // Adjust by offset to get Kelvin + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + // Convert to 1/10 Kelvin + Multiply (Local0, 10, Local0) + Return (Local0) + } + } + + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + // Get Temperature from TIN# set in NVS + Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + + // Check for sensor not present + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (CTOK(0)) + } + + // Check for sensor not powered + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (CTOK(0)) + } + + // Check for sensor bad reading + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (CTOK(0)) + } + + // Adjust by offset to get Kelvin + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + // Convert to 1/10 Kelvin + Multiply (Local0, 10, Local0) + Return (Local0) + } + + /* CTDP Down */ + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + /* CTDP Nominal */ + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Name (_AL0, Package () { TDP0 }) + Name (_AL1, Package () { TDP1 }) + + PowerResource (TNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + \_SB.PCI0.MCHC.STND () + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + \_SB.PCI0.MCHC.STDN () + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (TNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (TDP0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { TNP0 }) + } + + Device (TDP1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { TNP1 }) + } + } +} diff --git a/src/mainboard/kontron/come-bip2/acpi_tables.c b/src/mainboard/kontron/come-bip2/acpi_tables.c new file mode 100644 index 0000000..a7f2c50 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/acpi_tables.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <ec/google/chromeec/ec.h> + +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = CTDP_SENSOR_ID; + + gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; + gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON; + + gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; + gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + +#if CONFIG_CHROMEOS + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif + + acpi_update_thermal_table(gnvs); + + // the lid is open by default. + gnvs->lids = 1; +} diff --git a/src/mainboard/kontron/come-bip2/board_info.txt b/src/mainboard/kontron/come-bip2/board_info.txt new file mode 100644 index 0000000..f8aa153 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/board_info.txt @@ -0,0 +1,7 @@ +Board name: Chromebook Pixel +Category: laptop +Board URL: http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/kontron/come-bip2/chromeos.c b/src/mainboard/kontron/come-bip2/chromeos.c new file mode 100644 index 0000000..d07e851 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/chromeos.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <bootmode.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + /* Write Protect: GPIO57 = PCH_SPI_WP_D */ + gpios->gpios[0].port = 57; + gpios->gpios[0].polarity = ACTIVE_HIGH; + gpios->gpios[0].value = get_write_protect_state(); + strncpy((char *)gpios->gpios[0].name,"write protect", + GPIO_MAX_NAME_LENGTH); + /* Recovery: the "switch" comes from the EC */ + gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + + /* Lid: the "switch" comes from the EC */ + gpios->gpios[2].port = -1; + gpios->gpios[2].polarity = ACTIVE_HIGH; + gpios->gpios[2].value = get_lid_switch(); + strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + + /* Power Button: hard-coded as not pressed; we'll detect later presses + * via SMI. */ + gpios->gpios[3].port = -1; + gpios->gpios[3].polarity = ACTIVE_HIGH; + gpios->gpios[3].value = 0; + strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + + /* Developer: a tricky case on Link, there is no switch */ + gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[4].polarity = ACTIVE_HIGH; + gpios->gpios[4].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH); + + /* Did we load the VGA Option ROM? */ + gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[5].polarity = ACTIVE_HIGH; + gpios->gpios[5].value = gfx_get_init_done(); + strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); +} +#endif + +int get_write_protect_state(void) +{ + return get_gpio(57); +} + +int get_lid_switch(void) +{ + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + + return !!(ec_switches & EC_SWITCH_LID_OPEN); +} + +/* The dev-switch is virtual on Link (and so handled elsewhere). */ +int get_developer_mode_switch(void) +{ + return 0; +} + +/* There are actually two recovery switches. One is the magic keyboard chord, + * the other is driven by Servo. */ +int get_recovery_mode_switch(void) +{ + u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES); + u32 ec_events; + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} diff --git a/src/mainboard/kontron/come-bip2/chromeos.fmd b/src/mainboard/kontron/come-bip2/chromeos.fmd new file mode 100644 index 0000000..21b39c0 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/chromeos.fmd @@ -0,0 +1,38 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x200000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x1ff000 + } + SI_BIOS@0x200000 0x600000 { + RW_SECTION_A@0x0 0xf0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0xdffc0 + RW_FWID_A@0xeffc0 0x40 + } + RW_SECTION_B@0xf0000 0xf0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0xdffc0 + RW_FWID_B@0xeffc0 0x40 + } + RW_MRC_CACHE@0x1e0000 0x10000 + RW_ELOG@0x1f0000 0x4000 + RW_SHARED@0x1f4000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x1f8000 0x2000 + RW_UNUSED@0x1fa000 0x6000 + RW_LEGACY@0x200000 0x200000 + WP_RO@0x400000 0x200000 { + RO_VPD@0x0 0x4000 + RO_UNUSED@0x4000 0xc000 + RO_SECTION@0x10000 0x1f0000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x100000 + } + } + } +} diff --git a/src/mainboard/kontron/come-bip2/cmos.layout b/src/mainboard/kontron/come-bip2/cmos.layout new file mode 100644 index 0000000..0513a54 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/cmos.layout @@ -0,0 +1,124 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode +#412 4 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv + +# coreboot config options: northbridge +544 3 e 11 gfx_uma_size + +#547 437 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/kontron/come-bip2/devicetree.cb b/src/mainboard/kontron/come-bip2/devicetree.cb new file mode 100644 index 0000000..437b3cb --- /dev/null +++ b/src/mainboard/kontron/come-bip2/devicetree.cb @@ -0,0 +1,103 @@ +chip northbridge/intel/sandybridge + # IGD Displays + register "gfx.ndid" = "1" + register "gfx.did" = "{ 0x80000000, 0x80000000, 0x00000000, 0x00000000, 0x00000000 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as eDP and configure power delays + register "gpu_panel_port_select" = "1" # eDP_A + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000000" + + register "max_mem_clock_mhz" = "666" + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA989 + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + subsystemid 0x1ae0 0xc000 inherit + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0100" + register "gpi7_routing" = "2" + register "gpi8_routing" = "1" + + register "sata_port_map" = "0x1" + + register "sata_port0_gen3_tx" = "0x00880a7f" + + # EC range is 0x800-0x9ff + # Please note: you MUST not change this unless + # you also change romstage.c:pch_enable_lpc + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + register "c2_latency" = "1" + register "p_cnt_throttling_supported" = "0" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (WLAN actual) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/kontron/come-bip2/dsdt.asl b/src/mainboard/kontron/come-bip2/dsdt.asl new file mode 100644 index 0000000..be6a412 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + // Some generic macros + #include "acpi/platform.asl" + #include "acpi/mainboard.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include "acpi/thermal.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include "acpi/sandybridge_pci_irqs.asl" + + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/kontron/come-bip2/ec.c b/src/mainboard/kontron/come-bip2/ec.c new file mode 100644 index 0000000..acf1185 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/ec.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <types.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +void link_ec_init(void) +{ + printk(BIOS_DEBUG, "link_ec_init\n"); + post_code(0xf0); + + /* Restore SCI event mask on resume. */ + if (acpi_is_wakeup_s3()) { + google_chromeec_log_events(LINK_EC_LOG_EVENTS | + LINK_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(LINK_EC_LOG_EVENTS | + LINK_EC_S5_WAKE_EVENTS); + } + + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_wake_mask(0); + + post_code(0xf1); +} diff --git a/src/mainboard/kontron/come-bip2/ec.h b/src/mainboard/kontron/come-bip2/ec.h new file mode 100644 index 0000000..af06772 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/ec.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_EC_H +#define LINK_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +#define EC_SCI_GPI 23 /* GPIO7/GPE23 is EC_SCI# */ +#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */ + +#define LINK_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define LINK_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define LINK_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define LINK_EC_S3_WAKE_EVENTS \ + (LINK_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define LINK_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#ifndef __ACPI__ +extern void link_ec_init(void); +#endif + +#endif // LINK_EC_H diff --git a/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex new file mode 100644 index 0000000..ef36c39 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/elpida_4Gb_1600_x16.spd.hex @@ -0,0 +1,32 @@ +92 10 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 81 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 42 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 02 fe 00 +11 52 00 00 00 07 7f 37 +45 42 4a 32 30 55 47 36 +45 42 55 30 2d 47 4e 2d +46 20 30 20 02 fe 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/gpio.c b/src/mainboard/kontron/come-bip2/gpio.c new file mode 100644 index 0000000..dcd29a3 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/gpio.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_GPIO_H +#define LINK_GPIO_H + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */ + .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */ + .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */ + .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */ + .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */ + .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */ + .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */ + .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */ + .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */ + .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */ + .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */ + .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */ + .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */ + .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */ +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio1 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */ + .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */ + .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */ + .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */ + .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */ + .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */ +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio36 = GPIO_DIR_OUTPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio36 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; +#endif diff --git a/src/mainboard/kontron/come-bip2/hda_verb.c b/src/mainboard/kontron/come-bip2/hda_verb.c new file mode 100644 index 0000000..b824f0f --- /dev/null +++ b/src/mainboard/kontron/come-bip2/hda_verb.c @@ -0,0 +1,136 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x11020011, // Codec Vendor / Device ID: Creative CA0132 + 0x144dc0c2, // Subsystem ID + 0x00000014, // Number of jacks + Number of Malcolm setup blocks. + + /* Malcolm Setup */ + + 0x01570d09, + 0x01570c23, + 0x01570a01, + 0x01570df0, + + 0x01570efe, + 0x01570775, + 0x015707d3, + 0x01570709, + + 0x01570753, + 0x015707d4, + 0x015707ef, + 0x01570775, + + 0x015707d3, + 0x01570709, + 0x01570702, + 0x01570737, + + 0x01570778, + 0x01553cce, + 0x015575c9, + 0x01553dce, + + 0x0155b7c9, + 0x01570de8, + 0x01570efe, + 0x01570702, + + 0x01570768, + 0x01570762, + 0x01553ace, + 0x015546c9, + + 0x01553bce, + 0x0155e8c9, + 0x01570d49, + 0x01570c88, + + 0x01570d20, + 0x01570e19, + 0x01570700, + 0x01571a05, + + 0x01571b29, + 0x01571a04, + 0x01571b29, + 0x01570a01, + + /* Pin Widget Verb Table */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144DC0C2 */ + AZALIA_SUBVENDOR(0x0, 0x144dc0c2), + + /* Pin Complex (NID 0x0B) Port-G Analog Unknown Speaker at Int N/A */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x901700f0), + + /* Pin Complex (NID 0x0C) N/C */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x70f000f0), + + /* Pin Complex (NID 0x0D) N/C */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x70f000f0), + + /* Pin Complex (NID 0x0E) N/C */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x70f000f0), + + /* Pin Complex (NID 0x0F) N/C */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x70f000f0), + + /* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */ + AZALIA_PIN_CFG(0x0, 0x10, 0x032110f0), + + /* Pin Complex (NID 0x11) Port-B Click Mic */ + AZALIA_PIN_CFG(0x0, 0x11, 0x90a700f0), + + /* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */ + AZALIA_PIN_CFG(0x0, 0x12, 0x03a110f0), + + /* Pin Complex (NID 0x13) What you hear */ + AZALIA_PIN_CFG(0x0, 0x13, 0x90d600f0), + + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel CougarPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of jacks + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) +}; + + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up codec */ + 0x00270500, /* power up DAC */ + 0x00b70500, /* power up speaker */ + 0x00b70740, /* enable speaker out */ + 0x00b78d00, /* enable EAPD pin */ + 0x00b70c02, /* set EAPD pin */ + 0x0143b013, /* beep volume */ +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/kontron/come-bip2/i915.c b/src/mainboard/kontron/come-bip2/i915.c new file mode 100644 index 0000000..31249a1 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/i915.c @@ -0,0 +1,374 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <stdlib.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <delay.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "onboard.h" +#include "ec.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <northbridge/intel/sandybridge/gma.h> +#include <smbios.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> + +#include <cpu/x86/tsc.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <edid.h> +#include "i915io.h" + +enum { + vmsg = 1, vio = 2, vspin = 4, +}; + +static int verbose = 0; + +static unsigned int *mmio; +static unsigned int graphics; +static unsigned short addrport; +static unsigned short dataport; +static unsigned int physbase; +static u32 htotal, hblank, hsync, vtotal, vblank, vsync; + +const u32 link_edid_data[] = { + 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, + 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259, + 0x00545017, 0x01010000, 0x01010101, 0x01010101, + 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031, + 0xb510003a, 0x19000010, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00, + 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000, + 0x31504c00, 0x45513932, 0x50532d31, 0x24003141, +}; + +#define READ32(addr) io_i915_READ32(addr) +#define WRITE32(val, addr) io_i915_WRITE32(val, addr) + +static char *regname(unsigned long addr) +{ + static char name[16]; + snprintf(name, sizeof (name), "0x%lx", addr); + return name; +} + +unsigned long io_i915_READ32(unsigned long addr) +{ + unsigned long val; + outl(addr, addrport); + val = inl(dataport); + if (verbose & vio) + printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); + return val; +} + +void io_i915_WRITE32(unsigned long val, unsigned long addr) +{ + if (verbose & vio) + printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); + outl(addr, addrport); + outl(val, dataport); +} + + +/* + 2560 + 4 words per + 4 *p + 10240 + 4k bytes per page + 4096/p + 2.50 + 1700 lines + 1700 * p + 4250.00 + PTEs +*/ +static void +setgtt(int start, int end, unsigned long base, int inc) +{ + int i; + + for(i = start; i < end; i++){ + u32 word = base + i*inc; + WRITE32(word|1,(i*4)|1); + } +} + +static unsigned long tickspermicrosecond = 1795; +static unsigned long long globalstart; + +static unsigned long +microseconds(unsigned long long start, unsigned long long end) +{ + unsigned long ret; + ret = ((end - start)/tickspermicrosecond); + return ret; +} + +static unsigned long globalmicroseconds(void) +{ + return microseconds(globalstart, rdtscll()); +} + +extern struct iodef iodefs[]; +extern int niodefs; + +static int i915_init_done = 0; + +/* fill the palette. This runs when the P opcode is hit. */ +/* and, yes, it's needed for even 32 bits per pixel */ +static void palette(void) +{ + int i; + unsigned long color = 0; + + for(i = 0; i < 256; i++, color += 0x010101){ + io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); + } +} + +static unsigned long times[4096]; + +static int run(int index) +{ + int i, prev = 0; + struct iodef *id, *lastidread = 0; + unsigned long u, t; + if (index >= niodefs) + return index; + /* state machine! */ + for(i = index, id = &iodefs[i]; id->op; i++, id++){ + switch(id->op){ + case M: + if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n", + globalmicroseconds(), id->msg); + break; + case P: + palette(); + break; + case R: + u = READ32(id->addr); + if (verbose & vio) + printk(BIOS_SPEW, "\texpect %08lx\n", id->data); + /* we're looking for something. */ + if (lastidread->addr == id->addr){ + /* they're going to be polling. + * just do it 1000 times + */ + for (t = 0; t < 1000 && id->data != u; t++){ + u = READ32(id->addr); + } + if (verbose & vspin) printk(BIOS_SPEW, + "%s: # loops %ld got %08lx want %08lx\n", + regname(id->addr), + t, u, id->data); + } + lastidread = id; + break; + case W: + WRITE32(id->data, id->addr); + if (id->addr == PCH_PP_CONTROL){ + if (verbose & vio) + printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); + switch(id->data & 0xf){ + case 8: break; + case 7: break; + default: udelay(100000); + if (verbose & vio) + printk(BIOS_SPEW, "U %d\n", 100000); + } + } + break; + case V: + if (id->count < 8){ + prev = verbose; + verbose = id->count; + } else { + verbose = prev; + } + printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); + break; + case I: + printk(BIOS_SPEW, "run: return %d\n", i+1); + return i+1; + break; + default: + printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i); + return -1; + } + if (id->udelay) + udelay(id->udelay); + if (i < ARRAY_SIZE(times)) + times[i] = globalmicroseconds(); + } + printk(BIOS_SPEW, "run: return %d\n", i); + return i+1; +} + +int i915lightup_sandy(const struct i915_gpu_controller_info *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) +{ + static struct edid edid; + int edid_ok; + + int index; + u32 auxin[16], auxout[16]; + mmio = (void *)pmmio; + addrport = piobase; + dataport = addrport + 4; + physbase = pphysbase; + graphics = pgfx; + printk(BIOS_SPEW, "i915lightup: graphics %p mmio %p" + "addrport %04x physbase %08x\n", + (void *)graphics, mmio, addrport, physbase); + globalstart = rdtscll(); + + + edid_ok = decode_edid((unsigned char *)&link_edid_data, + sizeof(link_edid_data), &edid); + printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok); + edid.framebuffer_bits_per_pixel = 32; + + htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); + + hblank = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); + + hsync = (edid.ha + edid.hso - 1) | + ((edid.ha + edid.hso + edid.hspw- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); + + vtotal = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); + + vblank = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); + + vsync = (edid.va + edid.vso - 1) |((edid.va + edid.vso + edid.vspw- 1) << 16); + printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); + + printk(BIOS_SPEW, "Table has %d elements\n", niodefs); + + index = run(0); + printk(BIOS_SPEW, "Run returns %d\n", index); + auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14); + auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); + index = run(index); + printk(BIOS_SPEW, "Run returns %d\n", index); + auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0); + index = run(index); + printk(BIOS_SPEW, "Run returns %d\n", index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0; + auxout[1] = 0x01000000; + /* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8; + auxout[1] = 0x0a840000; + /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ + auxout[2] = 0x00000000; + auxout[3] = 0x01000000; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[1] = 0x21000000; + /* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE | + * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; + auxout[1] = 0x00000000; + /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[1] = 0x22000000; + /* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE | + * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3; + auxout[1] = 0x00000000; + /* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5; + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5); + index = run(index); + auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0; + auxout[1] = 0x00000000; + /* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE | + * DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/ + intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0); + index = run(index); + + if (index != niodefs) + printk(BIOS_ERR, "Left over IO work in i915_lightup" + " -- this is likely a table error. " + "Only %d of %d were done.\n", index, niodefs); + printk(BIOS_SPEW, "DONE startup\n"); + verbose = 0; + /* GTT is the Global Translation Table for the graphics pipeline. + * It is used to translate graphics addresses to physical + * memory addresses. As in the CPU, GTTs map 4K pages. + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * There are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + * The setgtt function adds a further bit of flexibility: + * it allows you to set a range (the first two parameters) to point + * to a physical address (third parameter);the physical address is + * incremented by a count (fourth parameter) for each GTT in the + * range. + * Why do it this way? For ultrafast startup, + * we can point all the GTT entries to point to one page, + * and set that page to 0s: + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * this takes about 2 ms, and is a win because zeroing + * the page takes a up to 200 ms. We will be exploiting this + * trick in a later rev of this code. + * This call sets the GTT to point to a linear range of pages + * starting at physbase. + */ + setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); + printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n", + (void *)graphics, FRAME_BUFFER_BYTES); + memset((void *)graphics, 0, FRAME_BUFFER_BYTES); + printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); + set_vbe_mode_info_valid(&edid, (uintptr_t)graphics); + i915_init_done = 1; + return i915_init_done; +} diff --git a/src/mainboard/kontron/come-bip2/i915io.c b/src/mainboard/kontron/come-bip2/i915io.c new file mode 100644 index 0000000..5ebb42d --- /dev/null +++ b/src/mainboard/kontron/come-bip2/i915io.c @@ -0,0 +1,355 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include "i915io.h" + +struct iodef iodefs[] = { + {V, 0}, + {W, 1, "", PCH_GMBUS0, 0x00000000, 0}, + {R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0}, + {R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0}, + {W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0}, + {M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0}, + {R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10}, + {W, 1, "", FORCEWAKE_MT, 0x00010001, 0}, + {R, 1, "", FORCEWAKE_MT, 0x00010001, 0}, + {R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0}, + {R, 1, "", 0x13805c, 0x40000000, 0}, + {R, 1, "", 0xa180, 0x84100020, 0}, + {W, 1, "", FORCEWAKE_MT, 0x00010000, 0}, + {R, 1, "", 0x120000, 0x00000000, 0}, + {M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {R, 1, "", _PIPEBCONF, 0x00000000, 0}, + {W, 1, "", _PIPEBCONF, 0x00000000, 0}, + {R, 1, "", 0x72008, 0x00000000, 0}, + {W, 1, "", 0x72008, 0x00000000, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {R, 1, "", _PIPEBCONF, 0x00000000, 0}, + {W, 1, "", _PIPEBCONF, 0x00000000, 0}, + {R, 1, "", 0x72008, 0x00000000, 0}, + {W, 1, "", 0x72008, 0x00000000, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {R, 1, "", _PIPEBCONF, 0x00000000, 0}, + {W, 1, "", _PIPEBCONF, 0x00000000, 0}, + {R, 1, "", 0x72008, 0x00000000, 0}, + {W, 1, "", 0x72008, 0x00000000, 300}, + {W, 1, "", CPU_VGACNTRL, 0x80000000, 0}, + {R, 1, "", CPU_VGACNTRL, 0x80000000, 0}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, + {R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0}, + {R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0}, + {R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0}, + {M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0}, + {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, 0x00000000, 0}, + {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, + {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {I,}, + {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0}, + {R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0}, + {M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0}, + {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0}, + {W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0}, + {R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200}, + {M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0}, + {W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0}, + {R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200}, + {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, + {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", 0x9404, 0x00002000, 0}, + {W, 1, "", ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE | 0x10000000, 0}, + {W, 1, "", IVB_CHICKEN3, 0x00000024, 0}, + {W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0}, + {W, 1, "", 0xb01c, 0x3c4fff8c, 0}, + {W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0}, + {R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0}, + {W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0}, + {R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0}, + {W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0}, + {R, 1, "", _DSPAADDR, 0x00000000, 0}, + {W, 1, "", _DSPAADDR, 0x00000000, 0}, + {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, + {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, + {R, 1, "", _DSPBCNTR, 0x00000000, 0}, + {W, 1, "", _DSPBCNTR, 0x00004000, 0}, + {R, 1, "", _DSPBADDR, 0x00000000, 0}, + {W, 1, "", _DSPBADDR, 0x00000000, 0}, + {R, 1, "", _DSPBSURF, 0x00000000, 0}, + {W, 1, "", _DSPBSURF, 0x00000000, 0}, + {R, 1, "", _DVSACNTR, 0x00000000, 0}, + {W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0}, + {R, 1, "", _DVSALINOFF, 0x00000000, 0}, + {W, 1, "", _DVSALINOFF, 0x00000000, 0}, + {R, 1, "", _DVSASURF, 0x00000000, 0}, + {W, 1, "", _DVSASURF, 0x00000000, 0}, + {W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0}, + {R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0}, + {W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0}, + {W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0}, + {W, 1, "", _TRANSB_CHICKEN2, TRANS_CHICKEN2_TIMING_OVERRIDE | 0x80000000, 0}, + {M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {I,}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, + {R, 2, "", PCH_DP_D, 0x00000004, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0}, + {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0}, + {M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0}, + {W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0}, + {W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0}, + {W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0}, + {W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0}, + {W, 1, "", _PCH_FPA1, 0x00020e08, 0}, + {W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0}, + {W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0}, + {W, 1, "", _HBLANK_A, 0x0a9f09ff, 0}, + {W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0}, + {W, 1, "", _VTOTAL_A, 0x06d406a3, 0}, + {W, 1, "", _VBLANK_A, 0x06d406a3, 0}, + {W, 1, "", _VSYNC_A, 0x06b006a6, 0}, + {W, 1, "", _PIPEASRC, 0x09ff06a3, 0}, + {W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0}, + {W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0}, + {W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0}, + {W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0}, + {M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, + {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500}, + {W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, + {R, 1, "", _PIPEASTAT, 0x00000000, 0}, + {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, + {R, 4562, "", _PIPEASTAT, 0x00000000, 0}, + {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, + {R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0}, + {W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0}, + {W, 1, "", _DSPASTRIDE, 0x00002800, 0}, + {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, + {W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0}, + {W, 1, "", _DSPAADDR, 0x00000000, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0}, + {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, + {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, + {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, + {M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0}, + {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200}, + {R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, + {W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0}, + {M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0}, + {W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0}, + {R, 1, "", 0x145d10, 0x2010040c, 0}, + {W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0}, + {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, + {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, + {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, + {R, 1, "", _FDI_RXA_CTL, 0x00000040, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, + {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, + {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, + {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, + {W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0}, + {R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0}, + {R, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, + {W, 1, "", _FDI_TXA_CTL, 0x00040000, 0}, + {R, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, + {W, 1, "", _FDI_RXA_CTL, 0x00020040, 0}, + {R, 1, "", _FDI_RXA_CTL, 0x00020040, 100}, + {P, 1, "Set Palette"}, + {R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0}, + {W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0}, + {R, 1, "", _PIPEASTAT, 0x00000000, 0}, + {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, + {R, 4533, "", _PIPEASTAT, 0x00000000, 0}, + {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, + {R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0}, + {R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0}, + {W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_BGRX888 & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0}, + {R, 1, "", _DSPAADDR, 0x00000000, 0}, + {W, 1, "", _DSPAADDR, 0x00000000, 0}, + {R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, + {W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0}, + {R, 1, "", _PIPEASTAT, 0x00000000, 0}, + {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, + {R, 4392, "", _PIPEASTAT, 0x00000000, 0}, + {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_STATUS, 0x00000000, 0}, + {M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0}, + {R, 2, "", PCH_PP_STATUS, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0}, + {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, + {M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0}, + {R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0}, + {R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0}, + {R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0}, + {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0}, + {R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0}, + {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, + {M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0}, + {R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0}, + {M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0}, + {W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, + {R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {I,}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {I,}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {I,}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0}, + {I,}, + {M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, + {I,}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, + {I,}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, + {I,}, + {W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, + {R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0}, + {R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0}, + {I,}, + {M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0}, + {W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, + {R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0}, + {R, 1, "", _PIPEADSL, 0x00000633, 500}, + {R, 1, "", _PIPEADSL, 0x00000652, 0}, + {R, 1, "", _PIPEASTAT, 0x00000000, 0}, + {W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0}, + {R, 5085, "", _PIPEASTAT, 0x00000000, 0}, + {M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0}, + {M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0}, + {I,}, +}; + +int niodefs = ARRAY_SIZE(iodefs); diff --git a/src/mainboard/kontron/come-bip2/i915io.h b/src/mainboard/kontron/come-bip2/i915io.h new file mode 100644 index 0000000..a7e915a --- /dev/null +++ b/src/mainboard/kontron/come-bip2/i915io.h @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/intel/gma/i915_reg.h> +#include <drivers/intel/gma/drm_dp_helper.h> + +/* things that are, strangely, not defined anywhere? */ +#define PCH_PP_UNLOCK 0xabcd0000 +#define WMx_LP_SR_EN (1<<31) + +/* Google Link-specific defines */ +/* how many 4096-byte pages do we need for the framebuffer? + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * HencetThere are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + */ +#define FRAME_BUFFER_PAGES ((2560*1700)/1024) +#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096) + +/* One-letter commands for code not meant to be ready for humans. + * The code was generated by a set of programs/scripts. + * M print out a kernel message + * R read a register. We do these mainly to ensure that if hardware wanted + * the register read, it was read; also, in debug, we can see what was expected + * and what was found. This has proven *very* useful to get this debugged. + * The udelay, if non-zero, will make sure there is a + * udelay() call with the value. + * The count is from the kernel and tells us how many times this read was done. + * Also useful for debugging and the state + * machine uses the info to drive a poll. + * W Write a register + * V set verbosity. It's a bit mask. + * 0 -> nothing + * 1 -> print kernel messages + * 2 -> print IO ops + * 4 -> print the number of times we spin on a register in a poll + * 8 -> restore whatever the previous verbosity level was + * (only one deep stack) + * + * Again, this is not really meant for human consumption. There is not a poll + * operator as such because, sometimes, there is a read/write/read where the + * second read is a poll, and this chipset is so touchy I'm reluctant to move + * things around and/or delete too many reads. + */ +#define M 1 +#define R 2 +#define W 4 +#define V 8 +#define I 16 +#define P 32 + +struct iodef { + unsigned char op; + unsigned int count; + const char *msg; + unsigned long addr; + unsigned long data; + unsigned long udelay; +}; + +/* i915.c */ +unsigned long io_i915_READ32(unsigned long addr); +void io_i915_WRITE32(unsigned long val, unsigned long addr); + +/* intel_dp.c */ +u32 pack_aux(u32 *src, int src_bytes); +void unpack_aux(u32 src, u32 *dst, int dst_bytes); +int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, + u32 *recv, int recv_size); diff --git a/src/mainboard/kontron/come-bip2/intel_dp.c b/src/mainboard/kontron/come-bip2/intel_dp.c new file mode 100644 index 0000000..f74743a --- /dev/null +++ b/src/mainboard/kontron/come-bip2/intel_dp.c @@ -0,0 +1,166 @@ +/* + * Copyright 2013 Google Inc. + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Keith Packard <keithp(a)keithp.com> + * + */ + +#include <console/console.h> +#include <stdint.h> +#include <delay.h> +#include "i915io.h" + +u32 +pack_aux(u32 *src32, int src_bytes) +{ + u8 *src = (u8 *)src32; + int i; + u32 v = 0; + + if (src_bytes > 4) + src_bytes = 4; + for (i = 0; i < src_bytes; i++) + v |= ((u32) src[i]) << ((3-i) * 8); + return v; +} + +void +unpack_aux(u32 src, u32 *dst32, int dst_bytes) +{ + u8 *dst = (u8 *)dst32; + + int i; + if (dst_bytes > 4) + dst_bytes = 4; + for (i = 0; i < dst_bytes; i++) + dst[i] = src >> ((3-i) * 8); +} + +int +intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, + u32 *recv, int recv_size) +{ + int i; + int recv_bytes; + u32 status; + u32 aux_clock_divider; + int try, precharge = 5; + + /* The clock divider is based off the hrawclk, + * and would like to run at 2MHz. So, take the + * hrawclk value and divide by 2 and use that + * + * Note that PCH attached eDP panels should use a 125MHz input + * clock divider. + */ + /* 200 on link */ + aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ + + /* Try to wait for any previous AUX channel activity */ + for (try = 0; try < 3; try++) { + status = io_i915_READ32(ch_ctl); + if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) + break; + udelay(1000); + } + + if (try == 3) { + printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); + printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n", + io_i915_READ32(ch_ctl)); + return -1; + } + + /* Must try at least 3 times according to DP spec */ + for (try = 0; try < 5; try++) { + /* Load the send data into the aux channel data registers */ + for (i = 0; i < send_bytes; i += 4) + io_i915_WRITE32(send[i], ch_data + i); + + /* Send the command and wait for it to complete */ + io_i915_WRITE32( + DP_AUX_CH_CTL_SEND_BUSY | + DP_AUX_CH_CTL_TIME_OUT_400us | + (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | + (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | + (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); + for (;;) { + status = io_i915_READ32(ch_ctl); + if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) + break; + udelay(100); + } + + /* Clear done status and any errors */ + io_i915_WRITE32( + status | + DP_AUX_CH_CTL_DONE | + DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl); + + if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | + DP_AUX_CH_CTL_RECEIVE_ERROR)) + continue; + if (status & DP_AUX_CH_CTL_DONE) + break; + } + + if ((status & DP_AUX_CH_CTL_DONE) == 0) { + printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); + printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status); + return -1; + } + + /* Check for timeout or receive error. + * Timeouts occur when the sink is not connected + */ + if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { + printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); + printk(BIOS_SPEW, "dp_aux_ch receive error status 0x%08x\n", status); + return -1; + } + + /* Timeouts occur when the device isn't connected, so they're + * "normal" -- don't fill the kernel log with these */ + if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { + printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__); + printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status); + return -1; + } + + /* Unload any bytes sent back from the other side */ + recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> + DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); + if (recv_bytes > recv_size) + recv_bytes = recv_size; + + for (i = 0; i < recv_bytes; i += 4) + unpack_aux(io_i915_READ32(ch_data + i), + recv + i, recv_bytes - i); + + return recv_bytes; +} diff --git a/src/mainboard/kontron/come-bip2/mainboard.c b/src/mainboard/kontron/come-bip2/mainboard.c new file mode 100644 index 0000000..922061f --- /dev/null +++ b/src/mainboard/kontron/come-bip2/mainboard.c @@ -0,0 +1,210 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "onboard.h" +#include "ec.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <smbios.h> +#include <device/pci.h> +#include <ec/google/chromeec/ec.h> + +/* placeholder for evenual link post. Not sure what we'll + * do but it will look nice + */ +void mainboard_post(u8 value) +{ + /* + * What you DO NOT want to do: push every post to the EC backlight. + * it seems cute but in practice it looks like a hardware failure. + * I'm leaving this here so we don't make this mistake again later. + * And it seems to break the SMP startup. + * google_chromeec_post(value); + */ +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, X86_AX); + + switch(X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; /* eDP */ + res = 1; + break; + case 0x5f70: + switch (X86_CH) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + X86_CH); + break; + } + break; + case 0x5fac: + res = 1; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + + + +static void mainboard_init(device_t dev) +{ + /* Initialize the Embedded Controller */ + link_ec_init(); + + if (google_chromeec_get_board_version() == 0) { + /* If running on proto1 - enable reversion of gpio11. */ + u32 gpio_inv; + u16 gpio_base = pci_read_config16 + (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) & + 0xfffc; + u16 gpio_inv_addr = gpio_base + GPI_INV; + gpio_inv = inl(gpio_inv_addr); + outl(gpio_inv | (1 << 11), gpio_inv_addr); + } +} + +static int link_onboard_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + int len = 0; + + len += smbios_write_type41( + current, handle, + BOARD_LIGHTSENSOR_NAME, /* name */ + BOARD_LIGHTSENSOR_IRQ, /* instance */ + 0, /* segment */ + BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + len += smbios_write_type41( + current, handle, + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ + 0, /* segment */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + len += smbios_write_type41( + current, handle, + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ + 0, /* segment */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + return len; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = link_onboard_smbios_data; +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/kontron/come-bip2/mainboard_smi.c b/src/mainboard/kontron/come-bip2/mainboard_smi.c new file mode 100644 index 0000000..d281742 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/mainboard_smi.c @@ -0,0 +1,116 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> +#include <elog.h> + +/* Include EC functions */ +#include <ec/google/chromeec/ec.h> +#include "ec.h" + +static u8 mainboard_smi_ec(void) +{ + u8 cmd = google_chromeec_get_event(); + u32 pm1_cnt; + +#if CONFIG_ELOG_GSMI + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(smm_get_pmbase() + PM1_CNT); + pm1_cnt |= (0xf << 10); + outl(pm1_cnt, smm_get_pmbase() + PM1_CNT); + break; + } + + return cmd; +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0); + } +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + break; + case 5: + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0); + + /* Enable wake events */ + google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS); +} + +#define APMC_ACPI_EN 0xe1 +#define APMC_ACPI_DIS 0x1e + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_ACPI_EN: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS); + break; + case APMC_ACPI_DIS: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS); + break; + } + return 0; +} diff --git a/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex new file mode 100644 index 0000000..7ed2663 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/micron_4Gb_1600_1.35v_x16.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 ad 75 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/kontron/come-bip2/onboard.h b/src/mainboard/kontron/come-bip2/onboard.h new file mode 100644 index 0000000..7bc213b --- /dev/null +++ b/src/mainboard/kontron/come-bip2/onboard.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_ONBOARD_H +#define LINK_ONBOARD_H + +#define BOARD_LIGHTSENSOR_NAME "lightsensor" +#define BOARD_LIGHTSENSOR_I2C_ADDR 0x44 +#define BOARD_LIGHTSENSOR_IRQ 0 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_I2C_ADDR 0x4b +#define BOARD_TRACKPAD_IRQ 20 +#define BOARD_TRACKPAD_WAKE_GPIO 0x1c + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a +#define BOARD_TOUCHSCREEN_IRQ 22 + +#endif diff --git a/src/mainboard/kontron/come-bip2/romstage.c b/src/mainboard/kontron/come-bip2/romstage.c new file mode 100644 index 0000000..8142845 --- /dev/null +++ b/src/mainboard/kontron/come-bip2/romstage.c @@ -0,0 +1,233 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/gpio.h> +#include "ec/google/chromeec/ec.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <halt.h> +#include <tpm.h> +#include <cbfs.h> + +#include <southbridge/intel/bd82x6x/chip.h> + +void pch_enable_lpc(void) +{ + const struct device *lpc; + const struct southbridge_intel_bd82x6x_config *config = NULL; + + lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + if (!lpc) + return; + if (lpc->chip_info) + config = lpc->chip_info; + if (!config) + return; + + /* Set COM1/COM2 decode range */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); + + /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \ + GAMEL_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); +} + +void rcba_config(void) +{ + u32 reg32; + + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P3IP WLAN INTA -> PIRQB + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQF (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * TRACKPAD -> PIRQE (Edge Triggered) + * TOUCHSCREEN -> PIRQG (Edge Triggered) + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + reg32 = RCBA32(FD); + reg32 |= PCH_DISABLE_ALWAYS; + RCBA32(FD) = reg32; +} + +static uint8_t *locate_spd(void) +{ + const int gpio_vector[] = {41, 42, 43, 10, -1}; + uint8_t *spd_file; + size_t spd_file_len; + int spd_index = get_gpios(gpio_vector); + + printk(BIOS_DEBUG, "spd index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < ((spd_index + 1) * 256)) { + printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < 256) + die("Missing SPD data."); + + return spd_file + spd_index * 256; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ + { 0, 3, 0x0000 }, /* P0: Empty */ + { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */ + { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */ + { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */ + { 0, 3, 0x0000 }, /* P4: Empty */ + { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */ + { 0, 3, 0x0000 }, /* P6: Empty */ + { 0, 3, 0x0000 }, /* P7: Empty */ + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + { 1, 4, 0x0040 }, /* P8: Camera (no OC) */ + { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */ + { 0, 4, 0x0000 }, /* P10: Empty */ + { 0, 4, 0x0000 }, /* P11: Empty */ + { 0, 4, 0x0000 }, /* P12: Empty */ + { 0, 4, 0x0000 }, /* P13: Empty */ + }, + }; + *pei_data = pei_data_template; + memcpy(pei_data->spd_data[0], locate_spd(), + sizeof(pei_data->spd_data[0])); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled power usb oc pin */ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, -1 }, /* P3: SDCARD (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 1, 0, -1 }, /* P5: WWAN (no OC) */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: Camera (no OC) */ + { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ + { 0, 0, -1 }, /* P10: Empty */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ +}; + +void mainboard_get_spd(spd_raw_data *spd) { + memcpy(&spd[0], locate_spd(), 128); +} + +void mainboard_early_init(int s3resume) +{ + if (!s3resume) { + /* This is the fastest way to let users know + * the Intel CPU is now alive. + */ + google_chromeec_kbbacklight(100); + } +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex new file mode 100644 index 0000000..5beb5fc --- /dev/null +++ b/src/mainboard/kontron/come-bip2/samsung_4Gb_1600_1.35v_x16.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +f0 0a 3c 3c 01 40 83 01 +00 80 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ce 01 +00 00 00 00 00 00 6a 04 +4d 34 37 31 42 35 36 37 +34 42 48 30 2d 59 4b 30 +20 20 00 00 80 ce 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/kontron/come-bip2/thermal.h b/src/mainboard/kontron/come-bip2/thermal.h new file mode 100644 index 0000000..4a1f31b --- /dev/null +++ b/src/mainboard/kontron/come-bip2/thermal.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef LINK_THERMAL_H +#define LINK_THERMAL_H + +/* Config TDP Sensor ID */ +#define CTDP_SENSOR_ID 9 /* PECI */ + +/* Config TDP Nominal */ +#define CTDP_NOMINAL_THRESHOLD_OFF 0 +#define CTDP_NOMINAL_THRESHOLD_ON 0 + +/* Config TDP Down */ +#define CTDP_DOWN_THRESHOLD_OFF 80 +#define CTDP_DOWN_THRESHOLD_ON 90 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 100 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif

1 0

Patch set updated for coreboot: mainboard/amenia: add the inital files for amenia board
by Bora Guvendik 18 Apr '16

18 Apr '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14352 -gerrit commit 20c724db11fcd769c839cac02709fdfd30a3a4e3 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Mon Mar 14 14:19:22 2016 -0700 mainboard/amenia: add the inital files for amenia board Add amenia board files Change-Id: I6731a348b4c0550d3b9381adb5fb83719f90a5da Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 53 +++++++++ src/mainboard/intel/amenia/Kconfig.name | 3 + src/mainboard/intel/amenia/Makefile.inc | 5 + src/mainboard/intel/amenia/acpi/mainboard.asl | 49 +++++++++ src/mainboard/intel/amenia/acpi_tables.c | 47 ++++++++ src/mainboard/intel/amenia/board_info.txt | 4 + src/mainboard/intel/amenia/chromeos.c | 40 +++++++ src/mainboard/intel/amenia/chromeos.fmd | 37 +++++++ src/mainboard/intel/amenia/chromeos_ramstage.c | 31 ++++++ src/mainboard/intel/amenia/devicetree.cb | 52 +++++++++ src/mainboard/intel/amenia/dsdt.asl | 39 +++++++ src/mainboard/intel/amenia/mainboard.c | 143 +++++++++++++++++++++++++ src/mainboard/intel/amenia/romstage.c | 114 ++++++++++++++++++++ src/soc/intel/apollolake/Kconfig | 6 ++ 14 files changed, 623 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig new file mode 100644 index 0000000..f1946b5 --- /dev/null +++ b/src/mainboard/intel/amenia/Kconfig @@ -0,0 +1,53 @@ +if BOARD_INTEL_AMENIA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LPC_TPM + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_CHROMEOS + +config CHROMEOS + bool + default y + +config MAINBOARD_DIR + string + default intel/amenia + +config MAINBOARD_PART_NUMBER + string + default "Amenia" + +config MAINBOARD_VENDOR + string + default "Intel" + +config FMAP_FILE + string + default "amenia" + +config PREBUILT_SPI_IMAGE + string + default "amenia.bin.orig.a0" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config FLASHMAP_OFFSET + hex + default 0x200000 + +config MAX_CPUS + int + default 8 + +endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/Kconfig.name b/src/mainboard/intel/amenia/Kconfig.name new file mode 100644 index 0000000..ab27688 --- /dev/null +++ b/src/mainboard/intel/amenia/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_AMENIA + bool "Amenia" + diff --git a/src/mainboard/intel/amenia/Makefile.inc b/src/mainboard/intel/amenia/Makefile.inc new file mode 100644 index 0000000..00d738e --- /dev/null +++ b/src/mainboard/intel/amenia/Makefile.inc @@ -0,0 +1,5 @@ +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c diff --git a/src/mainboard/intel/amenia/acpi/mainboard.asl b/src/mainboard/intel/amenia/acpi/mainboard.asl new file mode 100644 index 0000000..76c63b7 --- /dev/null +++ b/src/mainboard/intel/amenia/acpi/mainboard.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> + +Scope (\_SB.PCI0.I2C4) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 1) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C4", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + GPIO_18_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + + } +} diff --git a/src/mainboard/intel/amenia/acpi_tables.c b/src/mainboard/intel/amenia/acpi_tables.c new file mode 100644 index 0000000..9a9cc3a --- /dev/null +++ b/src/mainboard/intel/amenia/acpi_tables.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, ARRAY_SIZE(header->oem_id)); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, ARRAY_SIZE(header->oem_table_id)); + memcpy(header->asl_compiler_id, ASLC, ARRAY_SIZE(header->asl_compiler_id)); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); +} diff --git a/src/mainboard/intel/amenia/board_info.txt b/src/mainboard/intel/amenia/board_info.txt new file mode 100644 index 0000000..b97ca15 --- /dev/null +++ b/src/mainboard/intel/amenia/board_info.txt @@ -0,0 +1,4 @@ +Vendor name: Intel +Board name: Amenia Board +Category: eval +Flashrom support: y diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c new file mode 100644 index 0000000..dabb899 --- /dev/null +++ b/src/mainboard/intel/amenia/chromeos.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <vendorcode/google/chromeos/chromeos.h> + +int get_lid_switch(void) +{ + /* Default to force open */ + return 1; +} + +/* The dev-switch is virtual */ +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} + +int get_write_protect_state(void) +{ + return 0; +} diff --git a/src/mainboard/intel/amenia/chromeos.fmd b/src/mainboard/intel/amenia/chromeos.fmd new file mode 100644 index 0000000..9c60c80 --- /dev/null +++ b/src/mainboard/intel/amenia/chromeos.fmd @@ -0,0 +1,37 @@ +FLASH 8M { + WP_RO 4M { + SI_ALL 2M { + SI_DESC 4K + bootblock@509056 32K + } + RO_SECTION@2M 2M { + FMAP 2K + RO_FRID 0x40 + RO_VPD @4K 16K + COREBOOT(CBFS) + SIGN_CSE@0x180000 64K + GBB + } + } + MISC_RW { + RW_MRC_CACHE 64K + RW_ELOG 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD 8K + } + RW_SECTION_A 0xf0000 { + VBLOCK_A 64K + FW_MAIN_A(CBFS) 768K + RW_FWID_A 64 + } + RW_SECTION_B 0xf0000 { + VBLOCK_B 64K + FW_MAIN_B(CBFS) 768K + RW_FWID_B 64 + } + DEVICE_EXTENSION@7M 1M +} + diff --git a/src/mainboard/intel/amenia/chromeos_ramstage.c b/src/mainboard/intel/amenia/chromeos_ramstage.c new file mode 100644 index 0000000..dcc6b90 --- /dev/null +++ b/src/mainboard/intel/amenia/chromeos_ramstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, 0, "write protect"}, + {-1, ACTIVE_HIGH, 0, "recovery"}, + {-1, ACTIVE_HIGH, 1, "developer"}, + {-1, ACTIVE_HIGH, 1, "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, 0, "oprom"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb new file mode 100644 index 0000000..c54e838 --- /dev/null +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -0,0 +1,52 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "3" # wifi/bt + register "pcie_rp2_clkreq_pin" = "0" # SSD + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl new file mode 100644 index 0000000..ba4e722 --- /dev/null +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + } + } + /* Mainboard Specific devices */ + #include "acpi/mainboard.asl" + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c new file mode 100644 index 0000000..9949061 --- /dev/null +++ b/src/mainboard/intel/amenia/mainboard.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <soc/gpio.h> + +/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ +static const struct pad_config amenia_gpios[] = { + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */ + + PAD_CFG_GPI(GPIO_9, UP_20K, DEEP), /* SPI_TPM_IRQ_N */ + PAD_CFG_GPI_SCI(GPIO_11, UP_20K, DEEP, LEVEL, NONE), /* SOC_WAKE_SCI_N */ + PAD_CFG_GPI_APIC(GPIO_18, UP_20K, DEEP, LEVEL, NONE), /* Trackpad_INT_N */ + PAD_CFG_GPI_APIC(GPIO_19, UP_20K, DEEP, LEVEL, NONE), /* Audio_Jack_Present_N */ + PAD_CFG_GPI_APIC(GPIO_21, UP_20K, DEEP, LEVEL, NONE), /* TCH_INT_N */ + PAD_CFG_GPI_APIC(GPIO_22, UP_20K, DEEP, LEVEL, NONE), /* EC_SOC_WAKE_1P8_N */ + PAD_CFG_GPO(GPIO_23, 1, DEEP), /* GPS_NSTANDBY */ + PAD_CFG_GPO(GPIO_24, 1, DEEP), /* SSD_SATA_DEVSLP */ + PAD_CFG_GPI_APIC(GPIO_30, UP_20K, DEEP, LEVEL, NONE), /* EC_KBD_IRQ_SOC_N */ + PAD_CFG_NF(GPIO_32, NATIVE, DEEP, NF5), /* GPS_SUSCLK_32K */ + PAD_CFG_GPI(GPIO_33, UP_20K, DEEP), /* EC_KBD_IRQ_SOC_N */ + PAD_CFG_GPO(GPIO_36, 0, DEEP), /* TOUCH_PNL_RST */ + PAD_CFG_NF(GPIO_37, NATIVE, DEEP, NF1), /* SOC_BUZZER */ + PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS_B */ + + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* GPS_UART_RXD */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* GPS_UART_TXD */ + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), /* GPS_UART_RTS_B */ + PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), /* GPS_UART_CTS_N */ + + PAD_CFG_GPI_SMI(GPIO_49, UP_20K, DEEP, LEVEL, NONE), /* EC_SMI_N */ + PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* SPI_WP_STAT */ + + PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* DMIC_CLK_A1 */ + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* DMIC_CLK_B1 */ + PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* DMIC_DATA_1 */ + PAD_CFG_NF(GPIO_82, NATIVE, DEEP, NF1), /* DMIC_CLK_AB2 */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* DMIC_DATA_2 */ + PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* MCLK */ + + PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1), /* I2S2_BCLK_AMP */ + PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1), /* I2S2_SYNC_AMP */ + PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1), /* I2S2_SDI_AMP */ + PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1), /* I2S2_SDO_AMP */ + PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ + PAD_CFG_GPI_APIC(GPIO_116, UP_20K, DEEP, LEVEL, INVERT), /* AUDIO_CODEC_IRQ_N */ + + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* I2C_SDA for Audio Codec */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* I2C_SCL for Audio Codec */ + + PAD_CFG_NF(GPIO_128, UP_5K, DEEP, NF1), /* I2C_SDA for ALS */ + PAD_CFG_NF(GPIO_129, UP_5K, DEEP, NF1), /* I2C_SCL for ALS */ + + PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1), /* I2C_SDA for Touch Screen */ + PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1), /* I2C_SCL for Touchscreen */ + + PAD_CFG_NF(GPIO_132, UP_2K, DEEP, NF1), /* I2C_SDA for Trackpad */ + PAD_CFG_NF(GPIO_133, UP_2K, DEEP, NF1), /* I2C_SCL for Trackpad */ + + PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2), /* I2S6_BCLK_Codec */ + PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2), /* I2S6_SYNC_Codec */ + PAD_CFG_NF(GPIO_148, NATIVE, DEEP, NF2), /* I2S6_SDI_Codec */ + PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2), /* I2S6_SDO_Codec */ + + PAD_CFG_GPO(GPIO_150, 1, DEEP), /* WIFI_PERST_1P8_N */ + PAD_CFG_GPI(GPIO_151, UP_20K, DEEP), /* RSVD (ISH_BASE_ACCEL_INT_N) */ + PAD_CFG_GPI(GPIO_152, UP_20K, DEEP), /* RSVD (ALS_IRQ_N) */ + + PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ + PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ + + + PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + PAD_CFG_NF(GPIO_177, NATIVE, DEEP, NF1), /* SDCARD_CD_B */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */ + + + /* Configure eMMC pins for proper pull UP/DN */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC0_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC0_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC0_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC0_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC0_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC0_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC0_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ + + PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ + PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ + + PAD_CFG_NF(GPIO_205, NATIVE, DEEP, NF1), /* PCIE_WLAN_WAKE3_N */ + PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_SSD_WAKE0_N */ + PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), /* SSD CLKREQ */ + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), /* Wifi CLKREQ */ + + PAD_CFG_GPO(PMU_BATLOW_B, 0, DEEP), /* EMMC_PLTRST_N ?? */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), /* LPC_CLKRUN_N */ + + PAD_CFG_NF(GPIO_199,NATIVE,DEEP,NF2), /* HV_DDI1_HPD */ + PAD_CFG_NF(GPIO_200,NATIVE,DEEP,NF2), /* HV_DDI0_HPD */ + PAD_CFG_NF(PMC_SPI_FS1,NATIVE,DEEP,NF2), /* HV_DDI2_HPD */ + +}; + +static void mainboard_init(void *chip_info) +{ + gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/intel/amenia/romstage.c b/src/mainboard/intel/amenia/romstage.c new file mode 100644 index 0000000..d08b343 --- /dev/null +++ b/src/mainboard/intel/amenia/romstage.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <soc/fsp/FspmUpd.h> + +/* Channel 0 PHY to DUnit DQ mapping */ +static const uint8_t swizzling_ch0_amenia[] = { + 9, 14, 12, 13, 10, 11, 8, 15, 7, 3, 5, 2, 6, 0, 1, 4, + 28, 24, 26, 27, 29, 30, 31, 25, 20, 22, 23, 16, 19, 17, 18, 21, +}; + +/* Channel 1 PHY to DUnit DQ mapping */ +static const uint8_t swizzling_ch1_amenia[] = { + 6, 7, 5, 4, 3, 1, 0, 2, 12, 10, 11, 13, 14, 8, 9, 15, + 16, 22, 23, 20, 18, 17, 19, 21, 30, 28, 29, 25, 24, 26, 27, 31, +}; + +/* Channel 2 PHY to DUnit DQ mapping */ +static const uint8_t swizzling_ch2_amenia[] = { + 15, 9, 8, 11, 14, 13, 12, 10, 4, 3, 7, 5, 6, 1, 0, 2, + 25, 28, 30, 31, 26, 27, 24, 29, 20, 23, 22, 21, 18, 19, 16, 17, +}; + +/* Channel 3 PHY to DUnit DQ mapping */ +static const uint8_t swizzling_ch3_amenia[] = { + 2, 1, 6, 7, 5, 4, 3, 0, 11, 10, 8, 9, 12, 15, 13, 14, + 17, 23, 19, 16, 21, 22, 20, 18, 31, 29, 26, 25, 28, 27, 24, 30, +}; + +static void amenia_fill_memory_params(struct FSP_M_CONFIG *cfg) +{ + cfg->Profile = 11; /* 0xB:LPDDR4_2400_24_22_22 */ + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + cfg->Ch0_RankEnable = 0x1; + cfg->Ch0_DeviceWidth = 0x1; + cfg->Ch0_DramDensity = 0x2; + cfg->Ch0_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch0_TristateClk1 = 0; + cfg->Ch0_Mode2N = 0; + cfg->Ch0_OdtLevels = 0; + cfg->Ch1_RankEnable = 0x1; + cfg->Ch1_DeviceWidth = 0x1; + cfg->Ch1_DramDensity = 0x2; + cfg->Ch1_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch1_TristateClk1 = 0; + cfg->Ch1_Mode2N = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch2_RankEnable = 0x1; + cfg->Ch2_DeviceWidth = 0x1; + cfg->Ch2_DramDensity = 0x2; + cfg->Ch2_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch2_TristateClk1 = 0; + cfg->Ch2_Mode2N = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch3_RankEnable = 0x1; + cfg->Ch3_DeviceWidth = 0x1; + cfg->Ch3_DramDensity = 0x2; + cfg->Ch3_Option = 0x3; /* Bank Address Hashing enabled */ + cfg->Ch3_TristateClk1 = 0; + cfg->Ch3_Mode2N = 0; + cfg->Ch3_OdtLevels = 0; + + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_amenia, + sizeof(swizzling_ch0_amenia)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_amenia, + sizeof(swizzling_ch1_amenia)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling_ch2_amenia, + sizeof(swizzling_ch2_amenia)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling_ch3_amenia, + sizeof(swizzling_ch3_amenia)); +} + +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + struct FSP_M_CONFIG *cfg = &memupd->FspmConfig; + + cfg->Package = 1; /* 0x1:BGA */ + cfg->MemoryDown = 1; + cfg->DDR3LPageSize = 0; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0x36; + cfg->SliceHashMask = 0x9; + cfg->InterleavedMode = 2; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->RmtCheckRun = 0; + cfg->RmtMarginCheckScaleHighThreshold = 0; + cfg->MemorySizeLimit = 0x1800; /* Limit to 6GB */ + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + + amenia_fill_memory_params(cfg); +} diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 10e8b0d..7cd548b 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -38,6 +38,12 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select HAVE_MONOTONIC_TIMER select PLATFORM_USES_FSP2_0 + select HAVE_HARD_RESET + select SOC_INTEL_COMMON + +config SOC_INTEL_COMMON_RESET + bool + default y config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

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coreboot-gerrit April 2016