coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: drivers/xgi: Switch to src/drivers/[X]/[Y]/ scheme
by gerrit＠coreboot.org 19 Apr '16

19 Apr '16

the following patch was just integrated into master: commit 431aa6dd1f49724f8998bc1092aff3d2185b30f7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:28:55 2016 -0800 drivers/xgi: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14049 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14049 for details. -gerrit

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Patch merged into coreboot/master: drivers/parade: Switch to src/drivers/[X]/[Y]/ scheme
by gerrit＠coreboot.org 19 Apr '16

19 Apr '16

the following patch was just integrated into master: commit efb866f519baf2e4ed59256d06cfb5d4fde4e30f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 19 01:30:01 2016 +0200 drivers/parade: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I1313797d60925cc0627987936199e62073c264d7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14061 for details. -gerrit

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Patch merged into coreboot/master: drivers/ti: Switch to src/drivers/[X]/[Y]/ scheme
by gerrit＠coreboot.org 19 Apr '16

19 Apr '16

the following patch was just integrated into master: commit 7c85168c45fe891670c0b9570bd77e01f6dd6957 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:29:45 2016 -0800 drivers/ti: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14050 for details. -gerrit

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Patch merged into coreboot/master: kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme
by gerrit＠coreboot.org 19 Apr '16

19 Apr '16

the following patch was just integrated into master: commit 86ddd732bd82b84724883b1f1579e18790611fe5 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:22:28 2016 -0800 kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Also, fix up the following driver subdirectories by switching to the src/drivers/[X]/[Y]/ scheme as these are hard requirements for the main change: * drivers/intel * drivers/pc80 * drivers/dec Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14047 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14047 for details. -gerrit

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Patch set updated for coreboot: ensure correct byte ordering for cbfs segment list
by George Trudeau 19 Apr '16

19 Apr '16

George Trudeau (george.trudeau(a)usherbrooke.ca) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14294 -gerrit commit e4f113542d81559b8758af3059454641f906f446 Author: George Trudeau <george.trudeau(a)usherbrooke.ca> Date: Mon Apr 4 00:19:02 2016 -0400 ensure correct byte ordering for cbfs segment list Decode each cbfs_payload_segment into native byte order during segments iteration. Note : List ordering has been changed, segments are now always inserted at the end. cbfs_serialized.h PAYLOAD_SEGMENT definitions have been changed to their standard order (big-endian). Change-Id: Icb3c6a7da2d253685a3bc157bc7f5a51183c9652 Signed-off-by: George Trudeau <george.trudeau(a)usherbrooke.ca> --- src/commonlib/include/commonlib/cbfs_serialized.h | 10 +-- src/lib/selfboot.c | 95 +++++++++++++---------- 2 files changed, 60 insertions(+), 45 deletions(-) diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index c1a1c3b..c01ba1a 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -175,11 +175,11 @@ struct cbfs_payload { struct cbfs_payload_segment segments; }; -#define PAYLOAD_SEGMENT_CODE 0x45444F43 -#define PAYLOAD_SEGMENT_DATA 0x41544144 -#define PAYLOAD_SEGMENT_BSS 0x20535342 -#define PAYLOAD_SEGMENT_PARAMS 0x41524150 -#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 +#define PAYLOAD_SEGMENT_CODE 0x434F4445 +#define PAYLOAD_SEGMENT_DATA 0x44415441 +#define PAYLOAD_SEGMENT_BSS 0x42535320 +#define PAYLOAD_SEGMENT_PARAMS 0x50415241 +#define PAYLOAD_SEGMENT_ENTRY 0x454E5452 struct cbfs_optionrom { uint32_t compression; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 23eda14..75d6725 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,6 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> + * Copyright (C) 2016 George Trudeau <george.trudeau(a)usherbrooke.ca> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,9 +16,9 @@ */ #include <commonlib/compression.h> +#include <commonlib/endian.h> #include <console/console.h> #include <cpu/cpu.h> -#include <endian.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -209,68 +210,89 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) return ret; } +/* Decode a serialized cbfs payload segment + * from memory into native endianness. + */ +static void cbfs_decode_payload_segment(struct cbfs_payload_segment *segment, + const struct cbfs_payload_segment *src) +{ + segment->type = read_be32(&src->type); + segment->compression = read_be32(&src->compression); + segment->offset = read_be32(&src->offset); + segment->load_addr = read_be64(&src->load_addr); + segment->len = read_be32(&src->len); + segment->mem_len = read_be32(&src->mem_len); +} static int build_self_segment_list( struct segment *head, struct cbfs_payload *cbfs_payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; + struct cbfs_payload_segment *current_segment, *first_segment, segment; + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + first_segment = &cbfs_payload->segments; + + for (current_segment = first_segment;; ++current_segment) { + printk(BIOS_DEBUG, + "Loading segment from rom address 0x%p\n", + current_segment); + + cbfs_decode_payload_segment(&segment, current_segment); + + switch (segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); - new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); + segment.type == PAYLOAD_SEGMENT_CODE + ? "code" : "data", segment.compression); + new = malloc(sizeof(*new)); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; new->s_srcaddr = (uintptr_t) ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); + + segment.offset; + new->s_filesz = segment.len; + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; printk(BIOS_DEBUG, - " cleaned up filesize 0x%lx\n", - new->s_filesz); + " cleaned up filesize 0x%lx\n", + new->s_filesz); } break; case PAYLOAD_SEGMENT_BSS: printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + (intptr_t)segment.load_addr, segment.mem_len); + new = malloc(sizeof(*new)); new->s_filesz = 0; new->s_srcaddr = (uintptr_t) ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + + segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: - printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + printk(BIOS_DEBUG, " Entry Point 0x%p\n", (void *) + (intptr_t)segment.load_addr); + + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -282,24 +304,17 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", + segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; - - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert new segment at the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } return 1;

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Patch merged into coreboot/master: Makefile.inc: Stop running git repeatedly for each build
by gerrit＠coreboot.org 19 Apr '16

19 Apr '16

the following patch was just integrated into master: commit 3812597c668b795d4fc85578021e501f2a56f6b9 Author: Martin Roth <martinroth(a)google.com> Date: Tue Apr 19 20:15:16 2016 -0600 Makefile.inc: Stop running git repeatedly for each build Currently, the coreboot makefiles repeatedly run git to try to set the KERNELVERSION variable and to fetch the submodules. This happens three times for every build. By exporting a variable, we can catch this on recursive makes and not run each of these steps again. Change-Id: I85ab867b40e80c36bd94d48510ffe3252c6cf93f Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14392 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/14392 for details. -gerrit

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Patch set updated for coreboot: ensure correct byte ordering for cbfs segment list
by George Trudeau 19 Apr '16

19 Apr '16

George Trudeau (george.trudeau(a)usherbrooke.ca) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14294 -gerrit commit 6e387d04e1aee5da26d67741ef0640956b13f8ea Author: George Trudeau <george.trudeau(a)usherbrooke.ca> Date: Mon Apr 4 00:19:02 2016 -0400 ensure correct byte ordering for cbfs segment list Decode each cbfs_payload_segment into native byte order during segments iteration. Note : List ordering has been changed, segments are now always inserted at the end. cbfs_serialized.h PAYLOAD_SEGMENT definitions have been changed to their standard order (big-endian). Change-Id: Icb3c6a7da2d253685a3bc157bc7f5a51183c9652 Signed-off-by: George Trudeau <george.trudeau(a)usherbrooke.ca> --- src/commonlib/include/commonlib/cbfs_serialized.h | 10 +-- src/lib/selfboot.c | 95 +++++++++++++---------- 2 files changed, 60 insertions(+), 45 deletions(-) diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/include/commonlib/cbfs_serialized.h index c1a1c3b..a2fed6d 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/include/commonlib/cbfs_serialized.h @@ -175,11 +175,11 @@ struct cbfs_payload { struct cbfs_payload_segment segments; }; -#define PAYLOAD_SEGMENT_CODE 0x45444F43 -#define PAYLOAD_SEGMENT_DATA 0x41544144 -#define PAYLOAD_SEGMENT_BSS 0x20535342 -#define PAYLOAD_SEGMENT_PARAMS 0x41524150 -#define PAYLOAD_SEGMENT_ENTRY 0x52544E45 +#define PAYLOAD_SEGMENT_CODE 0X434F4445 +#define PAYLOAD_SEGMENT_DATA 0X44415441 +#define PAYLOAD_SEGMENT_BSS 0X42535320 +#define PAYLOAD_SEGMENT_PARAMS 0X50415241 +#define PAYLOAD_SEGMENT_ENTRY 0X454E5452 struct cbfs_optionrom { uint32_t compression; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 23eda14..75d6725 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,6 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> + * Copyright (C) 2016 George Trudeau <george.trudeau(a)usherbrooke.ca> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,9 +16,9 @@ */ #include <commonlib/compression.h> +#include <commonlib/endian.h> #include <console/console.h> #include <cpu/cpu.h> -#include <endian.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -209,68 +210,89 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) return ret; } +/* Decode a serialized cbfs payload segment + * from memory into native endianness. + */ +static void cbfs_decode_payload_segment(struct cbfs_payload_segment *segment, + const struct cbfs_payload_segment *src) +{ + segment->type = read_be32(&src->type); + segment->compression = read_be32(&src->compression); + segment->offset = read_be32(&src->offset); + segment->load_addr = read_be64(&src->load_addr); + segment->len = read_be32(&src->len); + segment->mem_len = read_be32(&src->mem_len); +} static int build_self_segment_list( struct segment *head, struct cbfs_payload *cbfs_payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; + struct cbfs_payload_segment *current_segment, *first_segment, segment; + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + first_segment = &cbfs_payload->segments; + + for (current_segment = first_segment;; ++current_segment) { + printk(BIOS_DEBUG, + "Loading segment from rom address 0x%p\n", + current_segment); + + cbfs_decode_payload_segment(&segment, current_segment); + + switch (segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); - new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); + segment.type == PAYLOAD_SEGMENT_CODE + ? "code" : "data", segment.compression); + new = malloc(sizeof(*new)); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; new->s_srcaddr = (uintptr_t) ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); + + segment.offset; + new->s_filesz = segment.len; + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; printk(BIOS_DEBUG, - " cleaned up filesize 0x%lx\n", - new->s_filesz); + " cleaned up filesize 0x%lx\n", + new->s_filesz); } break; case PAYLOAD_SEGMENT_BSS: printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + (intptr_t)segment.load_addr, segment.mem_len); + new = malloc(sizeof(*new)); new->s_filesz = 0; new->s_srcaddr = (uintptr_t) ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + + segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: - printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + printk(BIOS_DEBUG, " Entry Point 0x%p\n", (void *) + (intptr_t)segment.load_addr); + + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -282,24 +304,17 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", + segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; - - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } - - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert new segment at the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } return 1;

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Patch set updated for coreboot: payloads/GRUB2: Add Kconfig option for grub.cfg
by Martin Roth 19 Apr '16

19 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5109 -gerrit commit 3a1c1b30c19def52c32f328006be24fb60c8d9ce Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Feb 3 23:09:30 2014 +0100 payloads/GRUB2: Add Kconfig option for grub.cfg Change-Id: I5480d6a5f2a6bbae4222e05bbe92eb717e1aff65 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/GRUB2/Kconfig | 23 +++++++++++++++++++++++ payloads/external/Makefile.inc | 4 ++++ 2 files changed, 27 insertions(+) diff --git a/payloads/external/GRUB2/Kconfig b/payloads/external/GRUB2/Kconfig index 04f0fa9..b7d5385 100644 --- a/payloads/external/GRUB2/Kconfig +++ b/payloads/external/GRUB2/Kconfig @@ -24,4 +24,27 @@ config GRUB2_EXTRA_MODULES config PAYLOAD_FILE default "payloads/external/GRUB2/grub2/build/default_payload.elf" +config GRUB2_INCLUDE_RUNTIME_CONFIG_FILE + bool "Include GRUB2 runtime config file into ROM image" + depends on PAYLOAD_GRUB2 + default n + help + The GRUB2 payload reads the runtime configuration file from the image + stored on the flash ROM chip. Without that, it’ll just drop into a + rescue shell. + + This configuration may need to be coreboot specific. + + Select this option, if you want to include the GRUB2 runtime + configuration file into the image as `etc/grub.cfg`. + + You can add this file manually too. + +config GRUB2_RUNTIME_CONFIG_FILE + string "Path of grub.cfg" + depends on GRUB2_INCLUDE_RUNTIME_CONFIG_FILE + default "grub.cfg" + help + The path of the GRUB2 runtime configuration file to be added to CBFS. + endif diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 26a5613..3e5713c 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -50,6 +50,10 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_revision payload_revision-file := $(PAYLOAD_VERSION) payload_revision-type := raw +cbfs-files-$(CONFIG_GRUB2_INCLUDE_RUNTIME_CONFIG_FILE) += etc/grub.cfg +etc/grub.cfg-file := $(CONFIG_GRUB2_RUNTIME_CONFIG_FILE) +etc/grub.cfg-type := raw + SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(top)/$(DOTCONFIG) $(MAKE) -C payloads/external/SeaBIOS \

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Patch set updated for coreboot: intel/fsp_broadwell_de: fix SPD CBFS file type
by Stef van Os 19 Apr '16

19 Apr '16

Stef van Os (stef.van.os(a)prodrive-technologies.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14415 -gerrit commit 36422308dcd065bfcb0178fee4e1012b4488b5dc Author: Stef van Os <stef.van.os(a)prodrive-technologies.com> Date: Tue Apr 19 14:11:11 2016 +0200 intel/fsp_broadwell_de: fix SPD CBFS file type File type for SPD in this soc is defined as CBFS_TYPE_RAW in Makefile, but CBFS_TYPE_SPD in code. Causes DDR SPD not to be loaded on memory down. Tested on Prodrive Technologies Broadwell-D 1548 module: http://prodrive-technologies.com/amc-ix5-intel-broadwell-de-platform/ Change-Id: I44525b4742b3f93d33f0c5bd9ed642c6fb06f23f Signed-off-by: Stef van Os <stef.van.os(a)prodrive-technologies.com> --- src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index cab4b59..7a9e8f5 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -62,16 +62,16 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData) if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT)) UpdData->MemDownCh0Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT)) UpdData->MemDownCh0Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT)) UpdData->MemDownCh1Dimm0SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL); if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT)) UpdData->MemDownCh1Dimm1SpdPtr - = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_RAW, NULL); + = (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL); } else { UpdData->MemDownEnable = 0; }

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Patch set updated for coreboot: AGESA boards: Split dispatcher to romstage and ramstage
by Kyösti Mälkki 19 Apr '16

19 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14417 -gerrit commit f4833474a4847b153d9af3440a211b34b9338b77 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:18:02 2016 +0300 AGESA boards: Split dispatcher to romstage and ramstage The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/buildOpts.c | 17 -- src/mainboard/amd/inagua/buildOpts.c | 15 -- src/mainboard/amd/olivehill/buildOpts.c | 12 - src/mainboard/amd/parmer/buildOpts.c | 12 - src/mainboard/amd/persimmon/buildOpts.c | 15 -- src/mainboard/amd/south_station/buildOpts.c | 15 -- src/mainboard/amd/thatcher/buildOpts.c | 12 - src/mainboard/amd/torpedo/buildOpts.c | 16 -- src/mainboard/amd/union_station/buildOpts.c | 15 -- src/mainboard/asrock/e350m1/buildOpts.c | 16 -- src/mainboard/asrock/imb-a180/buildOpts.c | 12 - src/mainboard/asus/f2a85-m/buildOpts.c | 12 - src/mainboard/asus/f2a85-m_le/buildOpts.c | 12 - src/mainboard/bap/ode_e20XX/buildOpts.c | 13 -- src/mainboard/biostar/am1ml/buildOpts.c | 12 - src/mainboard/gizmosphere/gizmo/buildOpts.c | 15 -- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 13 -- src/mainboard/hp/abm/buildOpts.c | 12 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 12 - src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 15 -- src/mainboard/lenovo/g505s/buildOpts.c | 12 - src/mainboard/lippert/frontrunner-af/buildOpts.c | 15 -- src/mainboard/lippert/toucan-af/buildOpts.c | 15 -- src/mainboard/pcengines/apu1/buildOpts.c | 15 -- src/mainboard/supermicro/h8qgi/buildOpts.c | 12 - src/mainboard/supermicro/h8scm/buildOpts.c | 12 - src/mainboard/tyan/s8226/buildOpts.c | 12 - src/vendorcode/amd/agesa/Makefile.inc | 5 + src/vendorcode/amd/agesa/common/agesa-entry-cfg.h | 86 +++++++ src/vendorcode/amd/agesa/common/agesa-entry.c | 177 +++++++++++++++ .../amd/agesa/f10/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f10/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f12/Include/OptionDmiInstall.h | 2 - .../agesa/f12/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f12/Include/PlatformInstall.h | 246 +------------------- .../amd/agesa/f14/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f14/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f14/Include/PlatformInstall.h | 248 +------------------- .../amd/agesa/f15/Include/OptionDmiInstall.h | 2 - .../agesa/f15/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 - .../agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15tn/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f16kb/Include/OptionDmiInstall.h | 2 - .../agesa/f16kb/Include/OptionL3FeaturesInstall.h | 2 - .../f16kb/Include/OptionPrefetchModeInstall.h | 2 - .../amd/agesa/f16kb/Include/PlatformInstall.h | 251 +-------------------- 48 files changed, 278 insertions(+), 1621 deletions(-) diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index f69f005..0b08cc6 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,7 +26,6 @@ */ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE @@ -153,24 +152,9 @@ #define BLDCFG_PSTATE_HPC_MODE FALSE #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap -/* - * Agesa entry points used in this implementation. - */ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE /***************************************************************************** @@ -395,7 +379,6 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterfaceStub.h" diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 57590a2..980fb3e 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 18e403f..d558694 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 41b3e39..e5637d0 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 23e2706..915303c 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 94d842a..69b8a87 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index b42d9a1..16817c2 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -83,20 +82,6 @@ //For revision C single-link processors #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /***************************************************************************** * Define the RELEASE VERSION string @@ -230,7 +215,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 140ece4..83049b6 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -103,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* * Agesa configuration values selection. @@ -246,7 +231,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 742646c..ea47cec 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 83f96f9..755505b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c index c6810f1..8b01f24 100644 --- a/src/mainboard/asus/f2a85-m_le/buildOpts.c +++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 075fe57..0e98517 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 8279802..9b62536 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -103,20 +103,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -220,7 +206,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 96d59db..05889cb 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -176,17 +176,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -256,7 +245,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8d02f03..23457d6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 73673ef..48b9118 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> @@ -115,20 +114,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * AGESA entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 7b491d4..19ea01e 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 50cf4cf..52b8f52 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index f6e654a..cbc7bd6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index 1403999..2f96f78 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -339,17 +338,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #include "SanMarinoInstall.h" diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 4a3d808..cdefa03 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 02d9063..4a304be 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -5,3 +5,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb + +ifeq ($(CONFIG_CPU_AMD_AGESA),y) +romstage-y += common/agesa-entry.c +ramstage-y += common/agesa-entry.c +endif diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h new file mode 100644 index 0000000..e882f2e --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -0,0 +1,86 @@ +#ifndef AGESA_ENTRY_CFG_H +#define AGESA_ENTRY_CFG_H + + +#if defined(__PRE_RAM__) + +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE + +/* Not implemented in coreboot romstage. */ +#define AGESA_ENTRY_INIT_RECOVERY FALSE + +#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +/* Move to ramstage? */ +#define AGESA_ENTRY_INIT_ENV TRUE + +#else + +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +#endif + +/* Not required. */ +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +/* Required for any multi-core. */ +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/* Defaults below. */ + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#endif + +#endif /* AGESA_ENTRY_CFG_H */ diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c new file mode 100644 index 0000000..e722fc1 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -0,0 +1,177 @@ +#include <Porting.h> +#include <AMD.h> +#include <AGESA.h> + +#include "CommonReturns.h" + +#include <heapManager.h> +#include <CreateStruct.h> + +#include <Options.h> + +#include <agesa-entry-cfg.h> + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h index 2ad7792..232d407 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h @@ -60,8 +60,6 @@ #define USER_DMI_OPTION &GetDmiInfoMain #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #ifdef OPTION_FAMILY10H diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h index c084924..a7149f0 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h @@ -79,8 +79,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h index 410d3cb..ead4fce 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h index f3ef633..7f3ac07 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 14dd179..2b99660 100644 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -52,30 +52,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature @@ -91,61 +67,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2268,6 +2189,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2484,171 +2407,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h index 31111e3..eb4bc91 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h @@ -66,8 +66,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h index d98300f..175482b 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h @@ -97,8 +97,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h index 8641589..9a8bd68 100644 --- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h @@ -51,31 +51,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -90,62 +65,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -2149,12 +2068,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess #endif - /***************************************************************************** * * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2329,170 +2249,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h index a6d48b3..b09a58f 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h @@ -64,8 +64,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h index 5804f1d..4a73c40 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h @@ -94,8 +94,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h index 38ec4ad..0e6f1c8 100644 --- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h @@ -49,31 +49,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -88,61 +63,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2249,6 +2169,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2499,171 +2421,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h index fb1b54d..541cee9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h index 5d188e2..203b9e2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h index eca567b..af5c8b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,61 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2618,6 +2538,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2883,171 +2805,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h index ce8ef06..e0b09b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h @@ -75,8 +75,6 @@ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_DMI_AP_GET_TYPE4_TYPE7 #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #endif diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h index 8d34603..3323fea 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h @@ -57,8 +57,6 @@ #if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE) #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h index aa510aa..711b1a3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h @@ -57,8 +57,6 @@ #if OPTION_PREFETCH_MODE == TRUE #if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_PREFETCH_MODE_AP_TASK #define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask}, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 1295888..afe15b6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,62 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -1727,6 +1646,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2008,174 +1929,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #if OPTION_DATA_EYE == TRUE - { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye }, - #endif - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK

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coreboot-gerrit April 2016