coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

1 participants
1140 discussions

New patch to review for coreboot: intel 82801dx/gx/ix: Commit SMM relocation code to DRAM
by Kyösti Mälkki 04 Dec '16

04 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17712 -gerrit commit 881b9296472d2a54c487359cc26ff88396102e13 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 22:17:37 2016 +0200 intel 82801dx/gx/ix: Commit SMM relocation code to DRAM Make sure relocation code reaches DRAM before issuing any SMIs. Snooping and cache coherency may have undefined behaviour as CPUs do not have uniform MTRR layout yet. Change-Id: I47a7d684e05ff8c1c2f1f6a5bf8c0bbc561d9eac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801dx/smi.c | 1 + src/southbridge/intel/i82801gx/smi.c | 1 + src/southbridge/intel/i82801ix/smi.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index e8b8ce7..71ef5fd 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -252,6 +252,7 @@ static void smm_relocate(void) /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); + wbinvd(); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 01fbbfb..3487aab 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -252,6 +252,7 @@ static void smm_relocate(void) /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); + wbinvd(); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index dd0915a..358a1a9 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -256,6 +256,7 @@ static void smm_relocate(void) /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); + wbinvd(); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status());

1 0

Patch set updated for coreboot: drivers/r8168: Read default MAC address from CBFS
by Damien Zammit 04 Dec '16

04 Dec '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17672 -gerrit commit d58b59ece7d57b92a5fec199a724298d12fe7700 Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Dec 1 23:29:34 2016 +1100 drivers/r8168: Read default MAC address from CBFS This driver applies to 10ec:8168 Previously, this driver resetted the nic and set a hardcoded MAC address. Now the driver reads a default MAC address from CBFS in the form of a string: echo -n "xx:xx:xx:xx:xx:xx" > macaddress and store the macaddress file in CBFS with the same name. UNTESTED: Please test Change-Id: If1af91120fa3efca3f1406334a83ed1e59fbdaf9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/drivers/net/r8168.c | 119 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 93 insertions(+), 26 deletions(-) diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 1e6db57..2292ef1 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 Google Inc. * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify @@ -14,11 +15,14 @@ */ /* - * This driver forces the 10ec:8168 device to reset so that it goes - * into a proper power state, also programs a default MAC address + * This driver resets the 10ec:8168 NIC then tries to read + * "macaddress" string XX:XX:XX:XX:XX:XX from CBFS. + * If no MAC is found, it programs a default MAC address in the device * so that if the EEPROM/efuse is unconfigured it still has a default MAC. */ +#include <cbfs.h> +#include <string.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -36,26 +40,70 @@ #define CFG_9346_LOCK 0x00 #define CFG_9346_UNLOCK 0xc0 -static void r8168_init(struct device *dev) +static u8 get_hex_digit(const u8 c) { - u32 i; - const u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + u8 ret = 0; - /* Get the resource of the NIC mmio */ - struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); - u16 nic_port = (u16)nic_res->base; + ret = c - '0'; + if (ret > 0x09) { + ret = c - 'A' + 0x0a; + if (ret > 0x0f) + ret = c - 'a' + 0x0a; + } + if (ret > 0x0f) { + printk(BIOS_DEBUG, "Error: Invalid hex digit found: " + "%c - 0x%02x\n", (char)c, c); + ret = 0; + } + return ret; +} - /* Ensble but do not set bus master. That's dangerous on a NIC. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); +static void get_mac_address(u8 *macaddr, const u8 *strbuf) +{ + size_t offset = 0; + int i; + + if ( (*(strbuf + 2) != ':') || (*(strbuf + 5) != ':') || + (*(strbuf + 8) != ':') || (*(strbuf + 11) != ':') || + (*(strbuf + 14) != ':') ) { + printk(BIOS_ERR, "r8168: ignore invalid MAC address in cbfs\n"); + return; + } + + for (i = 0; i < 6; i++) { + macaddr[i] = 0; + macaddr[i] |= get_hex_digit(*(strbuf + offset)) << 4; + macaddr[i] |= get_hex_digit(*(strbuf + offset + 1)); + offset += 3; + } +} + +#define MACSTRLEN 17 + +static void program_mac_address(struct device *dev, u16 io_base) +{ + struct cbfsf fh; + uint32_t matchraw = CBFS_TYPE_RAW; + u8 macstrbuf[MACSTRLEN] = { 0 }; + int i = 0; + u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + + if (cbfs_boot_locate(&fh, "macaddress", &matchraw)) { + printk(BIOS_ERR, "r8168: 'macaddress' not found in CBFS, " + "using default 00:e0:4c:00:c0:b0\n"); + } + if (rdev_readat(&fh.data, macstrbuf, 0, MACSTRLEN) != MACSTRLEN) { + printk(BIOS_ERR, "r8168: Error reading MAC from CBFS\n"); + } else { + get_mac_address(mac, macstrbuf); + } /* Reset NIC */ printk(BIOS_DEBUG, "r8168: Resetting NIC..."); - outb(CMD_REG_RESET, nic_port + CMD_REG); + outb(CMD_REG_RESET, io_base + CMD_REG); - i = 0; - /* Poll for reset, with 1s timeout */ - while (i < NIC_TIMEOUT && (inb(nic_port + CMD_REG) & CMD_REG_RESET)) { + /* Poll for reset, with 1sec timeout */ + while (i < NIC_TIMEOUT && (inb(io_base + CMD_REG) & CMD_REG_RESET)) { udelay(1000); if (++i >= NIC_TIMEOUT) printk(BIOS_DEBUG, "timeout waiting for nic to reset\n"); @@ -63,20 +111,39 @@ static void r8168_init(struct device *dev) if (i < NIC_TIMEOUT) printk(BIOS_DEBUG, "done\n"); - /* Unlock config regs */ - outb(CFG_9346_UNLOCK, nic_port + CFG_9346); - - /* Set MAC address 00:e0:4c:00:c0:b0 - * NB: only 4-byte write accesses allowed - */ - outl(mac[4] | mac[5] << 8, nic_port + 4); - inl(nic_port + 4); + printk(BIOS_DEBUG, "r8168: Programming MAC Address..."); - outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, nic_port); - inl(nic_port); + /* Disable register protection */ + outb(CFG_9346_UNLOCK, io_base + CFG_9346); + /* Set MAC address: only 4-byte write accesses allowed */ + outl(mac[4] | mac[5] << 8, io_base + 4); + inl(io_base + 4); + outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, + io_base); + inl(io_base); /* Lock config regs */ - outb(CFG_9346_LOCK, nic_port + CFG_9346); + outb(CFG_9346_LOCK, io_base + CFG_9346); + + printk(BIOS_DEBUG, "done\n"); +} + +static void r8168_init(struct device *dev) +{ + /* Get the resource of the NIC mmio */ + struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); + u16 io_base = (u16)nic_res->base; + + /* Enable but do not set bus master */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + + /* Program MAC address based on CBFS "macaddress" containing + * a string AA:BB:CC:DD:EE:FF */ + if (io_base) + program_mac_address(dev, io_base); + else + printk(BIOS_DEBUG, "r8168: Error cant find MMIO resource\n"); } static struct device_operations r8168_ops = {

1 0

New patch to review for coreboot: autoport: Fix romstage generator
by Kyösti Mälkki 04 Dec '16

04 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17711 -gerrit commit 660ef5f826141e754c5ae7b667777c8c361ba52e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 4 11:17:07 2016 +0200 autoport: Fix romstage generator Protototype changed here: e258b9a intel sandy/ivy: Improve DIMM replacement detection Change-Id: Id79238db2e497b9163f3bd1b1d5d4bc11fe4da9e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- util/autoport/bd82x6x.go | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 1252292..ed94df7 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -367,11 +367,11 @@ void mainboard_config_superio(void) } /* FIXME: Put proper SPD map here. */ -void mainboard_get_spd(spd_raw_data *spd) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { `) for i, spd := range guessedMap { - fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x);\n", i, spd) + fmt.Fprintf(sb, "\tread_spd(&spd[%d], 0x%02x, id_only);\n", i, spd) } sb.WriteString("}\n")

1 0

New patch to review for coreboot: mb/lowrisc/nexys4ddr: Read RAM information from the config string
by Jonathan Neuschäfer 04 Dec '16

04 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17710 -gerrit commit e32e83b91996ad4e056495f13d0f8d67f25ab129 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sun Dec 4 08:49:38 2016 +0100 mb/lowrisc/nexys4ddr: Read RAM information from the config string Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/lowrisc/nexys4ddr/mainboard.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c index 8b6bcb2..aae3b9b 100644 --- a/src/mainboard/lowrisc/nexys4ddr/mainboard.c +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -14,17 +14,17 @@ */ #include <cbmem.h> +#include <commonlib/configstring.h> #include <device/device.h> #include <symbols.h> static void mainboard_enable(device_t dev) { - /* - * TODO: Get this size from the hardware-supplied configuration string. - */ - const size_t ram_size = 1*GiB; + uintptr_t ram_base; + size_t ram_size; - ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB); + query_mem(configstring(), &ram_base, &ram_size); + ram_resource(dev, 0, ram_base / KiB, ram_size / KiB); cbmem_initialize_empty(); }

1 0

New patch to review for coreboot: [DO NOT MERGE] riscv: Work around lowrisc's different page table format
by Jonathan Neuschäfer 04 Dec '16

04 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17709 -gerrit commit 712db2324809c87b544668eff16f7f0afab0ac23 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sun Dec 4 07:57:48 2016 +0100 [DO NOT MERGE] riscv: Work around lowrisc's different page table format See https://github.com/lowRISC/rocket/issues/3 Change-Id: I23b9cc16c105d11b84a9da4a737a653c991e9d72 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/virtual_memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 26a0169..d9b0e84 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -138,7 +138,7 @@ pte_t pte_create(uintptr_t ppn, int prot, int user) pte |= PTE_X; if (user) pte |= PTE_U; - return pte; + return pte | 0x1f; } // The current RISCV *physical* address space is this:

1 0

New patch to review for coreboot: soc/lowrisc: Place CBMEM at top of autodetected RAM
by Jonathan Neuschäfer 04 Dec '16

04 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17708 -gerrit commit 8ad15834db54b90bd140035870435531e56f3a4d Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Nov 24 08:26:03 2016 +0100 soc/lowrisc: Place CBMEM at top of autodetected RAM Change-Id: I9f169db330d1792128db7a6308ed3afbe5803c03 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/soc/lowrisc/lowrisc/cbmem.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/lowrisc/lowrisc/cbmem.c b/src/soc/lowrisc/lowrisc/cbmem.c index ea7ad70..44ffa26 100644 --- a/src/soc/lowrisc/lowrisc/cbmem.c +++ b/src/soc/lowrisc/lowrisc/cbmem.c @@ -11,13 +11,15 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <cbmem.h> +#include <commonlib/configstring.h> void *cbmem_top(void) { - // TODO: find out how the lowrisc SOC decides to provide - // this information, when they know. - printk(BIOS_SPEW, "Returning hard-coded 128M; fix me\n"); - return (void *)((uintptr_t)(2ULL*GiB+128*MiB)); + uintptr_t base; + size_t size; + + query_mem(configstring(), &base, &size); + + return (void *)(base + size); }

1 0

New patch to review for coreboot: mb/lowrisc/nexys4ddr: Initialize CBMEM in romstage
by Jonathan Neuschäfer 04 Dec '16

04 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17707 -gerrit commit 556903df554d3ca96c1b0c0ee77a459e50839b33 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sat Dec 3 17:00:52 2016 +0100 mb/lowrisc/nexys4ddr: Initialize CBMEM in romstage Change-Id: Ic1706ae8ab3cbef8f445d70cb78fa9d3301d87be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/lowrisc/nexys4ddr/mainboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c index b2ce398..8b6bcb2 100644 --- a/src/mainboard/lowrisc/nexys4ddr/mainboard.c +++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cbmem.h> #include <device/device.h> #include <symbols.h> @@ -24,6 +25,8 @@ static void mainboard_enable(device_t dev) const size_t ram_size = 1*GiB; ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size / KiB); + + cbmem_initialize_empty(); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: soc/marvell/mvmap2315: Fix integer arithmetic
by Jonathan Neuschäfer 04 Dec '16

04 Dec '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17401 -gerrit commit f607b8ce2be0d554d304174f4a60613d120fbdf9 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sat Nov 12 13:50:17 2016 +0100 soc/marvell/mvmap2315: Fix integer arithmetic Replace logical with bitwise AND operator. Change-Id: I712fab61fbbc833fc2b2575948a875e2f07fd5de Reported-by: Coverity (CID 1362808) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/soc/marvell/mvmap2315/mcu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/mcu.c b/src/soc/marvell/mvmap2315/mcu.c index c334cda..e634ff8 100644 --- a/src/soc/marvell/mvmap2315/mcu.c +++ b/src/soc/marvell/mvmap2315/mcu.c @@ -31,7 +31,7 @@ static u8 mvmap2315_calc_checksum(const void *data, u32 size) for (i = csum = 0; i < size; i++) csum += bytes[i]; - return (~csum) && 0xFF; + return (~csum) & 0xFF; } void mcu_irq(void)

1 0

Patch merged into coreboot/master: spi_flash: Move spi flash opcodes to spi_flash.h
by gerrit＠coreboot.org 04 Dec '16

04 Dec '16

the following patch was just integrated into master: commit 52896c6c33250036928406d9dc38aa2ce1906b05 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 22 11:43:58 2016 -0800 spi_flash: Move spi flash opcodes to spi_flash.h BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I3b6656923bb312de470da43a23f66f350e1cebc7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17680 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17680 for details. -gerrit

1 0

Patch merged into coreboot/master: cbfstool: Fix off-by-one error in checking hash_type
by gerrit＠coreboot.org 04 Dec '16

04 Dec '16

the following patch was just integrated into master: commit 1d56eef728a9d9266b2dde9174520900ee87f9f2 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Dec 2 09:24:50 2016 -0800 cbfstool: Fix off-by-one error in checking hash_type Change-Id: Iaf208705d0cd450288af721d53053b2d3407a336 Found-by: Coverity Scan #1325836 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17698 for details. -gerrit

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2016