coreboot-gerrit December 2016

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Patch set updated for coreboot: intel/i3100: Switch to MMCONF_SUPPORT
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17548 -gerrit commit d075332a87a1e7b0f787735999998786687a6e62 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:26:23 2016 +0200 intel/i3100: Switch to MMCONF_SUPPORT TODO: HECBASE in bootblock Change-Id: Ia636bd82ccff542ac03b8799444eef8430a57e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/eagleheights/Kconfig | 4 ---- src/northbridge/intel/i3100/Kconfig | 10 +++++++++- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 9671fff..7e64004 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -22,10 +22,6 @@ config MAINBOARD_PART_NUMBER string default "EagleHeights" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config IRQ_SLOT_COUNT int default 9 diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 7d4f4e5..7e0b444 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,10 +1,18 @@ config NORTHBRIDGE_INTEL_I3100 bool - select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO if NORTHBRIDGE_INTEL_I3100 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MMCONF_BUS_NUMBER + int + default 256 + config DIMM_MAP_LOGICAL hex default 0x1248

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Patch set updated for coreboot: MMCONF_SUPPORT: Flip default to enabled
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17694 -gerrit commit 30c365185cfe71c3d9ad8891e04b63d833f12780 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:46:56 2016 +0200 MMCONF_SUPPORT: Flip default to enabled Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 1 - src/cpu/amd/agesa/family12/Kconfig | 1 - src/cpu/amd/agesa/family14/Kconfig | 1 - src/cpu/amd/agesa/family15/Kconfig | 1 - src/cpu/amd/agesa/family15rl/Kconfig | 1 - src/cpu/amd/agesa/family15tn/Kconfig | 1 - src/cpu/amd/agesa/family16kb/Kconfig | 1 - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/geode_gx2/Kconfig | 1 + src/cpu/amd/geode_lx/Kconfig | 1 + src/cpu/amd/pi/00630F01/Kconfig | 1 - src/cpu/amd/pi/00660F01/Kconfig | 1 - src/cpu/amd/pi/00670F00/Kconfig | 1 - src/cpu/amd/pi/00730F01/Kconfig | 1 - src/device/Kconfig | 8 ++------ src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/fsp_rangeley/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 2 -- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 - src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/pineview/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 2 -- src/northbridge/intel/x4x/Kconfig | 1 - src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_broadwell_de/Kconfig | 1 - src/soc/intel/sch/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 46 files changed, 15 insertions(+), 40 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 6bb8d43..b1076e1 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 8e4c7ba..fa9cd5f 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY12 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY12 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 7be63f5..c539d27 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY14 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 22e4d8c..3f13b3e 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig index b916e2c..85087ef 100644 --- a/src/cpu/amd/agesa/family15rl/Kconfig +++ b/src/cpu/amd/agesa/family15rl/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY15_RL bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_RL diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 1f41560..1cc77b8 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 3f65055..0cdf55a 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..95338df 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ config CPU_AMD_MODEL_10XXX select ARCH_RAMSTAGE_X86_32 select SSE select SSE2 - select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index 51dece5..c7745ec 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -24,6 +24,7 @@ if CPU_AMD_GEODE_GX2 config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 3a01828..82a5d46 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -9,6 +9,7 @@ if CPU_AMD_GEODE_LX config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT select TSC_MONOTONIC_TIMER config DCACHE_RAM_BASE diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 5c12ab6..910df58 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00630F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index b38ea6c..aab0639 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00660F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index e47dfa3..b4ba450 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00670F00 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00670F00 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 83af181..ecbdb53 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00730F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00730F01 diff --git a/src/device/Kconfig b/src/device/Kconfig index 622f3d5..d238547 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -221,15 +221,11 @@ if PCI config NO_MMCONF_SUPPORT bool - default !MMCONF_SUPPORT_DEFAULT + default n config MMCONF_SUPPORT bool - default MMCONF_SUPPORT_DEFAULT - -config MMCONF_SUPPORT_DEFAULT - bool - default n + default !NO_MMCONF_SUPPORT config HYPERTRANSPORT_PLUGIN_SUPPORT bool diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1dba29d..9a65f70 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -3,6 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_QEMU_X86 + select NO_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 442356e..3000533 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - select MMCONF_SUPPORT_DEFAULT # select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index f1ee3c3..8a5dddf 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_AMD_AMDK8 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index c1faac0..702ba1c 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -20,6 +20,7 @@ if NORTHBRIDGE_INTEL_E7505 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index 506a913..bc735264 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 96b2df5..89326b4 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -18,13 +18,11 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 80447d5..ca1f9c6 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index db51dd2..4fc117d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 2260664..7d4f4e5 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 3f574a4..36d4754 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I440BX bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index 9fde6cb..67a21fc 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -15,7 +15,6 @@ config NORTHBRIDGE_INTEL_I5000 bool - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 428505c..7d8c46b 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I82810 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 344dfed..d0bee8f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I82830 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index 25a1fd5..a9439dc 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I855 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d22451a..8f59be5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -20,7 +20,6 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index eee9405..4dada50 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_NEHALEM bool select CPU_INTEL_MODEL_2065X - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 188db6d..5b34fb2 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_PINEVIEW config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7ca897e..c78b397 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP @@ -25,7 +24,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 43c7b2a..57e93f9 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -22,7 +22,6 @@ if NORTHBRIDGE_INTEL_X4X config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI select EARLY_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 1889705..98af4e8 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CN700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 03014eb..ec2c75b 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CX700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..9bcb7cd 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_VX800 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 182345e..73d40ad 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 092102c..6769af0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_INTEL_FIRMWARE select HAVE_SMI_HANDLER - select MMCONF_SUPPORT_DEFAULT select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5fd88a5..2d07c99 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b3ca1b8..ac4a2ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2c62d29..75cd831 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 6260630..689e625 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 72979de..8442963 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select SMP diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index ed3e003..2456df7 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -15,7 +15,6 @@ config SOC_INTEL_SCH bool - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT select INTEL_GMA_ACPI select SOUTHBRIDGE_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1778dae..24c2e30 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IOAPIC - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select MRC_SETTINGS_PROTECT select PARALLEL_MP

1 0

Patch set updated for coreboot: PCI ops: MMCONF_SUPPORT_DEFAULT is permanent choice
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17693 -gerrit commit b4037e1d7ce5c810a980fd11e16bc3b3d3816b14 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 22:08:18 2016 +0200 PCI ops: MMCONF_SUPPORT_DEFAULT is permanent choice Doing PCI config operations via MMIO window is here to stay and we do not support the option of making it disabled. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 9 -------- src/arch/x86/include/arch/io.h | 12 +++++------ src/arch/x86/include/arch/pci_ops.h | 3 --- src/device/Kconfig | 23 +++++++++++++++------ src/device/pci_ops.c | 7 +++---- src/mainboard/emulation/qemu-q35/bootblock.c | 4 ++-- src/mainboard/google/beltino/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 25 +++++++++++------------ src/northbridge/amd/pi/00630F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00660F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00670F00/northbridge.c | 3 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +-- src/northbridge/intel/fsp_sandybridge/bootblock.c | 4 ++-- src/northbridge/intel/gm45/bootblock.c | 4 ++-- src/northbridge/intel/haswell/bootblock.c | 4 ++-- src/northbridge/intel/i5000/bootblock.c | 4 ++-- src/northbridge/intel/i945/bootblock.c | 4 ++-- src/northbridge/intel/sandybridge/bootblock.c | 4 ++-- src/northbridge/via/vx900/early_vx900.c | 3 +-- src/soc/intel/broadwell/bootblock/systemagent.c | 4 ++-- src/soc/intel/skylake/bootblock/systemagent.c | 4 ++-- src/southbridge/intel/i82801gx/i82801gx.c | 4 ---- src/southbridge/intel/i82801ix/i82801ix.c | 4 ---- 23 files changed, 61 insertions(+), 78 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 5cd0254..a22a2b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,15 +550,6 @@ config MAX_CPUS int default 1 -config MMCONF_SUPPORT_DEFAULT - bool - default n - -config MMCONF_SUPPORT - bool - default y if MMCONF_SUPPORT_DEFAULT - default n - source "src/console/Kconfig" config HAVE_ACPI_RESUME diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 1ab6996..53c49a1 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -249,7 +249,7 @@ typedef u32 device_t; static inline __attribute__((always_inline)) uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) return pci_mmio_read_config8(dev, where); else return pci_io_read_config8(dev, where); @@ -258,7 +258,7 @@ uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) static inline __attribute__((always_inline)) uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) return pci_mmio_read_config16(dev, where); else return pci_io_read_config16(dev, where); @@ -267,7 +267,7 @@ uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) static inline __attribute__((always_inline)) uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) return pci_mmio_read_config32(dev, where); else return pci_io_read_config32(dev, where); @@ -276,7 +276,7 @@ uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) static inline __attribute__((always_inline)) void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) pci_mmio_write_config8(dev, where, value); else pci_io_write_config8(dev, where, value); @@ -285,7 +285,7 @@ void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) static inline __attribute__((always_inline)) void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) pci_mmio_write_config16(dev, where, value); else pci_io_write_config16(dev, where, value); @@ -294,7 +294,7 @@ void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) static inline __attribute__((always_inline)) void pci_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) { - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) pci_mmio_write_config32(dev, where, value); else pci_io_write_config32(dev, where, value); diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b662170..1b245aa 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -17,10 +17,7 @@ #ifndef __SIMPLE_DEVICE__ extern const struct pci_bus_operations pci_cf8_conf1; - -#if CONFIG_MMCONF_SUPPORT extern const struct pci_bus_operations pci_ops_mmconf; -#endif const struct pci_bus_operations *pci_bus_default_ops(device_t dev); diff --git a/src/device/Kconfig b/src/device/Kconfig index fb0aaba..622f3d5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -217,31 +217,42 @@ config PCI bool default n +if PCI + +config NO_MMCONF_SUPPORT + bool + default !MMCONF_SUPPORT_DEFAULT + +config MMCONF_SUPPORT + bool + default MMCONF_SUPPORT_DEFAULT + +config MMCONF_SUPPORT_DEFAULT + bool + default n + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - depends on PCI default n config PCIX_PLUGIN_SUPPORT bool - depends on PCI default y config CARDBUS_PLUGIN_SUPPORT bool - depends on PCI default y config AZALIA_PLUGIN_SUPPORT bool - depends on PCI default n config PCIEXP_PLUGIN_SUPPORT bool - depends on PCI default y +endif # PCI + if PCIEXP_PLUGIN_SUPPORT config PCIEXP_COMMON_CLOCK @@ -268,7 +279,7 @@ config PCIEXP_CLK_PM config PCIEXP_L1_SUB_STATE prompt "Enable PCIe ASPM L1 SubState" bool - depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT) + depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT) default n help Detect and enable ASPM on PCIe links. diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 2f896d2..b6fc32d 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -22,11 +22,10 @@ const struct pci_bus_operations *pci_bus_default_ops(device_t dev) { -#if CONFIG_MMCONF_SUPPORT_DEFAULT + if (IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + return &pci_cf8_conf1; + return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif } static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev) diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 939a4e6..68df39f 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -10,12 +10,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 608523e..c430018 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -9,7 +9,6 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5634441..cc2e6f9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -740,19 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); - } + /* We have MMCONF_SUPPORT, create the resource window. */ + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index fb115ff..4872db0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -335,8 +335,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 115d760..4c1254c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index ce0dde3..9a39410 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 5b83721..44f91e2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -338,8 +338,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/intel/fsp_sandybridge/bootblock.c b/src/northbridge/intel/fsp_sandybridge/bootblock.c index 1c1d492..508afaa 100644 --- a/src/northbridge/intel/fsp_sandybridge/bootblock.c +++ b/src/northbridge/intel/fsp_sandybridge/bootblock.c @@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index 10c64e9..76ed1a0 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -10,12 +10,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. + * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 743007e..efd3bea 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/i5000/bootblock.c b/src/northbridge/intel/i5000/bootblock.c index eabbee6..ff7513a 100644 --- a/src/northbridge/intel/i5000/bootblock.c +++ b/src/northbridge/intel/i5000/bootblock.c @@ -4,12 +4,12 @@ static void bootblock_northbridge_init(void) { /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 4571446..d837122 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 1c1d492..508afaa 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -9,12 +9,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index eb5c79c..6e1bc23 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void) * accessed */ pci_io_write_config8(HOST_CTR, 0x4f, 0x01); -#if CONFIG_MMCONF_SUPPORT /* COOL, now enable MMCONF */ u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); reg8 |= 3; pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; pci_io_write_config8(TRAF_CTR, 0x61, reg8); -#endif } /** diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7511549..1a09f8e 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -23,12 +23,12 @@ static void bootblock_northbridge_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. + * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/soc/intel/skylake/bootblock/systemagent.c b/src/soc/intel/skylake/bootblock/systemagent.c index 608110e..e76d4d2 100644 --- a/src/soc/intel/skylake/bootblock/systemagent.c +++ b/src/soc/intel/skylake/bootblock/systemagent.c @@ -26,12 +26,12 @@ void bootblock_systemagent_early_init(void) /* * The "io" variant of the config access is explicitly used to - * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to * to true. That way all subsequent non-explicit config accesses use * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6d97088..aab674b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -20,10 +20,6 @@ #include "i82801gx.h" #include "sata.h" -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - void i82801gx_enable(device_t dev) { u32 reg32; diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f02429a..0f3a08c 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -23,10 +23,6 @@ #include <console/console.h> #include "i82801ix.h" -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(device_t dev)

1 0

Patch set updated for coreboot: AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17692 -gerrit commit d5253e9bff4158eb217cfe95e438652082f39a23 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 21:47:50 2016 +0200 AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/kcma-d8/Kconfig | 1 - src/mainboard/asus/kfsn4-dre/Kconfig | 1 - src/mainboard/asus/kgpe-d16/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/tyan/s2912_fam10/Kconfig | 1 - src/northbridge/amd/amdfam10/Kconfig | 1 - 6 files changed, 6 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 6e84fa8..6d2e13f 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select SPI_FLASH select SPI_FLASH_WINBOND select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index f40899d..96260ce 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select DRIVERS_I2C_W83793 select DRIVERS_XGI_Z9S select VGA diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 19bf728..8e7a105 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index a1f55f4..0222de6 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 861c2e5..9b36df6 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR string diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 0c6d289..b414d91 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -20,7 +20,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM

1 0

Patch set updated for coreboot: PCI ops: Remove pci_mmio_xx() in ramstage
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17691 -gerrit commit 1e91aa905ab1d27ee4cc0b1bb4d9a520f6020e06 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:06:55 2016 +0200 PCI ops: Remove pci_mmio_xx() in ramstage MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_ops.c | 45 -------------------------------------------- src/include/device/pci_ops.h | 8 -------- 2 files changed, 53 deletions(-) diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index ab72405..2f896d2 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -118,48 +118,3 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val) pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } - -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read8(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u16 pci_mmio_read_config16(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read16(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u32 pci_mmio_read_config32(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read32(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -#endif diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 920475a..3310e10 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -13,14 +13,6 @@ void pci_write_config8(struct device *dev, unsigned int where, u8 val); void pci_write_config16(struct device *dev, unsigned int where, u16 val); void pci_write_config32(struct device *dev, unsigned int where, u32 val); -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where); -u16 pci_mmio_read_config16(struct device *dev, unsigned int where); -u32 pci_mmio_read_config32(struct device *dev, unsigned int where); -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); -#endif #endif #endif /* PCI_OPS_H */

1 0

Patch set updated for coreboot: PCI ops: Rename pcie_xx() to pci_mmio_xx()
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17530 -gerrit commit 708ecf9d7887397bc2df32b6fe2bd58eb8ad34cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 27 14:59:00 2013 +0200 PCI ops: Rename pcie_xx() to pci_mmio_xx() Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 54 ++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/pci_io_cfg.h | 10 ------ src/arch/x86/include/arch/pci_mmio_cfg.h | 32 ++++--------------- 3 files changed, 60 insertions(+), 36 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d1cadf..1ab6996 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,6 +246,60 @@ typedef u32 device_t; #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> +static inline __attribute__((always_inline)) +uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config8(dev, where); + else + return pci_io_read_config8(dev, where); +} + +static inline __attribute__((always_inline)) +uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config16(dev, where); + else + return pci_io_read_config16(dev, where); +} + +static inline __attribute__((always_inline)) +uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + return pci_mmio_read_config32(dev, where); + else + return pci_io_read_config32(dev, where); +} + +static inline __attribute__((always_inline)) +void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config8(dev, where, value); + else + pci_io_write_config8(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config16(dev, where, value); + else + pci_io_write_config16(dev, where, value); +} + +static inline __attribute__((always_inline)) +void pci_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) +{ + if (IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT)) + pci_mmio_write_config32(dev, where, value); + else + pci_io_write_config32(dev, where, value); +} + #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index b838535..4346285 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -94,14 +94,4 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) outl(value, 0xCFC); } -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pci_io_read_config8 -#define pci_read_config16 pci_io_read_config16 -#define pci_read_config32 pci_io_read_config32 - -#define pci_write_config8 pci_io_write_config8 -#define pci_write_config16 pci_io_write_config16 -#define pci_write_config32 pci_io_write_config32 -#endif - #endif /* _PCI_IO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index d3eff8f..9b9f702 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -18,11 +18,10 @@ #include <arch/io.h> -#if CONFIG_MMCONF_SUPPORT #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) +u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -30,7 +29,7 @@ u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) +u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -38,7 +37,7 @@ u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) +u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); @@ -46,7 +45,7 @@ u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) +void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -54,7 +53,7 @@ void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) +void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -62,30 +61,11 @@ void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) +void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); write32(addr, value); } -#define pci_mmio_read_config8 pcie_read_config8 -#define pci_mmio_read_config16 pcie_read_config16 -#define pci_mmio_read_config32 pcie_read_config32 - -#define pci_mmio_write_config8 pcie_write_config8 -#define pci_mmio_write_config16 pcie_write_config16 -#define pci_mmio_write_config32 pcie_write_config32 - -#if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pcie_read_config8 -#define pci_read_config16 pcie_read_config16 -#define pci_read_config32 pcie_read_config32 - -#define pci_write_config8 pcie_write_config8 -#define pci_write_config16 pcie_write_config16 -#define pci_write_config32 pcie_write_config32 -#endif - -#endif /* CONFIG_MMCONF_SUPPORT */ #endif /* _PCI_MMIO_CFG_H */

1 0

Patch set updated for coreboot: PCI ops: Define read-modify-write routines globally
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17690 -gerrit commit fe86cf947e41832a52396200c1fc851c975ffa40 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 PCI ops: Define read-modify-write routines globally Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 33 ++++++++++ src/device/pciexp_device.c | 26 +++----- src/soc/intel/broadwell/pcie.c | 113 +++++++++++++-------------------- src/soc/intel/broadwell/romstage/pch.c | 16 +---- src/southbridge/intel/lynxpoint/pcie.c | 107 ++++++++++++------------------- 5 files changed, 131 insertions(+), 164 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d4be86..0d1cadf 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -374,4 +374,37 @@ void pci_or_config32(device_t dev, unsigned int where, u32 ormask) pci_write_config32(dev, where, value | ormask); } +static inline __attribute__ ((always_inline)) +void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} + #endif diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 7228249..0c36538 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -122,16 +122,6 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pciexp_config_max_latency(device_t root, device_t dev) { unsigned int cap; @@ -150,7 +140,7 @@ static void pciexp_enable_ltr(device_t dev) dev_path(dev)); return; } - pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10); + pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10); } static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, @@ -226,26 +216,26 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, pciexp_enable_ltr(root); - pcie_update_cfg(root, root_cap + 0x08, ~0xff00, + pci_update_config32(root, root_cap + 0x08, ~0xff00, (comm_mode_rst_time << 8)); - pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04, + pci_update_config32(root, root_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000, + pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(root, root_cap + 0x08, ~0x1f, + pci_update_config32(root, root_cap + 0x08, ~0x1f, L1SubStateSupport); for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { - pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04, + pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000, + pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f, + pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, L1SubStateSupport); pciexp_enable_ltr(dev_t); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 355e17a..c3d9e13 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -30,9 +30,6 @@ #include <soc/cpu.h> #include <delay.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -129,14 +126,14 @@ static void root_port_init_config(device_t dev) rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ - pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + pci_update_config8(dev, 0xf5, ~0xa, 0x5); pcie_iosf_port_grant_count(dev); rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); if (dev->chip_info != NULL) { config_t *config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce; @@ -168,7 +165,7 @@ static void root_port_init_config(device_t dev) break; } - pcie_update_cfg(dev, 0x418, 0, 0x02000430); + pci_update_config32(dev, 0x418, 0, 0x02000430); if (root_port_is_first(dev)) { /* @@ -227,23 +224,23 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -251,17 +248,17 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 3); + pci_update_config8(dev, 0xe8, ~0, 3); if (is_broadwell) { - pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)), + pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)), ((1 << 5) | (1 << 14))); } else { - pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5)); + pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5)); } /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) @@ -269,18 +266,18 @@ static void pcie_enable_clock_gating(void) * In addition to D28Fx PCICFG 420h[30:29] = 11b, * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. */ - pcie_update_cfg(dev, 0x420, ~0x20000, (3 << 29) | 1); + pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); /* CLKREQ# VR Idle Enable */ RCBA32_OR(0x2b1c, (1 << (16 + i))); } if (!enabled_ports) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -312,7 +309,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ - pcie_update_cfg(dev, 0x338, ~(1 << 26), 1 << 26); + pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26); do { reg32 = pci_read_config32(dev, 0x328); @@ -326,7 +323,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n", dev_path(dev)); - pcie_update_cfg(dev, 0x408, ~(1 << 27), 1 << 27); + pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -439,26 +436,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -510,10 +487,10 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); switch (rp) { case 1: @@ -547,55 +524,55 @@ static void pch_pcie_early(struct device *dev) break; } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. Disable OBFF. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); /* Set Invalid Receive Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x0f, 0); + pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e); + pci_update_config32(dev, 0x200, ~0xffff, 0x001e); - pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), + pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); /* Enable Relaxed Order from Root Port. */ - pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23)); + pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23)); if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pch_pcie_init(struct device *dev) diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 74d3125..35a361a 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -131,16 +131,6 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); @@ -151,7 +141,7 @@ void pch_early_init(void) enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 17858af..3fd8d1e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -22,9 +22,6 @@ #include "pch.h" #include <southbridge/intel/common/gpio.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* LynxPoint-LP has 6 root ports while non-LP has 8. */ #define MAX_NUM_ROOT_PORTS 8 #define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS @@ -198,39 +195,39 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); if (!is_lp) { if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } if (rp == 5 && !rpc.ports[5]->enabled && !rpc.ports[6]->enabled && !rpc.ports[7]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -238,29 +235,29 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); if (is_lp) { - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); } /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 1); + pci_update_config8(dev, 0xe8, ~0, 1); - pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); } if (!enabled_ports && is_lp) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -458,26 +455,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -549,13 +526,13 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); /* Set L1 exit latency in LCAP register. */ - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); if (is_lp) { switch (rp) { @@ -624,50 +601,50 @@ static void pch_pcie_early(struct device *dev) } } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); /* Set Invalid Recieve Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x3f, 0); + pci_update_config8(dev, 0xf5, 0x3f, 0); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Set something involving advanced error reporting. */ - pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); + pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); if (is_lp) - pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); + pci_update_config32(dev, 0x100, ~0, (1 << 29)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pci_init(struct device *dev)

1 0

Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17689 -gerrit commit 49750171008cdceecefc7ac536b4a6b3f3e1ec7c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 43 ++++++++++++++---------- src/arch/x86/include/arch/pci_mmio_cfg.h | 21 ------------ src/northbridge/intel/fsp_sandybridge/finalize.c | 22 ++++++------ src/northbridge/intel/nehalem/finalize.c | 22 ++++++------ src/southbridge/intel/fsp_bd82x6x/finalize.c | 4 +-- src/southbridge/intel/fsp_i89xx/finalize.c | 4 +-- 6 files changed, 51 insertions(+), 65 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 69922e2..0d4be86 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,24 +246,6 @@ typedef u32 device_t; #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -static inline __attribute__((always_inline)) -void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value) -{ - pci_write_config8(dev, where, pci_read_config8(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value) -{ - pci_write_config16(dev, where, pci_read_config16(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) -{ - pci_write_config32(dev, where, pci_read_config32(dev, where) | value); -} - #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { @@ -367,4 +349,29 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned index, unsigned drq) #endif /* __SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ +#include <device/pci_ops.h> +#endif + +static inline __attribute__ ((always_inline)) +void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + #endif diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 25cdae9..d3eff8f 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -69,27 +69,6 @@ void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); } -static inline __attribute__ ((always_inline)) -void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} - #define pci_mmio_read_config8 pcie_read_config8 #define pci_mmio_read_config16 pcie_read_config16 #define pci_mmio_read_config32 pcie_read_config32 diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c index 19cfdb7..4ceb756 100644 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ b/src/northbridge/intel/fsp_sandybridge/finalize.c @@ -22,17 +22,17 @@ void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index be4397b..0b5cb74 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -22,17 +22,17 @@ void intel_nehalem_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4);

1 0

Patch set updated for coreboot: PCI ops: Remove conflicting duplicate declarations
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17720 -gerrit commit aecdfb0be5cc4d471d329aa057adc5e24176f29d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 5 06:33:32 2016 +0200 PCI ops: Remove conflicting duplicate declarations The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/reset_test.c | 18 +++++----- src/southbridge/amd/amd8111/reset.c | 56 ++++++++++++-------------------- src/southbridge/broadcom/bcm5785/reset.c | 23 ++----------- src/southbridge/nvidia/ck804/reset.c | 23 ++----------- src/southbridge/nvidia/mcp55/reset.c | 23 ++----------- src/southbridge/sis/sis966/reset.c | 23 ++----------- 6 files changed, 37 insertions(+), 129 deletions(-) diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 53f2433..d8734a9 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -13,7 +13,7 @@ static inline int cpu_init_detected(unsigned nodeid) pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic = pci_io_read_config32(dev, HT_INIT_CONTROL); return !!(htic & HTIC_INIT_Detect); } @@ -21,7 +21,7 @@ static inline int cpu_init_detected(unsigned nodeid) static inline int bios_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -29,7 +29,7 @@ static inline int bios_reset_detected(void) static inline int cold_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -39,18 +39,18 @@ static inline void distinguish_cpu_resets(unsigned nodeid) u32 htic; pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(device, HT_INIT_CONTROL); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_write_config32(device, HT_INIT_CONTROL, htic); + pci_io_write_config32(device, HT_INIT_CONTROL, htic); } void set_bios_reset(void); void set_bios_reset(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } static unsigned node_link_to_bus(unsigned node, unsigned link) @@ -59,7 +59,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(0, 0x18, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -76,7 +76,7 @@ static inline unsigned get_sblk(void) { u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + reg = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x64); return ((reg>>8) & 3); } diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 3cc1a0a..fd2c82a 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -1,48 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> #include <device/pci_ids.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} #define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) { pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for (; dev <= last; dev += PCI_DEV(0,0,1)) { unsigned int id; - id = pci_read_config32(dev, 0); + id = pci_io_read_config32(dev, 0); if (id == pci_id) { return dev; } @@ -52,7 +37,6 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) #include "../../../northbridge/amd/amdk8/reset_test.c" - void hard_reset(void) { pci_devfn_t dev; @@ -64,11 +48,11 @@ void hard_reset(void) * There can only be one 8111 on a hypertransport chain/bus. */ bus = node_link_to_bus(node, link); - dev = pci_locate_device_on_bus( + dev = pci_io_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), bus); /* Reset */ set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + pci_io_write_config8(dev, 0x47, 1); } diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 82ff0fd..7511d29 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index 004ad58..ad994de 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 12cac29..a381cd3 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -17,30 +17,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 12cac29..a381cd3 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -17,30 +17,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void)

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New patch to review for coreboot: PCI ops: Remove conflicting duplicate declarations
by Kyösti Mälkki 05 Dec '16

05 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17720 -gerrit commit aedc1b77b834d4b58fe1de50a049892721fe252f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 5 06:33:32 2016 +0200 PCI ops: Remove conflicting duplicate declarations The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/reset_test.c | 18 +++++----- src/southbridge/amd/amd8111/reset.c | 56 ++++++++++++-------------------- src/southbridge/broadcom/bcm5785/reset.c | 23 ++----------- src/southbridge/nvidia/ck804/reset.c | 23 ++----------- src/southbridge/nvidia/mcp55/reset.c | 23 ++----------- 5 files changed, 35 insertions(+), 108 deletions(-) diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 53f2433..d8734a9 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -13,7 +13,7 @@ static inline int cpu_init_detected(unsigned nodeid) pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic = pci_io_read_config32(dev, HT_INIT_CONTROL); return !!(htic & HTIC_INIT_Detect); } @@ -21,7 +21,7 @@ static inline int cpu_init_detected(unsigned nodeid) static inline int bios_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -29,7 +29,7 @@ static inline int bios_reset_detected(void) static inline int cold_reset_detected(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -39,18 +39,18 @@ static inline void distinguish_cpu_resets(unsigned nodeid) u32 htic; pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(device, HT_INIT_CONTROL); + htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; - pci_write_config32(device, HT_INIT_CONTROL, htic); + pci_io_write_config32(device, HT_INIT_CONTROL, htic); } void set_bios_reset(void); void set_bios_reset(void) { u32 htic; - htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); + pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); } static unsigned node_link_to_bus(unsigned node, unsigned link) @@ -59,7 +59,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) for (reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(0, 0x18, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -76,7 +76,7 @@ static inline unsigned get_sblk(void) { u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); + reg = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x64); return ((reg>>8) & 3); } diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index 3cc1a0a..fd2c82a 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -1,48 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> #include <device/pci_ids.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -#define PCI_ID(VENDOR_ID, DEVICE_ID) \ - ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) - -static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} #define PCI_DEV_INVALID (0xffffffffU) -static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus) { pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for (; dev <= last; dev += PCI_DEV(0,0,1)) { unsigned int id; - id = pci_read_config32(dev, 0); + id = pci_io_read_config32(dev, 0); if (id == pci_id) { return dev; } @@ -52,7 +37,6 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) #include "../../../northbridge/amd/amdk8/reset_test.c" - void hard_reset(void) { pci_devfn_t dev; @@ -64,11 +48,11 @@ void hard_reset(void) * There can only be one 8111 on a hypertransport chain/bus. */ bus = node_link_to_bus(node, link); - dev = pci_locate_device_on_bus( + dev = pci_io_locate_device_on_bus( PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), bus); /* Reset */ set_bios_reset(); - pci_write_config8(dev, 0x47, 1); + pci_io_write_config8(dev, 0x47, 1); } diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 82ff0fd..7511d29 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index 004ad58..ad994de 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -14,30 +14,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev >> 4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void) diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 12cac29..a381cd3 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -17,30 +17,11 @@ * GNU General Public License for more details. */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - #include "../../../northbridge/amd/amdk8/reset_test.c" void hard_reset(void)

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coreboot-gerrit December 2016