coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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1140 discussions

Patch merged into coreboot/master: google/gru: Power-cycle USB ports in developer/recovery modes
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit c49782cbe7a79cca03c3c20c647211367bb0a03e Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Nov 21 20:14:18 2016 -0800 google/gru: Power-cycle USB ports in developer/recovery modes Gru only uses USB 2.0 in firmware to avoid all the madness associated with Type-C port orientation and USB 3.0 tuning. We do this by isolating the SuperSpeed lines in the Type-C PHY so it looks like they aren't connected to the device. Unfortunately, some devices seem to already get "locked" into SuperSpeed mode as soon as they detect Rx terminations once, and can never snap out again on their own. Since the terminations are already connected during power-on reset we cannot disable them fast enough to prevent this, and the only solution we found to date is to power-cycle the whole USB port. Now, Gru's USB port power is controlled by the EC, and unfortunately we have no direct host command to control it. We do however have a command to force a certain USB PD "role", and forcing our host into "sink" mode makes it stop sourcing power to the port. So for lack of a saner solution we'll use this to work around our problem. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Booted Kevin in recovery mode, confirmed that my "problem stick" gets detected immediately (whereas previously I had to unplug/replug it). Booted Kevin to OS in both developer and normal mode and confirmed that USB still seems to work. Change-Id: Ib3cceba9baa170b13f01bd5c01bd413be5b441ba Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: cd695eda33299e50362f1096c46f2f5260c49036 Original-Change-Id: I2db3d6d3710d18a8b8030e94eb1ac2e931f22638 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413031 Reviewed-on: https://review.coreboot.org/17628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17628 for details. -gerrit

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Patch merged into coreboot/master: google/chromeec: Add command to control USB PD role
by gerrit＠coreboot.org 06 Dec '16

06 Dec '16

the following patch was just integrated into master: commit ea79d2b3a3ddcb7909ac2862ebfda19c6b8823ae Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Nov 21 20:14:07 2016 -0800 google/chromeec: Add command to control USB PD role Normally firmware should have no business messing with the USB PD role (source/sink/whatever) in the EC. But, as so often happens, ugly issues crop up that require weird work-arounds, and before you know it you need to do this for some reason that only makes sense in context. I do now, so add this function to send the necessary host command in the simplest possible fashion. BRANCH=gru BUG=chrome-os-partner:59346 TEST=Used it in a follow-up patch. Change-Id: I07d40feafd6a8387a633d6384efb205baf578d76 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8b71767caccff9b77d458182ce8066f7abf6321c Original-Change-Id: Ie8d0be98f6b703f4db062fe2f728cd2588347202 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/413030 Original-Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17627 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17627 for details. -gerrit

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New patch to review for coreboot: arch/x86/tables: Add time stamps for each table type
by Paul Menzel 06 Dec '16

06 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17739 -gerrit commit e8e878deb27bf429dcb43f511e6d3a66ba7e5a79 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Dec 6 21:41:08 2016 +0100 arch/x86/tables: Add time stamps for each table type Change-Id: I9ec6a8d35dfdb73240a0d1b5038f105655a071a0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/tables.c | 17 +++++++++++++---- src/commonlib/include/commonlib/timestamp_serialized.h | 14 +++++++++++--- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index edcb717..e92928d 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -24,6 +24,7 @@ #include <arch/smp/mpspec.h> #include <arch/acpi.h> #include <string.h> +#include <timestamp.h> #include <cbmem.h> #include <smbios.h> @@ -191,18 +192,26 @@ void arch_write_tables(uintptr_t coreboot_table) unsigned long rom_table_end = 0xf0000; /* This table must be between 0x0f0000 and 0x100000 */ - if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) + if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE)) { + timestamp_add_now(TS_PIRQ_TABLE); rom_table_end = write_pirq_table(rom_table_end); + } /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */ - if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) + if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) { + timestamp_add_now(TS_MP_TABLE); rom_table_end = write_mptable(rom_table_end); + } - if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) + if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)) { + timestamp_add_now(TS_ACPI_TABLE); rom_table_end = write_acpi_table(rom_table_end); + } - if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) + if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)) { + timestamp_add_now(TS_SMBIOS_TABLE); rom_table_end = write_smbios_table(rom_table_end); + } sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table); diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 4f109a7..a707c73 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -56,9 +56,13 @@ enum timestamp_id { TS_DEVICE_DONE = 70, TS_CBMEM_POST = 75, TS_WRITE_TABLES = 80, - TS_COREBOOT_TABLE = 82, - TS_OPTION_TABLE = 84, - TS_BOOTMEM_INIT = 86, + TS_PIRQ_TABLE = 81, + TS_MP_TABLE = 82, + TS_ACPI_TABLE = 83, + TS_SMBIOS_TABLE = 84, + TS_COREBOOT_TABLE = 85, + TS_OPTION_TABLE = 86, + TS_BOOTMEM_INIT = 87, TS_FRAMEBUFFER = 88, TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, @@ -145,6 +149,10 @@ static const struct timestamp_id_to_name { { TS_DEVICE_DONE, "device setup done" }, { TS_CBMEM_POST, "cbmem post" }, { TS_WRITE_TABLES, "write tables" }, + { TS_PIRQ_TABLE, "write PIRQ table" }, + { TS_MP_TABLE, "write MP table" }, + { TS_ACPI_TABLE, "write ACPI table" }, + { TS_SMBIOS_TABLE, "write SMBIOS table" }, { TS_COREBOOT_TABLE, "write coreboot table" }, { TS_OPTION_TABLE, "write option table" }, { TS_BOOTMEM_INIT, "initialize memory map at boot time" },

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New patch to review for coreboot: lib: Instrument table writing
by Paul Menzel 06 Dec '16

06 Dec '16

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17738 -gerrit commit 7862538c408af5d4156ae766b3ce27a6ba5abfd3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Dec 6 21:12:57 2016 +0100 lib: Instrument table writing Change-Id: Ie54fec50edd51ee978d248c65eb1de88a0bf248b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/commonlib/include/commonlib/timestamp_serialized.h | 8 ++++++++ src/lib/coreboot_table.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 29f5e0d..4f109a7 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -56,6 +56,10 @@ enum timestamp_id { TS_DEVICE_DONE = 70, TS_CBMEM_POST = 75, TS_WRITE_TABLES = 80, + TS_COREBOOT_TABLE = 82, + TS_OPTION_TABLE = 84, + TS_BOOTMEM_INIT = 86, + TS_FRAMEBUFFER = 88, TS_LOAD_PAYLOAD = 90, TS_ACPI_WAKE_JUMP = 98, TS_SELFBOOT_JUMP = 99, @@ -141,6 +145,10 @@ static const struct timestamp_id_to_name { { TS_DEVICE_DONE, "device setup done" }, { TS_CBMEM_POST, "cbmem post" }, { TS_WRITE_TABLES, "write tables" }, + { TS_COREBOOT_TABLE, "write coreboot table" }, + { TS_OPTION_TABLE, "write option table" }, + { TS_BOOTMEM_INIT, "initialize memory map at boot time" }, + { TS_FRAMEBUFFER, "record framebuffer" }, { TS_LOAD_PAYLOAD, "load payload" }, { TS_ACPI_WAKE_JUMP, "ACPI wake jump" }, { TS_SELFBOOT_JUMP, "selfboot jump" }, diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f8da658..d833652 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <bootmem.h> #include <spi_flash.h> +#include <timestamp.h> #include <vboot/vbnv_layout.h> #if CONFIG_USE_OPTION_TABLE #include <option_table.h> @@ -474,12 +475,14 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) { struct lb_header *head; + timestamp_add_now(TS_COREBOOT_TABLE); printk(BIOS_DEBUG, "Writing coreboot table at 0x%08lx\n", (long)rom_table_end); head = lb_table_init(rom_table_end); #if CONFIG_USE_OPTION_TABLE + timestamp_add_now(TS_OPTION_TABLE); { struct cmos_option_table *option_table = cbfs_boot_map_with_leak("cmos_layout.bin", @@ -497,6 +500,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) #endif /* Initialize the memory map at boot time. */ + timestamp_add_now(TS_BOOTMEM_INIT); bootmem_init(); /* No other memory areas can be added after the memory table has been @@ -517,6 +521,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end) /* Record our various random string information */ lb_strings(head); lb_record_version_timestamp(head); + timestamp_add_now(TS_FRAMEBUFFER); /* Record our framebuffer */ lb_framebuffer(head);

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Patch set updated for coreboot: superio/fintek: Add support for Fintek F71889A.
by Marty Plummer 06 Dec '16

06 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17669 -gerrit commit 7a51aaba69673aedc66e70f1c5916d915d4362a9 Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Thu Dec 1 02:14:39 2016 -0600 superio/fintek: Add support for Fintek F71889A. Datasheet: F71889A rev V0.21P Change-Id: I91c60a3b48cd4872ae7a27de8f49faa40e877a27 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f71889a/Kconfig | 20 +++++++++ src/superio/fintek/f71889a/Makefile.inc | 18 ++++++++ src/superio/fintek/f71889a/f71889a.h | 33 +++++++++++++++ src/superio/fintek/f71889a/superio.c | 73 +++++++++++++++++++++++++++++++++ 5 files changed, 145 insertions(+) diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66..d70fc99 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += f71859 subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 +subdirs-y += f71889a subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d diff --git a/src/superio/fintek/f71889a/Kconfig b/src/superio/fintek/f71889a/Kconfig new file mode 100644 index 0000000..96366d9 --- /dev/null +++ b/src/superio/fintek/f71889a/Kconfig @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +# Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config SUPERIO_FINTEK_F71889A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71889a/Makefile.inc b/src/superio/fintek/f71889a/Makefile.inc new file mode 100644 index 0000000..06fcff9 --- /dev/null +++ b/src/superio/fintek/f71889a/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71889A) += superio.c diff --git a/src/superio/fintek/f71889a/f71889a.h b/src/superio/fintek/f71889a/f71889a.h new file mode 100644 index 0000000..4a272a6 --- /dev/null +++ b/src/superio/fintek/f71889a/f71889a.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71889A_H +#define SUPERIO_FINTEK_F71889A_H + +/* Logical Device Numbers (LDN). */ +#define F71889A_SP1 0x01 /* UART1 */ +#define F71889A_SP2 0x02 /* UART2 */ +#define F71889A_PP 0x03 /* Parallel Port */ +#define F71889A_HWM 0x04 /* Hardware Monitor */ +#define F71889A_KBC 0x05 /* Keyboard/Mouse */ +#define F71889A_GPIO 0x06 /* GPIO */ +#define F71889A_WDT 0x07 /* WDT */ +#define F71889A_CIR 0x08 /* CIR */ +#define F71889A_PM 0x0a /* ACPI/PME */ +#define F71889A_VREF 0x0b /* VREF */ + +#endif /* SUPERIO_FINTEK_F71889A_H */ diff --git a/src/superio/fintek/f71889a/superio.c b/src/superio/fintek/f71889a/superio.c new file mode 100644 index 0000000..c25c3f3 --- /dev/null +++ b/src/superio/fintek/f71889a/superio.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f71889a.h" + +static void f71889a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + + case F71889A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71889a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. + * double check bitmasks + */ + { &ops, F71889A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07f8, 0}, }, + { &ops, F71889A_GPIO, }, + { &ops, F71889A_WDT, PNP_IO0, {0x0ff8, 0}, }, + { &ops, F71889A_CIR, PNP_IO0 | PNP_IRQ0, }, + { &ops, F71889A_PM, }, + { &ops, F71889A_VREF, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71889a_ops = { + CHIP_NAME("Fintek F71889A Super I/O") + .enable_dev = enable_dev +};

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Patch set updated for coreboot: intel/i3100: Switch to MMCONF_SUPPORT
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17548 -gerrit commit f1ac3b80d6dd16aae354e2077cff9872411dd223 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:26:23 2016 +0200 intel/i3100: Switch to MMCONF_SUPPORT TODO: HECBASE in bootblock Change-Id: Ia636bd82ccff542ac03b8799444eef8430a57e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/eagleheights/Kconfig | 4 ---- src/northbridge/intel/i3100/Kconfig | 10 +++++++++- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 9671fff..7e64004 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -22,10 +22,6 @@ config MAINBOARD_PART_NUMBER string default "EagleHeights" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config IRQ_SLOT_COUNT int default 9 diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 7d4f4e5..7e0b444 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,10 +1,18 @@ config NORTHBRIDGE_INTEL_I3100 bool - select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO if NORTHBRIDGE_INTEL_I3100 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MMCONF_BUS_NUMBER + int + default 256 + config DIMM_MAP_LOGICAL hex default 0x1248

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Patch set updated for coreboot: AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17697 -gerrit commit 096a820b877052020ff4358371252deab02b1f45 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 16:02:30 2016 +0200 AMD fam10 binaryPI: Remove invalid PCI ops on CPU domain Device is of type CPU_CLUSTER, while pci_dev_set_resources() expects PCI_DOMAIN. Change-Id: Ib1add47d71071abb6e9c28e3a85dd0b671741b71 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 13 ++----------- src/northbridge/amd/agesa/family12/northbridge.c | 20 ++------------------ src/northbridge/amd/amdfam10/northbridge.c | 7 +------ src/northbridge/amd/pi/00660F01/northbridge.c | 13 ++----------- src/northbridge/amd/pi/00670F00/northbridge.c | 13 ++----------- src/northbridge/amd/pi/00730F01/northbridge.c | 13 ++----------- 6 files changed, 11 insertions(+), 68 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index fb4914d..dd19e08 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1101,18 +1101,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index f0fe4e8..2f70572 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -652,22 +652,6 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ - -static void cpu_bus_read_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - -static void cpu_bus_set_resources(device_t dev) -{ - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - pci_dev_set_resources(dev); - - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); -} - static void cpu_bus_init(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); @@ -813,8 +797,8 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = 0, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e7c85c3..09dbd62 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1955,14 +1955,9 @@ static void cpu_bus_init(device_t dev) #endif } -static void cpu_bus_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, - .set_resources = cpu_bus_set_resources, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 97c8179..0cdf4e5 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1088,18 +1088,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 5eae902..f042b36 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -1089,18 +1089,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 1654b8a..45361e7 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1108,18 +1108,9 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static void cpu_bus_read_resources(device_t dev) -{ -} - -static void cpu_bus_set_resources(device_t dev) -{ - pci_dev_set_resources(dev); -} - static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan,

1 0

Patch set updated for coreboot: MMCONF_SUPPORT: Drop redundant logging
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17696 -gerrit commit a0aff55faa75760c7b3b96cee6ef6740656872c6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 14:38:13 2016 +0200 MMCONF_SUPPORT: Drop redundant logging Resource is actually stored even before read_resources, but that's where we currently log this resource. For Intel, use PCI config register offset as the resource index, while AMD side uses MSR address. Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/family10/northbridge.c | 5 ----- src/northbridge/amd/agesa/family12/northbridge.c | 6 +----- src/northbridge/amd/agesa/family14/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15rl/northbridge.c | 6 ------ src/northbridge/amd/agesa/family15tn/northbridge.c | 6 ------ src/northbridge/amd/agesa/family16kb/northbridge.c | 6 ------ src/northbridge/amd/amdfam10/northbridge.c | 4 ---- src/northbridge/amd/pi/00630F01/northbridge.c | 6 ------ src/northbridge/amd/pi/00660F01/northbridge.c | 4 ---- src/northbridge/amd/pi/00670F00/northbridge.c | 4 ---- src/northbridge/amd/pi/00730F01/northbridge.c | 4 ---- src/northbridge/intel/fsp_sandybridge/northbridge.c | 19 ++----------------- src/northbridge/intel/i3100/northbridge.c | 15 ++------------- src/northbridge/intel/i945/northbridge.c | 19 ++----------------- src/northbridge/intel/sandybridge/northbridge.c | 19 ++----------------- src/soc/intel/sch/northbridge.c | 15 +-------------- 17 files changed, 10 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 7408e50..fb4914d 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -537,11 +537,6 @@ static void amdfam10_set_resources(device_t dev) assign_resources(bus); } } - - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static void mcf0_control_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 5ef7a90..f0fe4e8 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -662,13 +662,9 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 08d1c49..c41f68a 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -412,12 +412,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } /* Domain/Root Complex related code */ diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index c5e2921..e7f47f4 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -429,12 +429,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static void scan_chains(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 2417933..506d7c8 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -429,12 +429,6 @@ static void set_resources(struct device *dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7862e60..38c92e8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -428,12 +428,6 @@ static void nb_set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 23057a9..b9de2e3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -428,12 +428,6 @@ static void set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index b384ca9..e7c85c3 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1957,10 +1957,6 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_set_resources(struct device *dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 1695808..d8ad807 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -431,12 +431,6 @@ static void set_resources(device_t dev) assign_resources(bus); } } - - /* Print the MMCONF region if it has been reserved. */ - res = find_resource(dev, 0xc0010058); - if (res) { - report_resource_stored(dev, res, " <mmconfig>"); - } } static unsigned long acpi_fill_hest(acpi_hest_t *hest) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 9f6ae1f..97c8179 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -1094,10 +1094,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 521a32c..5eae902 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -1095,10 +1095,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index d97d875..1654b8a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1114,10 +1114,6 @@ static void cpu_bus_read_resources(device_t dev) static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 877d85f..8c146f1 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -245,28 +245,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, 0, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -320,7 +305,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .scan_bus = 0, diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 65107de..42064ab 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -138,18 +138,7 @@ static void mc_read_resources(device_t dev) { pci_dev_read_resources(dev); - mmconf_resource32(dev, 0xcf); -} - -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - pci_dev_set_resources(dev); + mmconf_resource32(dev, EXPECBASE); } static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -188,7 +177,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, .scan_bus = 0, diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c98a39f..56a23c7 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -157,28 +157,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, 0, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -216,7 +201,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 0c30b2d..c78a345 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -265,28 +265,13 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ buses = get_pcie_bar(&pcie_config_base); if (buses) { - struct resource *resource = new_resource(dev, 0xcf); + struct resource *resource = new_resource(dev, PCIEXBAR); mmconf_resource_init(resource, 1, pcie_config_base, buses); } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR */ - resource = find_resource(dev, 0xcf); - if (resource) { - report_resource_stored(dev, resource, "<mmconfig>"); - } - - /* And call the normal set_resources */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -475,7 +460,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, .scan_bus = 0, diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 07b17c0..e4d77f8 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -201,19 +201,6 @@ static void mc_read_resources(device_t dev) } } -static void mc_set_resources(device_t dev) -{ - struct resource *resource; - - /* Report the PCIe BAR. */ - resource = find_resource(dev, 0xcf); - if (resource) - report_resource_stored(dev, resource, "<mmconfig>"); - - /* And call the normal set_resources. */ - pci_dev_set_resources(dev); -} - static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { if (!vendor || !device) { @@ -231,7 +218,7 @@ static struct pci_operations intel_pci_ops = { static struct device_operations mc_ops = { .read_resources = mc_read_resources, - .set_resources = mc_set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0,

1 0

Patch set updated for coreboot: MMCONF_SUPPORT: Consolidate resource registration
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17695 -gerrit commit 23c7c10b2182b1d65c795f230fdf4b7805d2deb5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:56:05 2016 +0200 MMCONF_SUPPORT: Consolidate resource registration Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device_util.c | 39 ++++++++++++++++++ src/include/device/device.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 21 +++++----- src/northbridge/amd/agesa/family12/northbridge.c | 13 +++--- src/northbridge/amd/agesa/family14/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15rl/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 +-- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 +-- src/northbridge/amd/amdfam10/northbridge.c | 9 +---- src/northbridge/amd/pi/00630F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00660F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00670F00/northbridge.c | 11 +---- src/northbridge/amd/pi/00730F01/northbridge.c | 11 +---- src/northbridge/intel/fsp_rangeley/Kconfig | 4 ++ src/northbridge/intel/fsp_rangeley/northbridge.c | 27 ++++++------- src/northbridge/intel/fsp_sandybridge/Kconfig | 4 ++ .../intel/fsp_sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/intel/i3100/northbridge.c | 10 +---- src/northbridge/intel/i945/northbridge.c | 45 +++++---------------- src/northbridge/intel/nehalem/Kconfig | 4 ++ src/northbridge/intel/nehalem/northbridge.c | 11 +---- src/northbridge/intel/sandybridge/Kconfig | 4 ++ src/northbridge/intel/sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/northbridge.c | 5 +-- src/soc/intel/fsp_baytrail/northcluster.c | 28 ++++++------- src/soc/intel/sch/Kconfig | 4 ++ src/soc/intel/sch/northbridge.c | 43 +++++--------------- 29 files changed, 172 insertions(+), 276 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 56afefd..15f6d3e 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -19,10 +19,12 @@ */ #include <console/console.h> +#include <cpu/cpu.h> #include <device/device.h> #include <device/path.h> #include <device/pci_def.h> #include <device/resource.h> +#include <lib.h> #include <string.h> /** @@ -888,6 +890,43 @@ void fixed_mem_resource(device_t dev, unsigned long index, resource->flags |= type; } +int mmconf_resource_init(struct resource *resource, bool bar64, + resource_t base, int buses) +{ + resource->base = base; + resource->size = buses * MiB; + resource->align = log2(resource->size); + resource->gran = log2(resource->size); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* 64-bit BAR or MSR. */ + if (bar64 && IS_ENABLED(CONFIG_ARCH_RAMSTAGE_X86_64)) + resource->limit = (1ULL << cpu_phys_address_size()) - 1; + else + resource->limit = (1ULL << 32) - 1; + + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR " + "0x%08lx-0x%08lx.\n", (unsigned long)(resource->base), + (unsigned long)(resource->base + resource->size)); + + return 0; +} + +void mmconf_resource32(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + mmconf_resource_init(resource, 0, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} + +void mmconf_resource64(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + mmconf_resource_init(resource, 1, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} + void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..773ea56 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,11 @@ void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); +int mmconf_resource_init(struct resource *res, bool bar64, resource_t base, + int buses); +void mmconf_resource32(struct device *dev, unsigned long index); +void mmconf_resource64(struct device *dev, unsigned long index); + void scan_smbus(device_t bus); void scan_static_bus(device_t bus); void scan_lpc_bus(device_t bus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2a54892..7408e50 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -424,6 +424,13 @@ static void amdfam10_read_resources(device_t dev) amdfam10_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); } static void amdfam10_set_resource(device_t dev, struct resource *resource, @@ -530,6 +537,11 @@ static void amdfam10_set_resources(device_t dev) assign_resources(bus); } } + + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } } static void mcf0_control_init(struct device *dev) @@ -1096,19 +1108,10 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_read_resources(device_t dev) { - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 6f2896a..5ef7a90 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -300,6 +300,14 @@ static void read_resources(device_t dev) amdfam12_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -649,11 +657,6 @@ static void cpu_bus_read_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f92183e..08d1c49 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -302,11 +302,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5fc9833..c5e2921 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -326,11 +326,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index b5f7690..2417933 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -326,11 +326,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2353126..7862e60 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -325,11 +325,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 63e1c2e..23057a9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -325,11 +325,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the APIC_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index cc2e6f9..b384ca9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -741,14 +741,7 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); /* We have MMCONF_SUPPORT, create the resource window. */ - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 4872db0..1695808 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -309,15 +309,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -335,7 +326,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 4c1254c..9f6ae1f 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 9a39410..521a32c 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 44f91e2..d97d875 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -312,15 +312,6 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -338,7 +329,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index bc735264..fdb5566 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -24,6 +24,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + choice prompt "Set TSEG Size" default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index f01333e..34426c7 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -57,13 +57,12 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) @@ -76,25 +75,13 @@ static int get_pcie_bar(u32 *base, u32 *len) *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; /* 256MB ECAM range */ - return 1; + return 256; } static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; @@ -154,9 +141,19 @@ static void mc_add_dram_resources(device_t dev) static void mc_read_resources(device_t dev) { + u32 pcie_config_base; + int buses; + /* Call the normal read_resources */ pci_dev_read_resources(dev); + /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + } + /* Calculate and add DRAM resources. */ mc_add_dram_resources(dev); } diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 89326b4..cfcfc34 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -30,6 +30,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/fsp_sandybridge/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 64 + config VGA_BIOS_ID string default "8086,0106" diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 50615b5..877d85f 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -62,18 +62,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; + /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) @@ -82,16 +82,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -99,21 +96,8 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } @@ -256,24 +240,17 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 8025ac3..65107de 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -32,9 +32,6 @@ #include <arch/acpi.h> -static u32 max_bus; - - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -139,14 +136,9 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; - pci_dev_read_resources(dev); - resource = new_resource(dev, 0xcf); - resource->base = 0xe0000000; - resource->size = max_bus * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource32(dev, 0xcf); } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 5d18591..c98a39f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -27,13 +27,12 @@ #include <arch/acpi.h> #include "i945.h" -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) @@ -47,36 +46,18 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; } -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } -} - static void pci_domain_set_resources(device_t dev) { uint32_t pci_tolm; @@ -153,8 +134,6 @@ static void pci_domain_set_resources(device_t dev) uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); - add_fixed_resources(dev, 7); - assign_resources(dev->link_list); } @@ -173,19 +152,17 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 4dada50..884660a 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM if NORTHBRIDGE_INTEL_NEHALEM +config MMCONF_BUS_NUMBER + int + default 256 + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 06c0a96..cc782e9 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -69,11 +69,6 @@ static void add_fixed_resources(struct device *dev, int index) 0xfed1c000-0xfed20000 RCBA 0xfed90000-0xfed94000 IOMMU 0xff800000-0xffffffff ROM. */ - resource = new_resource(dev, index++); - resource->base = (resource_t) 0xe0000000; - resource->size = (resource_t) 0x10000000; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; resource = new_resource(dev, index++); resource->base = (resource_t) 0xfed00000; @@ -98,10 +93,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - * See e7525/northbridge.c for an example. - */ static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, @@ -119,6 +110,8 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); + mmconf_resource64(dev, 0x50); + tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_TOUUD); diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index c78b397..15f2aab 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -71,6 +71,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 64 + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index fe1a07c..0c30b2d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -61,18 +61,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; + /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) @@ -81,16 +81,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -98,21 +95,8 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); reserved_ram_resource(dev, index++, 0xc0000 >> 10, @@ -276,24 +260,17 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 73d40ad..4b1e6cc 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -33,6 +33,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "1106,7122" diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index a4a8ece..ffeaada0 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -297,10 +297,7 @@ static void vx900_read_resources(device_t dev) /* Now do the same for our MMCONF * We always run with MMCONF enabled. We need to access the extended * config space when configuring PCI-Express links */ - res = new_resource(dev, idx++); - res->size = 256 * MiB; - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + mmconf_resource32(dev, idx++); pci_domain_read_resources(dev); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index bf1a388..d6f12dc 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -86,18 +86,18 @@ uint32_t nc_read_top_of_low_memory(void) return fsp_mem_base; } -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; + /* FIXME: This is 64bit BAR. */ pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG); if (!(pciexbar_reg & (1 << 0))) @@ -105,26 +105,13 @@ static int get_pcie_bar(u32 *base, u32 *len) *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; /* 256MB ECAM range */ - return 1; + return 256; } static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; @@ -182,9 +169,18 @@ static void mc_add_dram_resources(device_t dev) static void nc_read_resources(device_t dev) { + u32 pcie_config_base; + int buses; + /* Call the normal read_resources */ pci_dev_read_resources(dev); + /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 1, pcie_config_base, buses); + } /* Calculate and add DRAM resources. */ mc_add_dram_resources(dev); diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index 2456df7..abdee44 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -28,6 +28,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "soc/intel/sch/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "8086,8108" diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 390a0bc..07b17c0 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -27,7 +27,7 @@ #include <arch/acpi.h> #include "sch.h" -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; @@ -50,18 +50,15 @@ static int get_pcie_bar(u32 *base, u32 *len) case 0: /* 256MB */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: /* 128M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: /* 64M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -70,16 +67,6 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } printk(BIOS_DEBUG, "Adding CMC shadow area\n"); resource = new_resource(dev, index++); @@ -198,28 +185,20 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); /* - * So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - - /* * We use 0xcf as an unused index for our PCIe bar so that we find * it again. */ - resource = new_resource(dev, 0xcf); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size); - printk(BIOS_DEBUG, - "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), - (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev)

1 0

Patch set updated for coreboot: MMCONF_SUPPORT: Flip default to enabled
by Kyösti Mälkki 06 Dec '16

06 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17694 -gerrit commit 7906d1e76a2ffdcecf623b31e0d84454164449ff Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:46:56 2016 +0200 MMCONF_SUPPORT: Flip default to enabled Also remove separate MMCONF_SUPPORT_DEFAULT flag. Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 1 - src/cpu/amd/agesa/family12/Kconfig | 1 - src/cpu/amd/agesa/family14/Kconfig | 1 - src/cpu/amd/agesa/family15/Kconfig | 1 - src/cpu/amd/agesa/family15rl/Kconfig | 1 - src/cpu/amd/agesa/family15tn/Kconfig | 1 - src/cpu/amd/agesa/family16kb/Kconfig | 1 - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/geode_gx2/Kconfig | 1 + src/cpu/amd/geode_lx/Kconfig | 1 + src/cpu/amd/pi/00630F01/Kconfig | 1 - src/cpu/amd/pi/00660F01/Kconfig | 1 - src/cpu/amd/pi/00670F00/Kconfig | 1 - src/cpu/amd/pi/00730F01/Kconfig | 1 - src/device/Kconfig | 8 ++------ src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 8 ++++++++ src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/fsp_rangeley/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 2 -- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 - src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/pineview/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 2 -- src/northbridge/intel/x4x/Kconfig | 1 - src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_broadwell_de/Kconfig | 1 - src/soc/intel/sch/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 46 files changed, 22 insertions(+), 40 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 6bb8d43..b1076e1 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 8e4c7ba..fa9cd5f 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY12 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY12 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 7be63f5..c539d27 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY14 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 22e4d8c..3f13b3e 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig index b916e2c..85087ef 100644 --- a/src/cpu/amd/agesa/family15rl/Kconfig +++ b/src/cpu/amd/agesa/family15rl/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY15_RL bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_RL diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 1f41560..1cc77b8 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 3f65055..0cdf55a 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..95338df 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ config CPU_AMD_MODEL_10XXX select ARCH_RAMSTAGE_X86_32 select SSE select SSE2 - select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index 51dece5..c7745ec 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -24,6 +24,7 @@ if CPU_AMD_GEODE_GX2 config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 3a01828..82a5d46 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -9,6 +9,7 @@ if CPU_AMD_GEODE_LX config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT select TSC_MONOTONIC_TIMER config DCACHE_RAM_BASE diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 5c12ab6..910df58 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00630F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index b38ea6c..aab0639 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00660F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index e47dfa3..b4ba450 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00670F00 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00670F00 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 83af181..ecbdb53 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00730F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00730F01 diff --git a/src/device/Kconfig b/src/device/Kconfig index 622f3d5..d238547 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -221,15 +221,11 @@ if PCI config NO_MMCONF_SUPPORT bool - default !MMCONF_SUPPORT_DEFAULT + default n config MMCONF_SUPPORT bool - default MMCONF_SUPPORT_DEFAULT - -config MMCONF_SUPPORT_DEFAULT - bool - default n + default !NO_MMCONF_SUPPORT config HYPERTRANSPORT_PLUGIN_SUPPORT bool diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1dba29d..9a65f70 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -3,6 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_QEMU_X86 + select NO_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 442356e..3000533 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - select MMCONF_SUPPORT_DEFAULT # select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index f1ee3c3..83f70c9 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -22,6 +22,14 @@ config NORTHBRIDGE_AMD_AMDK8 select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDK8 + +config NO_MMCONF_SUPPORT + bool + default y + help + If you want to remove this, you need to make sure any access to CPU + nodes 0:18.0, 0:19.0, ... continue to use PCI IO config access. + config AGP_APERTURE_SIZE hex default 0x4000000 diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index c1faac0..702ba1c 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -20,6 +20,7 @@ if NORTHBRIDGE_INTEL_E7505 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index 506a913..bc735264 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 96b2df5..89326b4 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -18,13 +18,11 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 80447d5..ca1f9c6 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index db51dd2..4fc117d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 2260664..7d4f4e5 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 3f574a4..36d4754 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I440BX bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index 9fde6cb..67a21fc 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -15,7 +15,6 @@ config NORTHBRIDGE_INTEL_I5000 bool - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 428505c..7d8c46b 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I82810 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 344dfed..d0bee8f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I82830 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index 25a1fd5..a9439dc 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I855 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d22451a..8f59be5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -20,7 +20,6 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index eee9405..4dada50 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_NEHALEM bool select CPU_INTEL_MODEL_2065X - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 188db6d..5b34fb2 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_PINEVIEW config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7ca897e..c78b397 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP @@ -25,7 +24,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 43c7b2a..57e93f9 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -22,7 +22,6 @@ if NORTHBRIDGE_INTEL_X4X config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI select EARLY_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 1889705..98af4e8 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CN700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 03014eb..ec2c75b 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CX700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..9bcb7cd 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_VX800 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 182345e..73d40ad 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 092102c..6769af0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_INTEL_FIRMWARE select HAVE_SMI_HANDLER - select MMCONF_SUPPORT_DEFAULT select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5fd88a5..2d07c99 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b3ca1b8..ac4a2ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2c62d29..75cd831 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 6260630..689e625 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 72979de..8442963 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select SMP diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index ed3e003..2456df7 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -15,7 +15,6 @@ config SOC_INTEL_SCH bool - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT select INTEL_GMA_ACPI select SOUTHBRIDGE_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1778dae..24c2e30 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IOAPIC - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select MRC_SETTINGS_PROTECT select PARALLEL_MP

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coreboot-gerrit December 2016