Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17554
-gerrit
commit cb7bc6ea0a8826d9a160155e9291cac64d55cf75
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Wed Nov 16 21:32:04 2016 +0530
soc/intel/skylake: Fix top_of_ram calculation
FSP 2.0 implementation conditionally sets PMRR base based on
EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being
set since FSP 2.0 changed behavior from FSP 1.1 implementation.
If prmrr base is non-zero value, then top_of_ram is prmrr base.
If Probeless trace is enabled, then deduct trace memory size from
calculated top_of_ram.
Change-Id: I2633bf78705e36b241668a313d215d0455fba607
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
---
src/soc/intel/skylake/memmap.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 96debfd..17dbc32 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -150,7 +150,8 @@ u32 top_of_32bit_ram(void)
* PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
* PRMRR_MASK MSR lock bit is set.
*/
- if (smm_region_start() == 0)
+ top_of_ram = smm_region_start();
+ if (top_of_ram == 0)
return 0;
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
@@ -163,7 +164,8 @@ u32 top_of_32bit_ram(void)
* Refer to Fsp Integration Guide for the memory mapping layout.
*/
prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
- top_of_ram = prmrr_base.lo;
+ if (prmrr_base.lo)
+ top_of_ram = prmrr_base.lo;
if (config->ProbelessTrace)
top_of_ram -= TRACE_MEMORY_SIZE;
Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17553
-gerrit
commit 59d204dced98df23d70348fdea20963b9a5f0bd6
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Wed Nov 16 21:27:38 2016 +0530
soc/intel/skylake: Disable Legacy PME for Root ports
Legacy PME are enabled by default in FSP UPD region.
When Legacy PME is enabled, then an SCI is generated and should be
handled by OS and BIOS/Coreboot in collboration. OS requires some
ACPI methods (eg _L69) which help to determine the wake source and also
to clear some registers. But this infrastructure is not present as of
now in coreboot and also linux handles PMEs natively.
Hence the SCI was never handled by OS and the status bits were never
cleared i.e., PCI_EXP_STS.
For this reason the level triggered SCI will remain active and the
system will wake up as soon as it enters S3.
To fix this, diabled Legacy PME (PmSci for Root ports).
Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
---
src/soc/intel/skylake/chip_fsp20.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index f90f6bc..59115a6 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
sizeof(params->PcieRpClkReqNumber));
+ /* disable Legacy PME */
+ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));
Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17648
-gerrit
commit 3fca021012459557b7416538de15704d70d538b8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 29 21:37:42 2016 -0600
lib: put romstage_handoff implementation in own compilation unit
Instead of putting all the functions inline just put the
current implementation into a C file. That way all the implementation
innards are not exposed.
Lastly, fix up the fallout of compilation units not including the
headers they actually use.
Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/drivers/intel/fsp1_1/romstage.c | 1 +
src/include/romstage_handoff.h | 89 +-------------------
src/lib/Makefile.inc | 3 +
src/lib/romstage_handoff.c | 95 ++++++++++++++++++++++
src/mainboard/google/gru/romstage.c | 2 +
src/soc/intel/baytrail/romstage/romstage.c | 1 +
src/soc/intel/braswell/romstage/romstage.c | 1 +
src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 1 +
8 files changed, 106 insertions(+), 87 deletions(-)
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b222082..bb3e96c 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -34,6 +34,7 @@
#include <smbios.h>
#include <soc/intel/common/mrc_cache.h>
#include <stage_cache.h>
+#include <string.h>
#include <timestamp.h>
#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index b36ff9f..1a6bbf7 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -15,95 +15,10 @@
#ifndef ROMSTAGE_HANDOFF_H
#define ROMSTAGE_HANDOFF_H
-#include <stdint.h>
-#include <string.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <rules.h>
-
-/* It is the chipset's responsibility for maintaining the integrity of this
- * structure in CBMEM. For instance, if chipset code adds this structure
- * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber
- * fields it doesn't own. */
-struct romstage_handoff {
- /* Indicate if the current boot is an S3 resume. If
- * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
- * responsible for initializing this variable. Otherwise, ramstage
- * will be re-loaded from cbfs (which can be slower since it lives
- * in flash). */
- uint8_t s3_resume;
- uint8_t reboot_required;
- uint8_t reserved[2];
-};
-
-static inline int cbmem_available(void)
-{
- /* No cbmem available prior to ramstage on non-early cbmem platforms. */
- if (!ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
- return 0;
-
- return 1;
-}
-
-/* The romstage_handoff_find_or_add() function provides the necessary logic
- * for initializing the romstage_handoff structure in cbmem. Different components
- * of the romstage may be responsible for setting up different fields. Therefore
- * that same logic flow should be used for allocating and initializing the
- * structure. A newly allocated structure will be memset to 0. */
-static inline struct romstage_handoff *romstage_handoff_find_or_add(void)
-{
- struct romstage_handoff *handoff;
-
- if (!cbmem_available())
- return NULL;
-
- /* cbmem_add() first does a find and uses the old location before the
- * real add. However, it is important to know when the structure is not
- * found so it can be initialized to 0. */
- handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
-
- if (handoff)
- return handoff;
-
- handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff));
-
- if (handoff != NULL)
- memset(handoff, 0, sizeof(*handoff));
- else
- printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
-
- return handoff;
-}
-
/* Returns 0 if initialized. Else < 0 if handoff structure not added. */
-static inline int romstage_handoff_init(int is_s3_resume)
-{
- struct romstage_handoff *handoff;
-
- handoff = romstage_handoff_find_or_add();
-
- if (handoff == NULL)
- return -1;
-
- handoff->s3_resume = is_s3_resume;
-
- return 0;
-}
+int romstage_handoff_init(int is_s3_resume);
/* Return 1 if resuming or 0 if not. */
-static inline int romstage_handoff_is_resume(void)
-{
- struct romstage_handoff *handoff;
-
- if (!cbmem_available())
- return 0;
-
- handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
-
- if (handoff == NULL)
- return 0;
-
- return handoff->s3_resume;
-}
+int romstage_handoff_is_resume(void);
#endif /* ROMSTAGE_HANDOFF_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index ddade2b..4157091 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -87,6 +87,8 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c
romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
+ramstage-y += romstage_handoff.c
+romstage-y += romstage_handoff.c
romstage-y += romstage_stack.c
ramstage-y += romstage_stack.c
romstage-y += stack.c
@@ -153,6 +155,7 @@ postcar-y += cbmem_common.c
postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
postcar-y += imd_cbmem.c
postcar-y += imd.c
+postcar-y += romstage_handoff.c
bootblock-y += hexdump.c
ramstage-y += hexdump.c
diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c
new file mode 100644
index 0000000..ccabd8a
--- /dev/null
+++ b/src/lib/romstage_handoff.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <romstage_handoff.h>
+#include <rules.h>
+
+struct romstage_handoff {
+ /* Indicate if the current boot is an S3 resume. If
+ * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is
+ * responsible for initializing this variable. Otherwise, ramstage
+ * will be re-loaded from cbfs (which can be slower since it lives
+ * in flash). */
+ uint8_t s3_resume;
+ uint8_t reboot_required;
+ uint8_t reserved[2];
+};
+
+static inline int cbmem_available(void)
+{
+ /* No cbmem available prior to ramstage on non-early cbmem platforms. */
+ if (!ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
+ return 0;
+
+ return 1;
+}
+
+static struct romstage_handoff *romstage_handoff_find_or_add(void)
+{
+ struct romstage_handoff *handoff;
+
+ if (!cbmem_available())
+ return NULL;
+
+ /* cbmem_add() first does a find and uses the old location before the
+ * real add. However, it is important to know when the structure is not
+ * found so it can be initialized to 0. */
+ handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
+
+ if (handoff)
+ return handoff;
+
+ handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff));
+
+ if (handoff != NULL)
+ memset(handoff, 0, sizeof(*handoff));
+ else
+ printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
+
+ return handoff;
+}
+
+int romstage_handoff_init(int is_s3_resume)
+{
+ struct romstage_handoff *handoff;
+
+ handoff = romstage_handoff_find_or_add();
+
+ if (handoff == NULL)
+ return -1;
+
+ handoff->s3_resume = is_s3_resume;
+
+ return 0;
+}
+
+int romstage_handoff_is_resume(void)
+{
+ struct romstage_handoff *handoff;
+
+ if (!cbmem_available())
+ return 0;
+
+ handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
+
+ if (handoff == NULL)
+ return 0;
+
+ return handoff->s3_resume;
+}
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 1e2507a..55ed79a 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -19,6 +19,7 @@
#include <arch/exception.h>
#include <arch/mmu.h>
#include <cbfs.h>
+#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
#include <romstage_handoff.h>
@@ -28,6 +29,7 @@
#include <soc/sdram.h>
#include <symbols.h>
#include <soc/usb.h>
+#include <stdlib.h>
#include "pwm_regulator.h"
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 124eb6e..d457151 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -28,6 +28,7 @@
#include <program_loading.h>
#include <romstage_handoff.h>
#include <stage_cache.h>
+#include <string.h>
#include <timestamp.h>
#include <tpm.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 95880e8..0125847 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -29,6 +29,7 @@
#include <device/pci_def.h>
#include <elog.h>
#include <romstage_handoff.h>
+#include <string.h>
#include <timestamp.h>
#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 49bdedb..49d9a94 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -19,6 +19,7 @@
#include <lib.h>
#include <arch/io.h>
#include <arch/cbfs.h>
+#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <program_loading.h>