coreboot-gerrit November 2016

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New patch to review for coreboot: lib: put romstage_handoff implementation in own compilation unit
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17648 -gerrit commit 69f0909c159e74bbe7046bdb1b699e7342bc63fb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:37:42 2016 -0600 lib: put romstage_handoff implementation in own compilation unit Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/romstage_handoff.h | 89 +-------------------------------------- src/lib/Makefile.inc | 3 ++ src/lib/romstage_handoff.c | 95 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 87 deletions(-) diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index b36ff9f..1a6bbf7 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -15,95 +15,10 @@ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H -#include <stdint.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <rules.h> - -/* It is the chipset's responsibility for maintaining the integrity of this - * structure in CBMEM. For instance, if chipset code adds this structure - * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber - * fields it doesn't own. */ -struct romstage_handoff { - /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is - * responsible for initializing this variable. Otherwise, ramstage - * will be re-loaded from cbfs (which can be slower since it lives - * in flash). */ - uint8_t s3_resume; - uint8_t reboot_required; - uint8_t reserved[2]; -}; - -static inline int cbmem_available(void) -{ - /* No cbmem available prior to ramstage on non-early cbmem platforms. */ - if (!ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - return 0; - - return 1; -} - -/* The romstage_handoff_find_or_add() function provides the necessary logic - * for initializing the romstage_handoff structure in cbmem. Different components - * of the romstage may be responsible for setting up different fields. Therefore - * that same logic flow should be used for allocating and initializing the - * structure. A newly allocated structure will be memset to 0. */ -static inline struct romstage_handoff *romstage_handoff_find_or_add(void) -{ - struct romstage_handoff *handoff; - - if (!cbmem_available()) - return NULL; - - /* cbmem_add() first does a find and uses the old location before the - * real add. However, it is important to know when the structure is not - * found so it can be initialized to 0. */ - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff) - return handoff; - - handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); - - if (handoff != NULL) - memset(handoff, 0, sizeof(*handoff)); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return handoff; -} - /* Returns 0 if initialized. Else < 0 if handoff structure not added. */ -static inline int romstage_handoff_init(int is_s3_resume) -{ - struct romstage_handoff *handoff; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) - return -1; - - handoff->s3_resume = is_s3_resume; - - return 0; -} +int romstage_handoff_init(int is_s3_resume); /* Return 1 if resuming or 0 if not. */ -static inline int romstage_handoff_is_resume(void) -{ - struct romstage_handoff *handoff; - - if (!cbmem_available()) - return 0; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) - return 0; - - return handoff->s3_resume; -} +int romstage_handoff_is_resume(void); #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ddade2b..4157091 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -87,6 +87,8 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +ramstage-y += romstage_handoff.c +romstage-y += romstage_handoff.c romstage-y += romstage_stack.c ramstage-y += romstage_stack.c romstage-y += stack.c @@ -153,6 +155,7 @@ postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c postcar-y += imd_cbmem.c postcar-y += imd.c +postcar-y += romstage_handoff.c bootblock-y += hexdump.c ramstage-y += hexdump.c diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c new file mode 100644 index 0000000..ccabd8a --- /dev/null +++ b/src/lib/romstage_handoff.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <romstage_handoff.h> +#include <rules.h> + +struct romstage_handoff { + /* Indicate if the current boot is an S3 resume. If + * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * responsible for initializing this variable. Otherwise, ramstage + * will be re-loaded from cbfs (which can be slower since it lives + * in flash). */ + uint8_t s3_resume; + uint8_t reboot_required; + uint8_t reserved[2]; +}; + +static inline int cbmem_available(void) +{ + /* No cbmem available prior to ramstage on non-early cbmem platforms. */ + if (!ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + return 0; + + return 1; +} + +static struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + struct romstage_handoff *handoff; + + if (!cbmem_available()) + return NULL; + + /* cbmem_add() first does a find and uses the old location before the + * real add. However, it is important to know when the structure is not + * found so it can be initialized to 0. */ + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff) + return handoff; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + + if (handoff != NULL) + memset(handoff, 0, sizeof(*handoff)); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + return handoff; +} + +int romstage_handoff_init(int is_s3_resume) +{ + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + if (handoff == NULL) + return -1; + + handoff->s3_resume = is_s3_resume; + + return 0; +} + +int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + if (!cbmem_available()) + return 0; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +}

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New patch to review for coreboot: romstage_handoff: add helper to determine resume status
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17647 -gerrit commit 81652739ec03ce81d7aa221291f91c684e772fac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:22:42 2016 -0600 romstage_handoff: add helper to determine resume status Instead of having callers query the romstage handoff resume status by inspecing the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/acpi_s3.c | 9 +-------- src/include/romstage_handoff.h | 16 ++++++++++++++++ src/lib/prog_loaders.c | 25 ++++++++++++------------- src/soc/intel/apollolake/chip.c | 4 +--- src/soc/intel/quark/chip.c | 5 +---- src/soc/intel/skylake/chip_fsp20.c | 7 +------ 6 files changed, 32 insertions(+), 34 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ffec64d..f3cb097 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -32,14 +32,7 @@ int acpi_slp_type = -1; #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) int acpi_get_sleep_type(void) { - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - return ACPI_S0; - } else if (handoff->s3_resume) { + if (romstage_handoff_is_resume()) { printk(BIOS_DEBUG, "S3 Resume.\n"); return ACPI_S3; } else { diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 175cf09..b36ff9f 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -90,4 +90,20 @@ static inline int romstage_handoff_init(int is_s3_resume) return 0; } +/* Return 1 if resuming or 0 if not. */ +static inline int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + if (!cbmem_available()) + return 0; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +} + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3a6f2e2..58c1a8a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -85,19 +85,19 @@ static void ramstage_cache_invalid(void) } } -static void run_ramstage_from_resume(struct romstage_handoff *handoff, - struct prog *ramstage) +static void run_ramstage_from_resume(struct prog *ramstage) { - if (handoff != NULL && handoff->s3_resume) { - /* Load the cached ramstage to runtime location. */ - stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); - - if (prog_entry(ramstage) != NULL) { - printk(BIOS_DEBUG, "Jumping to image.\n"); - prog_run(ramstage); - } - ramstage_cache_invalid(); + if (!romstage_handoff_is_resume()) + return; + + /* Load the cached ramstage to runtime location. */ + stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); + + if (prog_entry(ramstage) != NULL) { + printk(BIOS_DEBUG, "Jumping to image.\n"); + prog_run(ramstage); } + ramstage_cache_invalid(); } static int load_relocatable_ramstage(struct prog *ramstage) @@ -136,8 +136,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_NO_STAGE_CACHE) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - run_ramstage_from_resume(romstage_handoff_find_or_add(), - &ramstage); + run_ramstage_from_resume(&ramstage); if (prog_locate(&ramstage)) goto fail; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ef5908c..32d68cc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -260,7 +260,6 @@ static void set_power_limits(void) static void soc_init(void *data) { struct global_nvs_t *gnvs; - struct romstage_handoff *handoff; /* Save VBT info and mapping */ vbt = vbt_get(&vbt_rdev); @@ -269,8 +268,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 150df12..5e80463 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -102,8 +102,6 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { - struct romstage_handoff *handoff; - /* Validate the temperature settings */ ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS @@ -120,8 +118,7 @@ static void chip_init(void *chip_info) | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); /* Perform silicon specific init. */ - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f90f6bc..0768779 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -35,13 +35,8 @@ void soc_init_pre_device(void *chip_info) { - struct romstage_handoff *handoff; - - /* Get S3 status to pass to silicon init. */ - handoff = romstage_handoff_find_or_add(); - /* Perform silicon specific init. */ - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev)

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New patch to review for coreboot: romstage_handoff: remove code duplication
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17646 -gerrit commit 84d5707ae186e2d0830dec9f2ddca847e80ab55e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 17:43:04 2016 -0600 romstage_handoff: remove code duplication The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/amd/car/post_cache_as_ram.c | 9 +----- src/cpu/intel/haswell/romstage.c | 7 +---- src/drivers/intel/fsp1_1/romstage.c | 10 ++---- src/drivers/intel/fsp2_0/memory_init.c | 7 +---- src/include/romstage_handoff.h | 43 +++++++++++++++++++++++--- src/northbridge/intel/sandybridge/early_init.c | 8 +---- src/soc/intel/baytrail/romstage/romstage.c | 7 +---- src/soc/intel/broadwell/romstage/romstage.c | 9 +----- src/soc/intel/fsp_baytrail/romstage/romstage.c | 7 +---- 9 files changed, 47 insertions(+), 60 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 296adc9..e0ee93c 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -129,14 +129,7 @@ void post_cache_as_ram(void) prepare_romstage_ramstack(s3resume); - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3resume; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - } + romstage_handoff_init(s3resume) /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 48920b3..7eb115c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -172,7 +172,6 @@ void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; - struct romstage_handoff *handoff; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -245,11 +244,7 @@ void romstage_common(const struct romstage_params *params) #endif } - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = wake_from_s3; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(wake_from_s3); post_code(0x3f); if (IS_ENABLED(CONFIG_LPC_TPM)) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 97379b2..b222082 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -99,7 +99,6 @@ void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) void romstage_common(struct romstage_params *params) { const struct mrc_saved_data *cache; - struct romstage_handoff *handoff; struct pei_data *pei_data; post_code(0x32); @@ -165,14 +164,9 @@ void romstage_common(struct romstage_params *params) mainboard_save_dimm_info(params); /* Create romstage handof information */ - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (params->power_state->prev_sleep_state == - ACPI_S3); - else { - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (romstage_handoff_init( + params->power_state->prev_sleep_state == ACPI_S3) < 0) hard_reset(); - } /* * Initialize the TPM, unless the TPM was already initialized diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..c0cb5d3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -117,7 +117,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; - struct romstage_handoff *handoff; if (fsp_find_reserved_memory(&fsp_mem)) die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n"); @@ -144,11 +143,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3wake; - else - printk(BIOS_SPEW, "Romstage handoff structure not added!\n"); + romstage_handoff_init(s3wake); } static const char *mrc_cache_get_region_name(void) diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 4aba2ce..175cf09 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -18,6 +18,8 @@ #include <stdint.h> #include <string.h> #include <cbmem.h> +#include <console/console.h> +#include <rules.h> /* It is the chipset's responsibility for maintaining the integrity of this * structure in CBMEM. For instance, if chipset code adds this structure @@ -34,6 +36,15 @@ struct romstage_handoff { uint8_t reserved[2]; }; +static inline int cbmem_available(void) +{ + /* No cbmem available prior to ramstage on non-early cbmem platforms. */ + if (!ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + return 0; + + return 1; +} + /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -43,18 +54,40 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) { struct romstage_handoff *handoff; + if (!cbmem_available()) + return NULL; + /* cbmem_add() first does a find and uses the old location before the * real add. However, it is important to know when the structure is not * found so it can be initialized to 0. */ handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (handoff == NULL) { - handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); - if (handoff != NULL) - memset(handoff, 0, sizeof(*handoff)); - } + if (handoff) + return handoff; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + + if (handoff != NULL) + memset(handoff, 0, sizeof(*handoff)); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); return handoff; } +/* Returns 0 if initialized. Else < 0 if handoff structure not added. */ +static inline int romstage_handoff_init(int is_s3_resume) +{ + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + if (handoff == NULL) + return -1; + + handoff->s3_resume = is_s3_resume; + + return 0; +} + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index ef97a1a..16ea29d 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -227,13 +227,7 @@ void sandybridge_early_initialization(int chipset_type) void northbridge_romstage_finalize(int s3resume) { - struct romstage_handoff *handoff; - MCHBAR16(SSKPD) = 0xCAFE; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3resume; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a61b571..124eb6e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -210,7 +210,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct romstage_handoff *handoff; struct chipset_power_state *ps; int prev_sleep_state; @@ -232,11 +231,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(prev_sleep_state == ACPI_S3); if (IS_ENABLED(CONFIG_LPC_TPM)) { init_tpm(prev_sleep_state == ACPI_S3); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 44df88c..e0c329b 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -89,8 +89,6 @@ void * asmlinkage romstage_main(unsigned long bist, /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct romstage_handoff *handoff; - post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); @@ -114,12 +112,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (params->power_state->prev_sleep_state == - ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handof_init(params->power_state->prev_sleep_state == ACPI_S3); #if CONFIG_LPC_TPM init_tpm(params->power_state->prev_sleep_state == ACPI_S3); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a7ed414..9d204d1 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -218,7 +218,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; - struct romstage_handoff *handoff; timestamp_add_now(TS_AFTER_INITRAM); @@ -257,11 +256,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(prev_sleep_state == ACPI_S3); post_code(0x4f);

1 0

Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
by Naresh Solanki 30 Nov '16

30 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435 -gerrit commit 508e3a5f75cc8c57860d6be2088ca7089ead3f20 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 15 19:35:33 2016 +0530 mb/intel/kblrvp: Use common lib spd_bin to get spd Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/romstage.c | 21 +++++-- src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 ----- src/mainboard/intel/kblrvp/spd/spd.c | 94 ----------------------------- src/mainboard/intel/kblrvp/spd/spd.h | 18 +----- src/mainboard/intel/kblrvp/spd/spd_util.c | 34 ----------- 6 files changed, 19 insertions(+), 163 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 446266d..e53c446 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index d4fd113..bc39a80 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -23,20 +23,33 @@ #include <soc/gpio.h> #include "spd/spd.h" #include <string.h> +#include <spd_bin.h> +#include "board_id.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; + struct region_device spd_rdev; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + /* RVP3 SPD */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { + die("spd.bin not found\n"); + } + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 83f4831..0c864fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100 SPD_SOURCES += empty # 5b101 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB SPD_SOURCES += empty # 7b111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c deleted file mode 100644 index 1abee81..0000000 --- a/src/mainboard/intel/kblrvp/spd/spd.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - case SPD_DRAM_LPDDR3_INTEL: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index a9f8645..3ef2dd8 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -15,25 +15,11 @@ */ #ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #include <gpio.h> #include "../gpio.h" -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0B -#define SPD_DRAM_LPDDR3 0x0F -#define SPD_DRAM_LPDDR3_INTEL 0xF1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #define RCOMP_TARGET_PARAMS 0x5 @@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -uintptr_t mainboard_get_spd_data(void); -int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9ffc8ee..181af9f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - int spd_index, spd_span; - size_t spd_file_len; - - spd_index = (get_board_id() >> 5) & 0xF; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - spd_span = spd_index * SPD_LEN; - return (uintptr_t)(spd_file + spd_span); -} - -int mainboard_has_dual_channel_mem(void) -{ - return 1; -}

1 0

Patch set updated for coreboot: lib: Add library to handle SPD data in CBFS or DIMM
by Naresh Solanki 30 Nov '16

30 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17434 -gerrit commit f2938eb3715a2b8905c373f0be48219bb318aba2 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Oct 26 19:43:14 2016 +0530 lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/Kconfig | 25 ++++++++ src/include/spd_bin.h | 57 +++++++++++++++++ src/lib/Makefile.inc | 18 ++++++ src/lib/spd_bin.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 268 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 610be56..77d13d1 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. +config GENERIC_SPD_BIN + bool + default n + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 2 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + config BOARD_ID_AUTO bool default n diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h new file mode 100644 index 0000000..a0c1bbd --- /dev/null +++ b/src/include/spd_bin.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_BIN_H +#define SPD_BIN_H + +#include <arch/early_variables.h> +#include <stdint.h> +#include <commonlib/region.h> + +#define SPD_PAGE_LEN 256 +#define SPD_PAGE_LEN_DDR4 512 +#define SPD_PAGE_0 (0x6C >> 1) +#define SPD_PAGE_1 (0x6E >> 1) +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0B +#define SPD_DRAM_LPDDR3_INTEL 0xF1 +#define SPD_DRAM_LPDDR3_JEDEC 0x0F +#define SPD_DRAM_DDR4 0x0C +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_SPD_PART_OFF 128 +#define DDR3_SPD_PART_LEN 18 +#define LPDDR3_SPD_PART_OFF 128 +#define LPDDR3_SPD_PART_LEN 18 +#define DDR4_SPD_PART_OFF 329 +#define DDR4_SPD_PART_LEN 20 +#define LPDDR4_SPD_PART_OFF 329 +#define LPDDR4_SPD_PART_LEN 20 + +struct spd_block { + u8 *spd_array[CONFIG_DIMM_MAX]; + /* Length of each dimm */ + u16 len; +}; + +void print_spd_info(uint8_t spd[]); +/* Return 0 on success & -1 on failure */ +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); +void dump_spd_info(struct spd_block *blk); +void get_spd_smbus(struct spd_block *blk); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ddade2b..0480eec 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -279,3 +279,21 @@ subdirs-y += ../../3rdparty/libhwbase ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE + +romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c + +LIB_SPD_BIN = $(obj)/spd.bin + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(LIB_SPD_BIN): $(LIB_SPD_DEPS) + for f in $(LIB_SPD_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +spd.bin-file := $(LIB_SPD_BIN) +spd.bin-type := spd diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c new file mode 100644 index 0000000..343d48a --- /dev/null +++ b/src/lib/spd_bin.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <spd_bin.h> +#include <string.h> +#include <device/early_smbus.h> + +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; + +void dump_spd_info(struct spd_block *blk) +{ + u8 i; + + for (i = 0; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { + printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); + print_spd_info(blk->spd_array[i]); + } +} + +void print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; + const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + printk(BIOS_INFO, "LPDDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], + LPDDR3_SPD_PART_LEN); + spd_name[LPDDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_DDR4: + printk(BIOS_INFO, "DDR4\n"); + memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); + spd_name[DDR4_SPD_PART_LEN] = 0; + ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + devw = spd_devw[spd[12] & 7]; + busw = spd_busw[spd[13] & 7]; + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void update_spd_len(struct spd_block *blk) +{ + u8 i, j = 0; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL) + j |= blk->spd_array[i][SPD_DRAM_TYPE]; + + /* If spd used is DDR4, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; +} + +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) +{ + struct cbfsf fh; + + uint32_t cbfs_type = CBFS_TYPE_SPD; + + cbfs_boot_locate(&fh, "spd.bin", &cbfs_type); + cbfs_file_data(spd_rdev, &fh); + return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, + CONFIG_DIMM_SPD_SIZE); +} + +static void get_spd(u8 *spd, u8 addr) +{ + u16 i; + /* Assuming addr is 8 bit address, make it 7 bit */ + addr = addr >> 1; + if (smbus_read_byte(0, addr, 0) == 0xff) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", + addr << 1); + /* Make sure spd is zeroed if dimm doesn't exist. */ + memset(spd, 0, CONFIG_DIMM_SPD_SIZE); + return; + } + + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i] = smbus_read_byte(0, addr, i); + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) { + /* Switch to page 1 */ + smbus_write_byte(0, SPD_PAGE_1, 0, 0); + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i); + /* Restore to page 0 */ + smbus_write_byte(0, SPD_PAGE_0, 0, 0); + } +} + +void get_spd_smbus(struct spd_block *blk) +{ + u8 i, j; + unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); + + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, + 0xA0 + (i << 1)); + blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + } + + for (j = i; j < CONFIG_DIMM_MAX; j++) + blk->spd_array[j] = NULL; + + update_spd_len(blk); +}

1 0

New patch to review for coreboot: nb/intel/gm45: Clear GTT correctly for IOMMU (igd)
by Damien Zammit 30 Nov '16

30 Nov '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17645 -gerrit commit 8684bf8685a58fcc13792d1d6cf3a6c706677d14 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Nov 30 14:32:20 2016 +1100 nb/intel/gm45: Clear GTT correctly for IOMMU (igd) Bit 11 of BDF(0,0,0), GGC(0x52) is actually the correct bit for detecting VT mode on IGD, not bit 10, according to GM45 Intel chipset datasheet. Now we use the correct bit for detecting VT mode on IGD. UNTESTED ON HW. Change-Id: I60268072619253443a04e61c9617f2260d5a750c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/gm45/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 77aba94..76432fb 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,8 +46,8 @@ void init_iommu() MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ /* clear GTT */ - u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); - if (gtt & 0x400) { /* VT mode */ + u16 ggc = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); + if (ggc & 0x800) { /* VT mode */ pci_devfn_t igd = PCI_DEV(0, 2, 0); /* setup somewhere */

1 0

Patch set updated for coreboot: mainboard/intel/kblrvp: Enabling Kaby Lake RVP7
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17637 -gerrit commit f85b46fd0f3dbd876f61a4405477fb39c5ae1265 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 16:51:08 2016 +0530 mainboard/intel/kblrvp: Enabling Kaby Lake RVP7 Add support for Kaby Lake RVP7 board * Add RVP7 board support in Kconfig * Override default descriptor and ME binary paths in Kconfig since those binaries will differ for RVP3 and RVP7 * Add RVP7 board name in board_info.txt and Kconfig.name * Add devicetree.cb for RVP7 in the variants path * Add gpio.h for RVP7 in variants/include/variant path * Made board specific code for retrieving spd, i.e., in RVP7 there is non-soldered DIMMs, so SPD is read through smbus, unlike RVP3 where memory DIMMs are soldered down with board. Hence for RVP3, the spd binaries will be fixed and can be kept as binary file in cbfs. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP7 Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 17 +- src/mainboard/intel/kblrvp/Kconfig.name | 2 + src/mainboard/intel/kblrvp/board_info.txt | 2 +- src/mainboard/intel/kblrvp/romstage.c | 10 +- .../intel/kblrvp/variants/rvp7/devicetree.cb | 267 +++++++++++++++++++++ .../kblrvp/variants/rvp7/include/variant/gpio.h | 221 +++++++++++++++++ 6 files changed, 513 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 10752e7..2291472 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_KBLRVP3 +if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -50,7 +50,8 @@ config MAINBOARD_DIR config VARIANT_DIR string - default "rvp3" + default "rvp3" if BOARD_INTEL_KBLRVP3 + default "rvp7" if BOARD_INTEL_KBLRVP7 config MAINBOARD_PART_NUMBER string @@ -76,4 +77,16 @@ config GBB_HWID config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7 + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7 endif diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name index 66ec552..e697252 100644 --- a/src/mainboard/intel/kblrvp/Kconfig.name +++ b/src/mainboard/intel/kblrvp/Kconfig.name @@ -1,2 +1,4 @@ config BOARD_INTEL_KBLRVP3 bool "Kabylake LPDDR3 RVP3" +config BOARD_INTEL_KBLRVP7 + bool "Kabylake DDR3L RVP7" diff --git a/src/mainboard/intel/kblrvp/board_info.txt b/src/mainboard/intel/kblrvp/board_info.txt index 2c48625..a3fb505 100644 --- a/src/mainboard/intel/kblrvp/board_info.txt +++ b/src/mainboard/intel/kblrvp/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Intel -Board name: Kblrvp Kabylake RVP3 LPDDR3 +Board name: Kabylake RVP Reference Board Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 26c203b..0c79976 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -41,9 +41,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - mem_cfg->DqPinsInterleaved = 0; - - get_spd_cbfs(&blk, spd_index, 1); + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + mem_cfg->DqPinsInterleaved = 0; + get_spd_cbfs(&blk, spd_index, 1); + } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + } dump_spd_info(&blk); mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb new file mode 100644 index 0000000..e79c046 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -0,0 +1,267 @@ +chip soc/intel/skylake + + # SATA port 0 + register "EnableSata" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + + # Enable deep Sx states + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "FspSkipMpInit" = "1" + + # Enable Root ports. + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + + # RP 9 uses SRCCLKREQ5# + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkReqNumber[8]" = "1" + + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_G5" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h new file mode 100644 index 0000000..7a8314e --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP7_H +#define _GPIORVP7_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + + +/* GPE_EC_WAKE */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* CHROMEEC in RVP */ +#define EC_SCI_GPI GPP_E16 +#define EC_SMI_GPI GPP_E15 +/* + * Gpio based irq for touchpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define KBLRVP_TOUCHPAD_IRQ 33 + +#define KBLRVP_TOUCH_IRQ 31 + +#define BOARD_TOUCHPAD_NAME "touchpad" +#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ +#define BOARD_TOUCHPAD_I2C_BUS 0 +#define BOARD_TOUCHPAD_I2C_ADDR 0x20 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES), +/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES), +/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES), +/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP), +/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_D9, NONE, DEEP), +/* SD_D3_WAKE */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), +/* EN_PP3300_DX_CAM */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), +/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), +/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* AUDIO_IRQ */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), +/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_NF(GPD7, NONE, DEEP, NF1), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + + +#endif + +#endif +

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Patch set updated for coreboot: soc/intel/common: Add suppport for Extended VBT
by Abhay Kumar 30 Nov '16

30 Nov '16

Abhay Kumar (abhay.kumar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17585 -gerrit commit b5d0c8416d31c5f3cddccfe8b5dd177e5aa478f0 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Wed Nov 23 10:56:48 2016 -0800 soc/intel/common: Add suppport for Extended VBT With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> --- src/commonlib/include/commonlib/cbmem_id.h | 4 +- src/soc/intel/common/gma.h | 153 ++++++++++++++++++++--------- src/soc/intel/common/opregion.c | 19 +++- 3 files changed, 128 insertions(+), 48 deletions(-) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 0d2a7c3..0e9c313 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -67,6 +67,7 @@ #define CBMEM_ID_VPD 0x56504420 #define CBMEM_ID_WIFI_CALIBRATION 0x57494649 #define CBMEM_ID_EC_HOSTEVENT 0x63ccbbc3 +#define CBMEM_ID_EXT_VBT 0x69866684 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -114,5 +115,6 @@ { CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \ { CBMEM_ID_VPD, "VPD " }, \ { CBMEM_ID_WIFI_CALIBRATION, "WIFI CLBR " }, \ - { CBMEM_ID_EC_HOSTEVENT, "EC HOSTEVENT"}, + { CBMEM_ID_EC_HOSTEVENT, "EC HOSTEVENT"}, \ + { CBMEM_ID_EXT_VBT, "EXT VBT"}, #endif /* _CBMEM_ID_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h index c019286..4978835 100644 --- a/src/soc/intel/common/gma.h +++ b/src/soc/intel/common/gma.h @@ -28,14 +28,17 @@ /* mailbox 0: header */ typedef struct { - u8 signature[16]; - u32 size; - u32 version; - u8 sbios_version[32]; - u8 vbios_version[16]; - u8 driver_version[16]; - u32 mailboxes; - u8 reserved[164]; + u8 signature[16]; /* Offset 0 OpRegion signature */ + u32 size; /* Offset 16 OpRegion size */ + u32 version; /* Offset 20 OpRegion structure version */ + u8 sbios_version[32]; /* Offset 24 System BIOS build version */ + u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ + u8 driver_version[16]; /* Offset 72 Graphic driver build version */ + u32 mailboxes; /* Offset 88 Mailboxes supported */ + u32 dmod; /* Offset 92 Driver Model */ + u32 pcon; /* Offset 96 Platform Capabilities */ + u16 dver[16]; /* Offset 100 GOP Version */ + u8 reserved[124]; /* Offset 132 Reserved */ } __attribute__((packed)) opregion_header_t; #define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" @@ -55,51 +58,100 @@ typedef struct { /* mailbox 1: public ACPI methods */ typedef struct { - u32 drdy; - u32 csts; - u32 cevt; - u8 reserved1[20]; - u32 didl[8]; - u32 cpdl[8]; - u32 cadl[8]; - u32 nadl[8]; - u32 aslp; - u32 tidx; - u32 chpd; - u32 clid; - u32 cdck; - u32 sxsw; - u32 evts; - u32 cnot; - u32 nrdy; - u8 reserved2[60]; + u32 drdy; /* Offset 0 Driver readiness */ + u32 csts; /* Offset 4 Status */ + u32 cevt; /* Offset 8 Current event */ + u8 reserved[20]; /* Offset 12 Reserved */ + u32 didl; /* Offset 32 Supported display device 1 */ + u32 ddl2; /* Offset 36 Supported display device 2 */ + u32 ddl3; /* Offset 40 Supported display device 3 */ + u32 ddl4; /* Offset 44 Supported display device 4 */ + u32 ddl5; /* Offset 48 Supported display device 5 */ + u32 ddl6; /* Offset 52 Supported display device 6 */ + u32 ddl7; /* Offset 56 Supported display device 7 */ + u32 ddl8; /* Offset 60 Supported display device 8 */ + u32 cpdl; /* Offset 64 Currently present display device 1 */ + u32 cpl2; /* Offset 68 Currently present display device 2 */ + u32 cpl3; /* Offset 72 Currently present display device 3 */ + u32 cpl4; /* Offset 76 Currently present display device 4 */ + u32 cpl5; /* Offset 80 Currently present display device 5 */ + u32 cpl6; /* Offset 84 Currently present display device 6 */ + u32 cpl7; /* Offset 88 Currently present display device 7 */ + u32 cpl8; /* Offset 92 Currently present display device 8 */ + u32 cadl; /* Offset 96 Currently active display device 1 */ + u32 cal2; /* Offset 100 Currently active display device 2 */ + u32 cal3; /* Offset 104 Currently active display device 3 */ + u32 cal4; /* Offset 108 Currently active display device 4 */ + u32 cal5; /* Offset 112 Currently active display device 5 */ + u32 cal6; /* Offset 116 Currently active display device 6 */ + u32 cal7; /* Offset 120 Currently active display device 7 */ + u32 cal8; /* Offset 124 Currently active display device 8 */ + u32 nadl; /* Offset 128 Next active device 1 */ + u32 ndl2; /* Offset 132 Next active device 2 */ + u32 ndl3; /* Offset 136 Next active device 3 */ + u32 ndl4; /* Offset 140 Next active device 4 */ + u32 ndl5; /* Offset 144 Next active device 5 */ + u32 ndl6; /* Offset 148 Next active device 6 */ + u32 ndl7; /* Offset 152 Next active device 7 */ + u32 ndl8; /* Offset 156 Next active device 8 */ + u32 aslp; /* Offset 160 ASL sleep timeout */ + u32 tidx; /* Offset 164 Toggle table index */ + u32 chpd; /* Offset 168 Current hot plug enable indicator */ + u32 clid; /* Offset 172 Current lid state indicator */ + u32 cdck; /* Offset 176 Current docking state indicator */ + u32 sxsw; /* Offset 180 Display Switch notification on Sx State resume */ + u32 evts; /* Offset 184 Events supported by ASL */ + u32 cnot; /* Offset 188 Current OS Notification */ + u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ + u32 ddl9; /* Offset 196 Extended Supported display device 1 */ + u32 dd10; /* Offset 200 Extended Supported display device 2 */ + u32 dd11; /* Offset 204 Extended Supported display device 3 */ + u32 dd12; /* Offset 208 Extended Supported display device 4 */ + u32 dd13; /* Offset 212 Extended Supported display device 5 */ + u32 dd14; /* Offset 216 Extended Supported display device 6 */ + u32 dd15; /* Offset 220 Extended Supported display device 7 */ + u32 cpl9; /* Offset 224 Extended Currently present device 1 */ + u32 cp10; /* Offset 228 Extended Currently present device 2 */ + u32 cp11; /* Offset 232 Extended Currently present device 3 */ + u32 cp12; /* Offset 236 Extended Currently present device 4 */ + u32 cp13; /* Offset 240 Extended Currently present device 5 */ + u32 cp14; /* Offset 244 Extended Currently present device 6 */ + u32 cp15; /* Offset 248 Extended Currently present device 7 */ + u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ } __attribute__((packed)) opregion_mailbox1_t; /* mailbox 2: software sci interface */ typedef struct { - u32 scic; - u32 parm; - u32 dslp; - u8 reserved[244]; + u32 scic; /* Offset 0 Software SCI function number parameters */ + u32 parm; /* Offset 0 Software SCI function number parameters */ + u32 dslp; /* Offset 8 Driver sleep timeout */ + u8 reserved[244]; /* Offset 12 Reserved */ } __attribute__((packed)) opregion_mailbox2_t; /* mailbox 3: power conservation */ typedef struct { - u32 ardy; - u32 aslc; - u32 tche; - u32 alsi; - u32 bclp; - u32 pfit; - u32 cblv; - u16 bclm[20]; - u32 cpfm; - u32 epfm; - u8 plut[74]; - u32 pfmb; - u32 ccdv; - u32 pcft; - u8 reserved[94]; + u32 ardy; /* Offset 0 Driver readiness */ + u32 aslc; /* Offset 4 ASLE interrupt command / status */ + u32 tche; /* Offset 8 Technology enabled indicator */ + u32 alsi; /* Offset 12 Current ALS illuminance reading */ + u32 bclp; /* Offset 16 Backlight britness to set */ + u32 pfit; /* Offset 20 Panel fitting Request */ + u32 cblv; /* Offset 24 Brightness Current State */ + u16 bclm[20]; /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */ + u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ + u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ + u8 plut[74]; /* Offset 76 Panel Look Up Table */ + u32 pfmb; /* Offset 150 PWM Frequency and Minimum Brightness */ + u32 ccdv; /* Offset 154 Color Correction Default Values */ + u32 pcft; /* Offset 158 Power Conservation Features */ + u32 srot; /* Offset 162 Supported Rotation angle */ + u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ + u64 fdsp; /* Offset 170 FFS Display Physical address */ + u32 fdss; /* Offset 178 FFS Display Size */ + u32 stat; /* Offset 182 State Indicator */ + u64 rvda; /* Offset 186 (Igd opregion offset 0x3BAh) Physical address of Raw VBT data */ + u32 rvds; /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */ + u8 reserved[58]; /* Offset 198 Reserved */ } __attribute__((packed)) opregion_mailbox3_t; #define IGD_BACKLIGHT_BRIGHTNESS 0xff @@ -111,9 +163,16 @@ typedef struct { /* mailbox 4: vbt */ typedef struct { - u8 gvd1[7168]; + u8 gvd1[6*KiB]; } __attribute__((packed)) opregion_vbt_t; +/* Mailbox 5: BIOS to Driver Notification Extension */ +typedef struct { + u32 phed; /* Offset 7168 Panel Header */ + u8 bddc[256]; /* Offset 7172 Panel EDID */ + u8 reserved[764]; /* Offset 7428 764 bytes */ +} __attribute__((packed)) opregion_mailbox5_t; + /* IGD OpRegion */ typedef struct { opregion_header_t header; @@ -121,6 +180,8 @@ typedef struct { opregion_mailbox2_t mailbox2; opregion_mailbox3_t mailbox3; opregion_vbt_t vbt; + opregion_mailbox5_t mailbox5; + } __attribute__((packed)) igd_opregion_t; /* Intel Video BIOS (Option ROM) */ diff --git a/src/soc/intel/common/opregion.c b/src/soc/intel/common/opregion.c index 44c27fb..88fb916 100644 --- a/src/soc/intel/common/opregion.c +++ b/src/soc/intel/common/opregion.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <string.h> +#include <cbmem.h> #include "gma.h" #include "opregion.h" @@ -24,6 +25,7 @@ int init_igd_opregion(igd_opregion_t *opregion) { struct region_device vbt_rdev; optionrom_vbt_t *vbt; + optionrom_vbt_t *ext_vbt; if (locate_vbt(&vbt_rdev) == CB_ERR) { printk(BIOS_ERR, "VBT not found\n"); @@ -43,8 +45,23 @@ int init_igd_opregion(igd_opregion_t *opregion) sizeof(opregion->header.signature)); memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, ARRAY_SIZE(vbt->coreblock_biosbuild)); - memcpy(opregion->vbt.gvd1, vbt, MIN(vbt->hdr_vbt_size, + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); + + if (ext_vbt == NULL) { + printk(BIOS_ERR, "Unable to add Ext VBT to cbmem!\n"); + return 0; + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size <6k */ + memcpy(opregion->vbt.gvd1, vbt, MIN(vbt->hdr_vbt_size, sizeof(opregion->vbt.gvd1))); + } /* 8KiB */ opregion->header.size = sizeof(igd_opregion_t) / KiB;

1 0

Patch merged into coreboot/master: util/lint: Add check for symbolic links in the coreboot tree
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit adcba9438d54481a71f2e90c8fa1014c7ee273ed Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 28 13:16:24 2016 -0700 util/lint: Add check for symbolic links in the coreboot tree Because of the varied environments that coreboot is built under, we don't want to have symbolic links in the tree. Change-Id: I4cf9d95a437626cb52e3032a5e6cba83320a334b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17633 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/17633 for details. -gerrit

1 0

Patch merged into coreboot/master: mb/google/oak: replace symbolic links
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 19424a157df596b814a7c95bac219b1f95fe04ff Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 28 14:30:38 2016 -0700 mb/google/oak: replace symbolic links These three files were added as symbolic links to the other files in the same directory. Delete the links, and copy the real files into their places. Because of the varied environments that coreboot is built in, we don't want to have symbolic links in the tree. These three files were the only cases of symbolic links. Change-Id: If69f40c2c4cdcabc4fdfc1d6026a91c0791756da Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/17632 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17632 for details. -gerrit

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