coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch set updated for coreboot: AGESA: Use explicit PCI IO config access in bootblock
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17531 -gerrit commit f8686c09b1d274630b1066dbeecd45be78b0dbf5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:24:12 2016 +0200 AGESA: Use explicit PCI IO config access in bootblock This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I994bb257db96300c2eb8872be6fae2a92bbabab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/agesa/hudson/bootblock.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index ff52199..32b1298 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -34,15 +34,15 @@ static void hudson_enable_rom(void) dev = PCI_DEV(0, 0x14, 3); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -52,9 +52,9 @@ static void hudson_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void)

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Patch set updated for coreboot: asus/f2a85-m msi/ms7721: Enable MMCONF early
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17565 -gerrit commit 358293cd8d643cfdab71c7dab9c972d7dfa19c10 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 08:37:15 2016 +0200 asus/f2a85-m msi/ms7721: Enable MMCONF early PCI MMCONF access only works after amd_initmmio() call. Change-Id: I5765604e178d09abdd6bb6ce7cc220bc5b35ed03 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/f2a85-m/romstage.c | 4 ++-- src/mainboard/msi/ms7721/romstage.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 0e502e7..83f6778 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -64,6 +64,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + amd_initmmio(); + #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -71,8 +73,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - amd_initmmio(); - if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */ diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 599187d..f8565ad 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -128,6 +128,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + amd_initmmio(); + #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); #endif @@ -135,8 +137,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - amd_initmmio(); - if (!cpu_init_detectedx && boot_cpu()) { /* enable SIO LPC decode */

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Patch set updated for coreboot: AGESA f14: Consolidate early P-states setting
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17564 -gerrit commit 1bc763068d198e1ece72c0280fc0017f72393381 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:03:49 2016 +0200 AGESA f14: Consolidate early P-states setting Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family14/fixme.c | 4 ++++ src/mainboard/amd/inagua/romstage.c | 4 ---- src/mainboard/amd/persimmon/romstage.c | 3 --- src/mainboard/amd/south_station/romstage.c | 3 --- src/mainboard/asrock/e350m1/romstage.c | 3 --- src/mainboard/elmex/pcm205400/romstage.c | 3 --- src/mainboard/gizmosphere/gizmo/romstage.c | 12 ------------ src/mainboard/jetway/nf81-t56n-lf/romstage.c | 3 --- src/mainboard/lippert/frontrunner-af/romstage.c | 3 --- src/mainboard/lippert/toucan-af/romstage.c | 3 --- src/mainboard/pcengines/apu1/romstage.c | 3 --- 11 files changed, 4 insertions(+), 40 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index ab10e3a..25a32bd 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -98,6 +98,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + /* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ + MsrReg = 0; + LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 151ce31..3e37e03 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time - */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index d553c1b..980ff3e 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5ef95a0..4b725c0 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,9 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 6d2cad2..7a849e4 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,9 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr(0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index d553c1b..980ff3e 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index e6276ff..1335a8f 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -37,21 +37,9 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/agesa/s3_resume.h> -#define MSR_MTRR_VARIABLE_BASE6 0x020C -#define MSR_MTRR_VARIABLE_MASK6 0x020D -#define MSR_PSTATE_CONTROL 0xC0010062 - - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - msr_t msr; - - - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - msr.lo = 0; - msr.hi = 0; - wrmsr (MSR_PSTATE_CONTROL, msr); amd_initmmio(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index ea2e11f..5f22aaa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -62,9 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 0beda77..ccb6b39 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -45,9 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 44a27ca..b2590fc 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -46,9 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index cf4f3fa..f8e6318 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -51,9 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ - __writemsr (0xc0010062, 0); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) {

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Patch set updated for coreboot: AGESA f14: Consolidate XIP cache
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17563 -gerrit commit bbaebde7f3e562b74b5e2ecf84a7c63f66e18e4b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 07:45:17 2016 +0200 AGESA f14: Consolidate XIP cache Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family14/fixme.c | 6 ++++++ src/mainboard/amd/inagua/romstage.c | 6 ------ src/mainboard/amd/persimmon/romstage.c | 7 ------- src/mainboard/amd/south_station/romstage.c | 7 ------- src/mainboard/amd/union_station/romstage.c | 7 ------- src/mainboard/asrock/e350m1/romstage.c | 7 ------- src/mainboard/elmex/pcm205400/romstage.c | 7 ------- src/mainboard/gizmosphere/gizmo/romstage.c | 11 ----------- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 7 ------- src/mainboard/lippert/frontrunner-af/romstage.c | 7 ------- src/mainboard/lippert/toucan-af/romstage.c | 7 ------- src/mainboard/pcengines/apu1/romstage.c | 7 ------- 12 files changed, 6 insertions(+), 80 deletions(-) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index d1bd0a1..ab10e3a 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -92,6 +92,12 @@ void amd_initmmio(void) PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE4); PciData = (AMD_APU_SSID << 0x10) | AMD_APU_SVID; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); } void amd_initenv(void) diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 385328c..151ce31 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -40,12 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* all cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 0aad4f5..d553c1b 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index d37ea0a..5ef95a0 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -41,13 +41,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index eddcf29..cdc5640 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -39,13 +39,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 50f3f6b..6d2cad2 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -43,13 +43,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr(0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr(0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); diff --git a/src/mainboard/elmex/pcm205400/romstage.c b/src/mainboard/elmex/pcm205400/romstage.c index 0aad4f5..d553c1b 100644 --- a/src/mainboard/elmex/pcm205400/romstage.c +++ b/src/mainboard/elmex/pcm205400/romstage.c @@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 972f5d0..e6276ff 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -47,17 +47,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF; - msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32; - wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); - - msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF; - msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32; - wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ msr.lo = 0; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3deb9c3..ea2e11f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -62,13 +62,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index cdfb31a..0beda77 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -45,13 +45,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 70cd622..44a27ca 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -46,13 +46,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index 13efcad..cf4f3fa 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -51,13 +51,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - /* - * All cores: allow caching of flash chip code and data - * (there are no cache-as-ram reliability concerns with family 14h) - */ - __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); - __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); - /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0);

1 0

Patch set updated for coreboot: mainboard/intel/kblrvp: Enabling Kaby Lake RVP7
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17637 -gerrit commit f07d030ad18b13156c41a15d74374802c9ca723c Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 16:51:08 2016 +0530 mainboard/intel/kblrvp: Enabling Kaby Lake RVP7 Add support for Kaby Lake RVP7 board * Add RVP7 board support in Kconfig * Override default descriptor and ME binary paths in Kconfig since those binaries will differ for RVP3 and RVP7 * Add RVP7 board name in board_info.txt and Kconfig.name * Add devicetree.cb for RVP7 in the variants path * Add gpio.h for RVP7 in variants/include/variant path * Made board specific code for retrieving spd, i.e., in RVP7 there is non-soldered DIMMs, so SPD is read through smbus, unlike RVP3 where memory DIMMs are soldered down with board. Hence for RVP3, the spd binaries will be fixed and can be kept as binary file in cbfs. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP7 Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 17 +- src/mainboard/intel/kblrvp/Kconfig.name | 2 + src/mainboard/intel/kblrvp/board_info.txt | 2 +- src/mainboard/intel/kblrvp/romstage.c | 26 +- .../intel/kblrvp/variants/rvp7/devicetree.cb | 267 +++++++++++++++++++++ .../kblrvp/variants/rvp7/include/variant/gpio.h | 221 +++++++++++++++++ 6 files changed, 522 insertions(+), 13 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 10752e7..2291472 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_KBLRVP3 +if BOARD_INTEL_KBLRVP3 || BOARD_INTEL_KBLRVP7 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -50,7 +50,8 @@ config MAINBOARD_DIR config VARIANT_DIR string - default "rvp3" + default "rvp3" if BOARD_INTEL_KBLRVP3 + default "rvp7" if BOARD_INTEL_KBLRVP7 config MAINBOARD_PART_NUMBER string @@ -76,4 +77,16 @@ config GBB_HWID config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp3.bin" if BOARD_INTEL_KBLRVP3 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.rvp7.bin" if BOARD_INTEL_KBLRVP7 + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp3.bin" if BOARD_INTEL_KBLRVP3 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.rvp7.bin" if BOARD_INTEL_KBLRVP7 endif diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name index 66ec552..e697252 100644 --- a/src/mainboard/intel/kblrvp/Kconfig.name +++ b/src/mainboard/intel/kblrvp/Kconfig.name @@ -1,2 +1,4 @@ config BOARD_INTEL_KBLRVP3 bool "Kabylake LPDDR3 RVP3" +config BOARD_INTEL_KBLRVP7 + bool "Kabylake DDR3L RVP7" diff --git a/src/mainboard/intel/kblrvp/board_info.txt b/src/mainboard/intel/kblrvp/board_info.txt index 2c48625..a3fb505 100644 --- a/src/mainboard/intel/kblrvp/board_info.txt +++ b/src/mainboard/intel/kblrvp/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Intel -Board name: Kblrvp Kabylake RVP3 LPDDR3 +Board name: Kabylake RVP Reference Board Category: eval ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index bc39a80..2e0292d 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -31,7 +31,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - struct region_device spd_rdev; u8 spd_index = (get_board_id() >> 5) & 0x7; printk(BIOS_INFO, "SPD index %d\n", spd_index); @@ -41,15 +40,22 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - /* RVP3 SPD */ - mem_cfg->DqPinsInterleaved = 0; - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { - die("spd.bin not found\n"); + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + struct region_device spd_rdev; + + mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else { /* for CONFIG_BOARD_INTEL_KBLRVP7 */ + struct spd_block blk; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0]; } - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb new file mode 100644 index 0000000..e79c046 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -0,0 +1,267 @@ +chip soc/intel/skylake + + # SATA port 0 + register "EnableSata" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + + # Enable deep Sx states + register "deep_s5_enable" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "FspSkipMpInit" = "1" + + # Enable Root ports. + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[8]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[2]" = "1" + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + + # RP 9 uses SRCCLKREQ5# + register "PcieRpClkReqNumber[2]" = "5" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkReqNumber[5]" = "4" + register "PcieRpClkReqNumber[8]" = "1" + + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + + # Use default SD card detect GPIO configuration + register "sdcard_cd_gpio_default" = "GPP_G5" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h new file mode 100644 index 0000000..7a8314e --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP7_H +#define _GPIORVP7_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + + +/* GPE_EC_WAKE */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* CHROMEEC in RVP */ +#define EC_SCI_GPI GPP_E16 +#define EC_SMI_GPI GPP_E15 +/* + * Gpio based irq for touchpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define KBLRVP_TOUCHPAD_IRQ 33 + +#define KBLRVP_TOUCH_IRQ 31 + +#define BOARD_TOUCHPAD_NAME "touchpad" +#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ +#define BOARD_TOUCHPAD_I2C_BUS 0 +#define BOARD_TOUCHPAD_I2C_ADDR 0x20 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* PM_SLP_S0ix_R_N*/ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), +/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), +/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* ISH_GP5 */ PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), +/* CORE_VID0 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* CORE_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* HSJ_MIC_DET */ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_GPI_APIC(GPP_B5, NONE, DEEP), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, PLTRST, YES), +/* TBT_CIO_PLUG_EVT */ PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PU, PLTRST, YES), +/* PCH_SLOT1_WAKE_N */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, PLTRST, YES), +/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, DEEP), +/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* USB_CTL */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* ITCH_SPI_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* ITCH_SPI_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_1 */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* ITCH_SPI_MISO_0 */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPI(GPP_D9, NONE, DEEP), +/* SD_D3_WAKE */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), +/* EN_PP3300_DX_CAM */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), +/* EN_PP1800_DX_AUDIO */PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* ITCH_SPI_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* ITCH_SPI_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), +/* PCH_CODEC_IRQ */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* AUDIO_IRQ */ PAD_CFG_NF(GPP_F10, NONE, DEEP, NF2), +/* I2C5_SCL */ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF2), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* WWAN_UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_NF(GPD7, NONE, DEEP, NF1), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + + +#endif + +#endif +

1 0

Patch set updated for coreboot: mb/intel/kblrvp: Add Variant board support for KBLRVP
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17630 -gerrit commit 4c499b37e6466cd11bb5da6b167c64c479cf279b Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Mon Nov 28 14:53:12 2016 +0530 mb/intel/kblrvp: Add Variant board support for KBLRVP Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/Kconfig | 2 +- src/mainboard/intel/kblrvp/Kconfig | 8 + src/mainboard/intel/kblrvp/Makefile.inc | 3 + src/mainboard/intel/kblrvp/acpi/ec.asl | 2 +- src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 +- src/mainboard/intel/kblrvp/bootblock.c | 2 +- src/mainboard/intel/kblrvp/devicetree.cb | 262 --------------------- src/mainboard/intel/kblrvp/gpio.h | 218 ----------------- src/mainboard/intel/kblrvp/mainboard.c | 2 +- src/mainboard/intel/kblrvp/ramstage.c | 2 +- src/mainboard/intel/kblrvp/smihandler.c | 2 +- src/mainboard/intel/kblrvp/spd/spd.h | 3 +- .../intel/kblrvp/variants/rvp3/devicetree.cb | 262 +++++++++++++++++++++ .../kblrvp/variants/rvp3/include/variant/gpio.h | 218 +++++++++++++++++ 14 files changed, 499 insertions(+), 489 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 77d13d1..5cd0254 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -326,7 +326,7 @@ config GENERIC_SPD_BIN config DIMM_MAX int - default 2 + default 4 depends on GENERIC_SPD_BIN help Total number of memory DIMM slots available on motherboard. diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index e53c446..10752e7 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -48,6 +48,10 @@ config MAINBOARD_DIR string default "intel/kblrvp" +config VARIANT_DIR + string + default "rvp3" + config MAINBOARD_PART_NUMBER string default "Kblrvp" @@ -68,4 +72,8 @@ config GBB_HWID string depends on CHROMEOS default "KBLRVP TEST 8819" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" endif diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc index 68c87c9..7ddfb9f 100644 --- a/src/mainboard/intel/kblrvp/Makefile.inc +++ b/src/mainboard/intel/kblrvp/Makefile.inc @@ -32,3 +32,6 @@ ramstage-y += mainboard.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 7d7ff2f..01fa75c 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -15,7 +15,7 @@ /* mainboard configuration */ #include "../ec.h" -#include "../gpio.h" +#include <variant/gpio.h> /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 5d2b307..4764372 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "../gpio.h" +#include <variant/gpio.h> #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c index 627b4e8..dde7e86 100644 --- a/src/mainboard/intel/kblrvp/bootblock.c +++ b/src/mainboard/intel/kblrvp/bootblock.c @@ -15,7 +15,7 @@ #include <bootblock_common.h> #include <soc/gpio.h> -#include "gpio.h" +#include <variant/gpio.h> static void early_config_gpio(void) { diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb deleted file mode 100644 index c2dde4f..0000000 --- a/src/mainboard/intel/kblrvp/devicetree.cb +++ /dev/null @@ -1,262 +0,0 @@ -chip soc/intel/skylake - - # Enable deep Sx states - register "deep_s5_enable" = "0" - register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "gpe0_dw0" = "GPP_C" - register "gpe0_dw1" = "GPP_D" - register "gpe0_dw2" = "GPP_E" - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - - # Enable DPTF - register "dptf_enable" = "1" - - # FSP Configuration - register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "2" - register "InternalGfx" = "1" - register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" - register "SaGv" = "3" - register "PmTimerDisabled" = "1" - - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s - register "PmConfigSlpS3MinAssert" = "0x02" - - # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s - register "PmConfigSlpS4MinAssert" = "0x04" - - # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s - register "PmConfigSlpSusMinAssert" = "0x03" - - # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s - register "PmConfigSlpAMinAssert" = "0x03" - - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" - - # VR Settings Configuration for 5 Domains - #+----------------+-------+-------+-------------+-------------+-------+ - #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | - #+----------------+-------+-------+-------------+-------------+-------+ - #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 5A | 5A | 5A | 5A | 5A | - #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | - #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | - #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | - #| ImonSlope | 0 | 0 | 0 | 0 | 0 | - #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | - #+----------------+-------+-------+-------------+-------------+-------+ - register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x1C, \ - .voltage_limit = 0x5F0 \ - }" - - register "domain_vr_config[VR_IA_CORE]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0 \ - }" - register "domain_vr_config[VR_RING]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x88, \ - .voltage_limit = 0x5F0, \ - }" - - register "domain_vr_config[VR_GT_UNSLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C ,\ - .voltage_limit = 0x5F0 \ - }" - - register "domain_vr_config[VR_GT_SLICED]" = "{ - .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ - .psi3enable = 1, \ - .psi4enable = 1, \ - .imon_slope = 0x0, \ - .imon_offset = 0x0, \ - .icc_max = 0x8C, \ - .voltage_limit = 0x5F0 \ - }" - - register "FspSkipMpInit" = "1" - - # Enable Root ports. - # PCIE Port 1 x4 -> SLOT1 - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "2" - - # PCIE Port 5 x1 -> SLOT2/LAN - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "3" - - # PCIE Port 6 x1 -> SLOT3 - register "PcieRpEnable[5]" = "1" - register "PcieRpClkReqSupport[5]" = "1" - register "PcieRpClkReqNumber[5]" = "1" - - # PCIE Port 7 Disabled - # PCIE Port 8 Disabled - # PCIE Port 9 x1 -> WLAN - register "PcieRpEnable[8]" = "1" - register "PcieRpClkReqSupport[8]" = "1" - register "PcieRpClkReqNumber[8]" = "5" - - # PCIE Port 10 x1 -> WiGig - register "PcieRpEnable[9]" = "1" - register "PcieRpClkReqSupport[9]" = "1" - register "PcieRpClkReqNumber[9]" = "4" - - # USB 2.0 Enable all ports - register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port - register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth - register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port - register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port - register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port - - # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ - }" - - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - - # Enable/Disable VMX feature - register "VmxEnable" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 x1 WLAN - device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h deleted file mode 100644 index c6f4123..0000000 --- a/src/mainboard/intel/kblrvp/gpio.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2016 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ - -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - -#include <soc/gpe.h> -#include <soc/gpio.h> - -/* TCA6424A I/O Expander */ -#define IO_EXPANDER_BUS 4 -#define IO_EXPANDER_0_ADDR 0x22 -#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ -#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ -#define IO_EXPANDER_P1CONF 0x0D -#define IO_EXPANDER_P1DOUT 0x05 -#define IO_EXPANDER_P2CONF 0x0E -#define IO_EXPANDER_P2DOUT 0x06 -#define IO_EXPANDER_1_ADDR 0x23 - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ -#define EC_SCI_GPI GPE0_DW2_16 -#define EC_SMI_GPI GPP_E15 - -#ifndef __ACPI__ -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { -/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), -/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), -/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), -/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), -/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), -/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), -/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), -/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), -/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), -/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), -/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), -/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), -/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), -/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), -/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), -/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), -/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), -/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), -/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), -/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), -/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), -/* GSPI0_CS# */ /* GPP_B15 */ -/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* TBT_CIO */ PAD_CFG_NC(GPP_B17), -/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), -/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), -/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), -/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), -/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), -/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), -/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), -/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), -/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), -/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), -/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), -/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), -/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), -/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), -/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), -/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), -/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), -/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), -/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), -/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), -/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), -/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), -/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), -/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), -/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), -/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), -/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), -/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), -/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), -/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), -/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), -/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), -/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), -/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), -/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), -/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), -/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), -/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), -/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), -/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), -/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), -/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), -/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), -/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), -/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), -/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), -/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), -/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), -/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), -/* SATA_DEVSLP2 */ /* GPP_E6 */ -/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), -/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), -/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), -/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), -/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), -/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), -/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), -/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), -/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), -/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), -/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), -/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), -/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), -/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), -/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), -/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), -/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), -/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), -/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), -/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), -/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), -/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), -/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), -/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), -/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), -/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), -/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), -/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), -/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), -/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), -/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), -/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), -/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), -/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), -/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), -/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), -/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), -/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), -/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), -/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), -/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), -/* GPD7 */ PAD_CFG_NC(GPD7), -/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), -/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), -/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -}; - -#endif - -#endif diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index cd6c3f9..652af73 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -24,7 +24,7 @@ #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> #include "ec.h" -#include "gpio.h" +#include <variant/gpio.h> static void mainboard_init(device_t dev) { diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index bcd72bc..3a48396 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/i2c.h> #include <soc/ramstage.h> -#include "gpio.h" +#include <variant/gpio.h> void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 81aaf23..9ecc43a 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -25,7 +25,7 @@ #include <soc/pm.h> #include <soc/smm.h> #include "ec.h" -#include "gpio.h" +#include <variant/gpio.h> int mainboard_io_trap_handler(int smif) { diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index 3ef2dd8..c24baa0 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -18,8 +18,7 @@ #define MAINBOARD_SPD_H #include <gpio.h> -#include "../gpio.h" - +#include <variant/gpio.h> #define RCOMP_TARGET_PARAMS 0x5 diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb new file mode 100644 index 0000000..c2dde4f --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -0,0 +1,262 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "2" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmTimerDisabled" = "1" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 5A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + register "domain_vr_config[VR_RING]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0, \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + register "FspSkipMpInit" = "1" + + # Enable Root ports. + # PCIE Port 1 x4 -> SLOT1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "2" + + # PCIE Port 5 x1 -> SLOT2/LAN + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + + # PCIE Port 6 x1 -> SLOT3 + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "1" + + # PCIE Port 7 Disabled + # PCIE Port 8 Disabled + # PCIE Port 9 x1 -> WLAN + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + + # PCIE Port 10 x1 -> WiGig + register "PcieRpEnable[9]" = "1" + register "PcieRpClkReqSupport[9]" = "1" + register "PcieRpClkReqNumber[9]" = "4" + + # USB 2.0 Enable all ports + register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port + register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth + register "usb2_ports[4]" = "USB2_PORT_MAX(OC_SKIP)" # Type-A Port + register "usb2_ports[5]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[7]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[9]" = "USB2_PORT_MAX(OC1)" # TYPE-A Port + register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port + + # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disabled + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disabled + + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 off end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 x1 WLAN + device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 on end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 on end # SDCard + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h new file mode 100644 index 0000000..c6f4123 --- /dev/null +++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* EC_HID_INT */ PAD_CFG_NC(GPP_A11), +/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), +/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), +/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), +/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* GSPI0_CS# */ /* GPP_B15 */ +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), +/* TBT_CIO */ PAD_CFG_NC(GPP_B17), +/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), +/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), +/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), +/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), +/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ /* GPP_E6 */ +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), +/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), +/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* GPD7 */ PAD_CFG_NC(GPD7), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +#endif + +#endif

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Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435 -gerrit commit 5e3396f31aed694953da08e2e9fcd293021ab799 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 15 19:35:33 2016 +0530 mb/intel/kblrvp: Use common lib spd_bin to get spd Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/romstage.c | 21 +++++-- src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 ----- src/mainboard/intel/kblrvp/spd/spd.c | 94 ----------------------------- src/mainboard/intel/kblrvp/spd/spd.h | 18 +----- src/mainboard/intel/kblrvp/spd/spd_util.c | 34 ----------- 6 files changed, 19 insertions(+), 163 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 446266d..e53c446 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index d4fd113..bc39a80 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -23,20 +23,33 @@ #include <soc/gpio.h> #include "spd/spd.h" #include <string.h> +#include <spd_bin.h> +#include "board_id.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; + struct region_device spd_rdev; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + /* RVP3 SPD */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { + die("spd.bin not found\n"); + } + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 83f4831..0c864fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100 SPD_SOURCES += empty # 5b101 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB SPD_SOURCES += empty # 7b111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c deleted file mode 100644 index 1abee81..0000000 --- a/src/mainboard/intel/kblrvp/spd/spd.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - case SPD_DRAM_LPDDR3_INTEL: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index a9f8645..3ef2dd8 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -15,25 +15,11 @@ */ #ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #include <gpio.h> #include "../gpio.h" -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0B -#define SPD_DRAM_LPDDR3 0x0F -#define SPD_DRAM_LPDDR3_INTEL 0xF1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #define RCOMP_TARGET_PARAMS 0x5 @@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -uintptr_t mainboard_get_spd_data(void); -int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9ffc8ee..181af9f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - int spd_index, spd_span; - size_t spd_file_len; - - spd_index = (get_board_id() >> 5) & 0xF; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - spd_span = spd_index * SPD_LEN; - return (uintptr_t)(spd_file + spd_span); -} - -int mainboard_has_dual_channel_mem(void) -{ - return 1; -}

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Patch set updated for coreboot: lib: Add library to handle SPD data in CBFS or DIMM
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17434 -gerrit commit c3b641a4d2640ca06994b78fb4e4ed824bdff173 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Oct 26 19:43:14 2016 +0530 lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/Kconfig | 25 ++++++++ src/include/spd_bin.h | 57 +++++++++++++++++ src/lib/Makefile.inc | 18 ++++++ src/lib/spd_bin.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 268 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 610be56..77d13d1 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. +config GENERIC_SPD_BIN + bool + default n + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 2 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + config BOARD_ID_AUTO bool default n diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h new file mode 100644 index 0000000..a0c1bbd --- /dev/null +++ b/src/include/spd_bin.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_BIN_H +#define SPD_BIN_H + +#include <arch/early_variables.h> +#include <stdint.h> +#include <commonlib/region.h> + +#define SPD_PAGE_LEN 256 +#define SPD_PAGE_LEN_DDR4 512 +#define SPD_PAGE_0 (0x6C >> 1) +#define SPD_PAGE_1 (0x6E >> 1) +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0B +#define SPD_DRAM_LPDDR3_INTEL 0xF1 +#define SPD_DRAM_LPDDR3_JEDEC 0x0F +#define SPD_DRAM_DDR4 0x0C +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_SPD_PART_OFF 128 +#define DDR3_SPD_PART_LEN 18 +#define LPDDR3_SPD_PART_OFF 128 +#define LPDDR3_SPD_PART_LEN 18 +#define DDR4_SPD_PART_OFF 329 +#define DDR4_SPD_PART_LEN 20 +#define LPDDR4_SPD_PART_OFF 329 +#define LPDDR4_SPD_PART_LEN 20 + +struct spd_block { + u8 *spd_array[CONFIG_DIMM_MAX]; + /* Length of each dimm */ + u16 len; +}; + +void print_spd_info(uint8_t spd[]); +/* Return 0 on success & -1 on failure */ +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); +void dump_spd_info(struct spd_block *blk); +void get_spd_smbus(struct spd_block *blk); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ddade2b..0480eec 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -279,3 +279,21 @@ subdirs-y += ../../3rdparty/libhwbase ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE + +romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c + +LIB_SPD_BIN = $(obj)/spd.bin + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(LIB_SPD_BIN): $(LIB_SPD_DEPS) + for f in $(LIB_SPD_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +spd.bin-file := $(LIB_SPD_BIN) +spd.bin-type := spd diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c new file mode 100644 index 0000000..343d48a --- /dev/null +++ b/src/lib/spd_bin.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <spd_bin.h> +#include <string.h> +#include <device/early_smbus.h> + +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; + +void dump_spd_info(struct spd_block *blk) +{ + u8 i; + + for (i = 0; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { + printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); + print_spd_info(blk->spd_array[i]); + } +} + +void print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; + const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + printk(BIOS_INFO, "LPDDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], + LPDDR3_SPD_PART_LEN); + spd_name[LPDDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_DDR4: + printk(BIOS_INFO, "DDR4\n"); + memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); + spd_name[DDR4_SPD_PART_LEN] = 0; + ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + devw = spd_devw[spd[12] & 7]; + busw = spd_busw[spd[13] & 7]; + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void update_spd_len(struct spd_block *blk) +{ + u8 i, j = 0; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL) + j |= blk->spd_array[i][SPD_DRAM_TYPE]; + + /* If spd used is DDR4, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; +} + +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) +{ + struct cbfsf fh; + + uint32_t cbfs_type = CBFS_TYPE_SPD; + + cbfs_boot_locate(&fh, "spd.bin", &cbfs_type); + cbfs_file_data(spd_rdev, &fh); + return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, + CONFIG_DIMM_SPD_SIZE); +} + +static void get_spd(u8 *spd, u8 addr) +{ + u16 i; + /* Assuming addr is 8 bit address, make it 7 bit */ + addr = addr >> 1; + if (smbus_read_byte(0, addr, 0) == 0xff) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", + addr << 1); + /* Make sure spd is zeroed if dimm doesn't exist. */ + memset(spd, 0, CONFIG_DIMM_SPD_SIZE); + return; + } + + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i] = smbus_read_byte(0, addr, i); + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) { + /* Switch to page 1 */ + smbus_write_byte(0, SPD_PAGE_1, 0, 0); + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i); + /* Restore to page 0 */ + smbus_write_byte(0, SPD_PAGE_0, 0, 0); + } +} + +void get_spd_smbus(struct spd_block *blk) +{ + u8 i, j; + unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); + + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, + 0xA0 + (i << 1)); + blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + } + + for (j = i; j < CONFIG_DIMM_MAX; j++) + blk->spd_array[j] = NULL; + + update_spd_len(blk); +}

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Patch set updated for coreboot: mainboard/intel/kblrvp: Revert back USB OC pin programming
by Barnali Sarkar 30 Nov '16

30 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17635 -gerrit commit 1ab583d3b96489c52320efc2cbad2894ca013278 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 12:05:28 2016 +0530 mainboard/intel/kblrvp: Revert back USB OC pin programming With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/mainboard/intel/kblrvp/ramstage.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index d33c967..bcd72bc 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -21,21 +21,10 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - size_t i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Set proper OC for various USB ports*/ - u8 usb2_oc[] = {0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; - u8 usb3_oc[] = {0x0, 0x8, 0x8, 0x1, 0x8, 0x8}; - - for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) - params->Usb2OverCurrentPin[i] = usb2_oc[i]; - - for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) - params->Usb3OverCurrentPin[i] = usb3_oc[i]; } static void ioexpander_init(void *unused)

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New patch to review for coreboot: google/pyro: set i2c bus timings by rise/fall times
by Kevin Chiu 30 Nov '16

30 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17652 -gerrit commit f3b61eaf051bb90f7ade35ae2d94b023fa3d4bc7 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Nov 30 16:30:28 2016 +0800 google/pyro: set i2c bus timings by rise/fall times Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- .../google/reef/variants/pyro/devicetree.cb | 41 +++++++--------------- 1 file changed, 12 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index d5745b4..3520add 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -71,50 +71,33 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" - # Limit I2C0 Audio codec da7219 speed to 400kHz with manually tuned values. + # Enable I2C0 for audio codec at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 104, + .fall_time_ns = 52, }" - # Enable I2C2 bus early for TPM access and configure as 400kHz - # with manually tuned values. + # Enable I2C2 bus early for TPM at 400kHz register "i2c[2]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 57, + .fall_time_ns = 28, }" - # Limit I2C3 WACOM touchscreen speed to 400kHz with manually tuned values. + # touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 76, + .fall_time_ns = 164, }" - # Limit trackpad speed to 400kHz with manually tuned values. + # trackpad at 400kHz register "i2c[4]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 90, + .fall_time_ns = 164, }" # Minimum SLP S3 assertion width 28ms.

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coreboot-gerrit November 2016