coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/skylake: Disable Legacy PME for Root ports
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit eedf6d8aa81e85b52d3c150dc992cbfb3077988d Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Nov 16 21:27:38 2016 +0530 soc/intel/skylake: Disable Legacy PME for Root ports Legacy PME are enabled by default in FSP UPD region. When Legacy PME is enabled, then an SCI is generated and should be handled by OS and BIOS/Coreboot in collboration. OS requires some ACPI methods (eg _L69) which help to determine the wake source and also to clear some registers. But this infrastructure is not present as of now in coreboot and also linux handles PMEs natively. Hence the SCI was never handled by OS and the status bits were never cleared i.e., PCI_EXP_STS. For this reason the level triggered SCI will remain active and the system will wake up as soon as it enters S3. To fix this, diabled Legacy PME (PmSci for Root ports). Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17553 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17553 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/snappy: Tune i2c frequency to 400 Khz
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 1612cef81f20cb955d591f3cebcf864d784856ac Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sun Nov 27 16:56:30 2016 +0800 mainboard/google/snappy: Tune i2c frequency to 400 Khz tune i2c devices clk for snappy: I2C0: audio I2C2: TPM H1 I2C3: elan touchscreen I2C4: elan touchpad I2C5: wacom digitizer BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.7kHz Rise Time 58.8ns Fall time 12.11ns TPM H1: Freq. 398.8kHz Rise Time 31.71ns Fall time 13.28ns elan touchscreen: Freq. 390.5kHz Rise Time 235.7ns Fall time 37.64ns elan touchpad: Freq. 393.7kHz Rise Time 288.8ns Fall time 51.67ns wacom digitizer: Freq. 388.8kHz Rise Time 124.1ns Fall time 21.10ns Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/17634 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17634 for details. -gerrit

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Patch set updated for coreboot: sb/intel/lynxpoint: add missing I2C ACPI SSCN/FMCN methods
by Matt DeVillier 30 Nov '16

30 Nov '16

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17620 -gerrit commit fedf45a74fa34b8dda7243ebc92426e30497e1d7 Author: Prabal Saha <coolstarorganization(a)gmail.com> Date: Thu Jul 14 12:34:33 2016 -0700 sb/intel/lynxpoint: add missing I2C ACPI SSCN/FMCN methods The SSCN and FMCN methods provide the optimal HCNT/LCNT timing values to the driver, and are necessary when using I2C devices (eg, trackpad and touchscreen) in ACPI (vs PCI) mode. Add these methods using the timing values from Broadwell, which work for Haswell/Lynxpoint as well. TEST: build google/peppy with trackpad/touchscreen devices in ACPI mode, observe proper operation under Windows [8.1/10] and Linux [Mint 18] Change-Id: I25f07ac474b041358315530e5f391bb33d9c4d04 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 930a8ee..e8e81c3 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -165,6 +165,9 @@ Device (I2C0) Name (_UID, 1) Name (_ADR, 0x00150001) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () { @@ -244,6 +247,9 @@ Device (I2C1) Name (_UID, 1) Name (_ADR, 0x00150002) + Name (SSCN, Package () { 432, 507, 30 }) + Name (FMCN, Package () { 72, 160, 30 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () {

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Patch merged into coreboot/master: soc/intel/apollolake: Add save/restore variable MRC cache
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 96e9ff168ca52f3bb06606b65fb07ba5e4e7bb50 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 16:18:30 2016 -0700 soc/intel/apollolake: Add save/restore variable MRC cache Apollolake MRC cache is divided into two regions: constant and variable. Currently they are clubbed together. Since variable data changes across cold reboot it triggers invalidation of the whole cache region. This change declubs the data, adds routines to load/store variable data on flash. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I374519777abe9b9a1e6cceae5318decd405bb527 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/17237 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17237 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/common: Add save/restore for variable MRC data
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit ef9a9ea3b7585354d447ab0b3145e1b357226647 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Nov 8 08:30:06 2016 -0800 soc/intel/common: Add save/restore for variable MRC data Piggy-back on existing MRC cache infrastructure to store variable MRC data. Only one set of data can be valid at given point of time. Currently this magically happens because region alignment is forced to 0x1000 and region itself is of the same size. This needs to be somehow programmatically enforced. Change-Id: I8a660d356ca760b8ff9907396fb9b34cb16cf1db Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/17320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17320 for details. -gerrit

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Patch merged into coreboot/master: mainboard/reef: Add RW_VAR_MRC_CACHE
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 4ed99ad067a7bd9f5ef6004c7b0e5f9f7edbe0d5 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 4 16:17:11 2016 -0700 mainboard/reef: Add RW_VAR_MRC_CACHE Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/17235 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17235 for details. -gerrit

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Patch merged into coreboot/master: driver/intel/fsp2_0: Add version parameter to FSP platform callback
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit f796c6e0ec6769873d63b6fcfc64c0ac14ba3555 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 18 14:57:51 2016 -0800 driver/intel/fsp2_0: Add version parameter to FSP platform callback Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17497 for details. -gerrit

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Patch merged into coreboot/master: vendorcode/intel: Update apollolake UPD headers to SIC 1.2.3 release
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 51c67601f16899cac0b860b80b76ee674e135faa Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Mon Nov 28 10:47:09 2016 -0800 vendorcode/intel: Update apollolake UPD headers to SIC 1.2.3 release This header update contains updates for skipping punit as well as some MRC related UPD values. BUG=chrome-os-partner:60068 BRANCH=none TEST=built with FSP 1.2.3 and MRC patches for coreboot CQ-DEPEND=CL:*307357 Change-Id: I8c66c0c0febba5e67ae3290034e9b095c9e68f07 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://review.coreboot.org/17631 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17631 for details. -gerrit

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Patch set updated for coreboot: soc/intel/skylake: Pass proper CPU flex ratio override to FSP
by Naresh Solanki 30 Nov '16

30 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17555 -gerrit commit 627885b0ced9d1379f12d19c81dc95b4288e2417 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Nov 16 21:34:41 2016 +0530 soc/intel/skylake: Pass proper CPU flex ratio override to FSP In bootblock, cpu flex ratio is set to non-turbo max. In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu ratio to zero. Since it is different than the non-zero value programmed in bootblock, FSP gives reset. To avoid the reset, set FSP UPD for CPU flex ratio override to that value as set in bootblock. Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/soc/intel/skylake/romstage/romstage_fsp20.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8e08323..662c4c5 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -19,12 +19,14 @@ #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> #include <cbmem.h> #include <chip.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/util.h> #include <fsp/memmap.h> +#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> @@ -94,6 +96,18 @@ asmlinkage void *car_stage_c_entry(void) return postcar_commit_mtrrs(&pcf); } +static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +{ + msr_t flex_ratio; + m_cfg->CpuRatioOverride = 1; + /* + * Set cpuratio to that value set in bootblock, This will ensure FSPM + * knows the intended flex ratio. + */ + flex_ratio = rdmsr(MSR_FLEX_RATIO); + m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) { const struct device *dev; @@ -130,6 +144,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg) mask |= (1<<i); } m_cfg->PcieRpEnableMask = mask; + + cpu_flex_override(m_cfg); } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd)

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Patch set updated for coreboot: mainboard/google/reef: allow variants to modify nhlt oem revision
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17651 -gerrit commit 7c810cf95d687f656ed151767f2e3a16d96c23c5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:20:07 2016 -0600 mainboard/google/reef: allow variants to modify nhlt oem revision In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 7 ++++--- .../google/reef/variants/baseboard/include/baseboard/variants.h | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 44858d4..4425c01 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -41,8 +41,9 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -void __attribute__((weak)) variant_nhlt_oem_strings(const char **oem_id, - const char **oem_table_id) +void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, + uint32_t *oem_revision) { } @@ -64,7 +65,7 @@ static unsigned long mainboard_write_acpi_tables( return start_addr; variant_nhlt_init(nhlt); - variant_nhlt_oem_strings(&oem_id, &oem_table_id); + variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, oem_id, oem_table_id, oem_revision); diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 31ee3d0..65a32b3 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -42,8 +42,8 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); /* Seed the NHLT tables with the board specific information. */ struct nhlt; -void variant_nhlt_oem_strings(const char **oem_id, - const char **oem_table_id); +void variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, uint32_t *oem_revision); void variant_nhlt_init(struct nhlt *nhlt); #endif /* BASEBOARD_VARIANTS_H */

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coreboot-gerrit November 2016