coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch merged into coreboot/master: mainboard/intel/kblrvp: Revert back USB OC pin programming
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 500ba45b2c18a2742188d603808e2812fe6ed437 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 12:05:28 2016 +0530 mainboard/intel/kblrvp: Revert back USB OC pin programming With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Reviewed-on: https://review.coreboot.org/17635 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17635 for details. -gerrit

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Patch set updated for coreboot: mainboard/google/reef: allow variants to modify nhlt oem revision
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17651 -gerrit commit fd75adb561b95efdfe852e17f9eb25a2a9e0fe3e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:20:07 2016 -0600 mainboard/google/reef: allow variants to modify nhlt oem revision In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/reef/mainboard.c | 7 ++++--- .../google/reef/variants/baseboard/include/baseboard/variants.h | 4 ++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 44858d4..4425c01 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -41,8 +41,9 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } -void __attribute__((weak)) variant_nhlt_oem_strings(const char **oem_id, - const char **oem_table_id) +void __attribute__((weak)) variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, + uint32_t *oem_revision) { } @@ -64,7 +65,7 @@ static unsigned long mainboard_write_acpi_tables( return start_addr; variant_nhlt_init(nhlt); - variant_nhlt_oem_strings(&oem_id, &oem_table_id); + variant_nhlt_oem_overrides(&oem_id, &oem_table_id, &oem_revision); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, oem_id, oem_table_id, oem_revision); diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h index 31ee3d0..65a32b3 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/variants.h @@ -42,8 +42,8 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); /* Seed the NHLT tables with the board specific information. */ struct nhlt; -void variant_nhlt_oem_strings(const char **oem_id, - const char **oem_table_id); +void variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, uint32_t *oem_revision); void variant_nhlt_init(struct nhlt *nhlt); #endif /* BASEBOARD_VARIANTS_H */

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Patch set updated for coreboot: lib/nhlt: add support for setting the oem_revision
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17650 -gerrit commit 43277c43cb3450b500c537e2c01cc4599e92d063 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:14:25 2016 -0600 lib/nhlt: add support for setting the oem_revision In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/nhlt.h | 6 ++++-- src/lib/nhlt.c | 6 ++++-- src/mainboard/google/reef/mainboard.c | 3 ++- src/mainboard/intel/kunimitsu/mainboard.c | 2 +- src/soc/intel/common/nhlt.c | 7 ++++--- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 17b7d11..5b72320 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -162,7 +162,8 @@ uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr); * valid after thisfunction is called. */ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + uint32_t oem_revision); /* * While very similar to nhlt_serialize() the SoC specific function allows @@ -177,7 +178,8 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr); * as updating ACPI field references for the serialized structure. */ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id); + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision); /* Link and device types. */ enum { diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 7bf8ce8..da94415 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -390,11 +390,12 @@ static void nhlt_serialize_endpoints(struct nhlt *nhlt, struct cursor *cur) uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { - return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0); } uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) { struct cursor cur; acpi_header_t *header; @@ -424,6 +425,7 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, memcpy(header->oem_id, oem_id, oem_id_len); memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); + write_le32(&header->oem_revision, oem_revision); memcpy(header->asl_compiler_id, ASLC, 4); cur.buf = (void *)(acpi_addr + sizeof(acpi_header_t)); diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 4d4ef53..44858d4 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -54,6 +54,7 @@ static unsigned long mainboard_write_acpi_tables( struct nhlt *nhlt; const char *oem_id = NULL; const char *oem_table_id = NULL; + uint32_t oem_revision = 0; start_addr = current; @@ -66,7 +67,7 @@ static unsigned long mainboard_write_acpi_tables( variant_nhlt_oem_strings(&oem_id, &oem_table_id); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, oem_revision); if (end_addr != start_addr) acpi_add_table(rsdp, (void *)start_addr); diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 9f79db6..cbadc2e 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -84,7 +84,7 @@ static unsigned long mainboard_write_acpi_tables( printk(BIOS_ERR, "Couldn't add headset codec.\n"); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, 0); if (end_addr != start_addr) acpi_add_table(rsdp, (void *)start_addr); diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index 03a4b4f..a268ea6 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -19,11 +19,12 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { - return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0); } uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) { global_nvs_t *gnvs; @@ -37,5 +38,5 @@ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, gnvs->nhll = nhlt_current_size(nhlt); return nhlt_serialize_oem_overrides(nhlt, acpi_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, oem_revision); }

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Patch set updated for coreboot: arch/x86: cache postcar in stage cache
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17649 -gerrit commit a09815e37132616d7e9498317335ec924f055dc8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 15:52:08 2016 -0600 arch/x86: cache postcar in stage cache Stash and reload postcar stage in the stage cache for increased S3 resume speed. It's impact is small (2 ms or so), but there's no need to go to the boot media on resume to reload something that was already loaded. This aligns with the same paths we take on ramstage as well. Change-Id: I4313794826120853163c7366e81346858747ed0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 28 +++++++++++++++++++++------- src/include/stage_cache.h | 1 + 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d9719ff..948e445 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -20,6 +20,8 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <rmodule.h> +#include <romstage_handoff.h> +#include <stage_cache.h> static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { @@ -110,18 +112,14 @@ void *postcar_commit_mtrrs(struct postcar_frame *pcf) return (void *) pcf->stack; } -void run_postcar_phase(struct postcar_frame *pcf) +static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) { - struct prog prog = - PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); struct rmod_stage_load rsl = { .cbmem_id = CBMEM_ID_AFTER_CAR, - .prog = &prog, + .prog = prog, }; - postcar_commit_mtrrs(pcf); - - if (prog_locate(&prog)) + if (prog_locate(prog)) die("Failed to locate after CAR program.\n"); if (rmodule_stage_load(&rsl)) die("Failed to load after CAR program.\n"); @@ -139,5 +137,21 @@ void run_postcar_phase(struct postcar_frame *pcf) prog_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), SEG_FINAL); + if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + stage_cache_add(STAGE_POSTCAR, prog); +} + +void run_postcar_phase(struct postcar_frame *pcf) +{ + struct prog prog = + PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + + postcar_commit_mtrrs(pcf); + + if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && romstage_handoff_is_resume()) + stage_cache_load_stage(STAGE_POSTCAR, &prog); + else + load_postcar_cbfs(&prog, pcf); + prog_run(&prog); } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index a24ea71..fbf9c46 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -23,6 +23,7 @@ enum { STAGE_RAMSTAGE, STAGE_REFCODE, + STAGE_POSTCAR, }; /* Cache the loaded stage provided according to the parameters. */

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Patch set updated for coreboot: lib: put romstage_handoff implementation in own compilation unit
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17648 -gerrit commit 3ccc037a50a41949a9dde6d2fca5bf4fd280f65c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:37:42 2016 -0600 lib: put romstage_handoff implementation in own compilation unit Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage.c | 1 + src/include/romstage_handoff.h | 74 +------------------- src/lib/Makefile.inc | 3 + src/lib/romstage_handoff.c | 80 ++++++++++++++++++++++ src/mainboard/google/gru/romstage.c | 2 + src/soc/intel/baytrail/romstage/romstage.c | 1 + src/soc/intel/braswell/romstage/romstage.c | 1 + src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 1 + 8 files changed, 91 insertions(+), 72 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index b222082..bb3e96c 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -34,6 +34,7 @@ #include <smbios.h> #include <soc/intel/common/mrc_cache.h> #include <stage_cache.h> +#include <string.h> #include <timestamp.h> #include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 9e254cd..1a6bbf7 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -15,80 +15,10 @@ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H -#include <stdint.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <rules.h> - -/* It is the chipset's responsibility for maintaining the integrity of this - * structure in CBMEM. For instance, if chipset code adds this structure - * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber - * fields it doesn't own. */ -struct romstage_handoff { - /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is - * responsible for initializing this variable. Otherwise, ramstage - * will be re-loaded from cbfs (which can be slower since it lives - * in flash). */ - uint8_t s3_resume; - uint8_t reboot_required; - uint8_t reserved[2]; -}; - -/* The romstage_handoff_find_or_add() function provides the necessary logic - * for initializing the romstage_handoff structure in cbmem. Different components - * of the romstage may be responsible for setting up different fields. Therefore - * that same logic flow should be used for allocating and initializing the - * structure. A newly allocated structure will be memset to 0. */ -static inline struct romstage_handoff *romstage_handoff_find_or_add(void) -{ - struct romstage_handoff *handoff; - - /* cbmem_add() first does a find and uses the old location before the - * real add. However, it is important to know when the structure is not - * found so it can be initialized to 0. */ - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff) - return handoff; - - handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); - - if (handoff != NULL) - memset(handoff, 0, sizeof(*handoff)); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return handoff; -} - /* Returns 0 if initialized. Else < 0 if handoff structure not added. */ -static inline int romstage_handoff_init(int is_s3_resume) -{ - struct romstage_handoff *handoff; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) - return -1; - - handoff->s3_resume = is_s3_resume; - - return 0; -} +int romstage_handoff_init(int is_s3_resume); /* Return 1 if resuming or 0 if not. */ -static inline int romstage_handoff_is_resume(void) -{ - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) - return 0; - - return handoff->s3_resume; -} +int romstage_handoff_is_resume(void); #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ddade2b..4157091 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -87,6 +87,8 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +ramstage-y += romstage_handoff.c +romstage-y += romstage_handoff.c romstage-y += romstage_stack.c ramstage-y += romstage_stack.c romstage-y += stack.c @@ -153,6 +155,7 @@ postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c postcar-y += imd_cbmem.c postcar-y += imd.c +postcar-y += romstage_handoff.c bootblock-y += hexdump.c ramstage-y += hexdump.c diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c new file mode 100644 index 0000000..bdfdb64 --- /dev/null +++ b/src/lib/romstage_handoff.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <romstage_handoff.h> +#include <rules.h> + +struct romstage_handoff { + /* Indicate if the current boot is an S3 resume. If + * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * responsible for initializing this variable. Otherwise, ramstage + * will be re-loaded from cbfs (which can be slower since it lives + * in flash). */ + uint8_t s3_resume; + uint8_t reboot_required; + uint8_t reserved[2]; +}; + +static struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + struct romstage_handoff *handoff; + + /* cbmem_add() first does a find and uses the old location before the + * real add. However, it is important to know when the structure is not + * found so it can be initialized to 0. */ + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff) + return handoff; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + + if (handoff != NULL) + memset(handoff, 0, sizeof(*handoff)); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + return handoff; +} + +int romstage_handoff_init(int is_s3_resume) +{ + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + if (handoff == NULL) + return -1; + + handoff->s3_resume = is_s3_resume; + + return 0; +} + +int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +} diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 1e2507a..55ed79a 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -19,6 +19,7 @@ #include <arch/exception.h> #include <arch/mmu.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -28,6 +29,7 @@ #include <soc/sdram.h> #include <symbols.h> #include <soc/usb.h> +#include <stdlib.h> #include "pwm_regulator.h" diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 124eb6e..d457151 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -28,6 +28,7 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> +#include <string.h> #include <timestamp.h> #include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 95880e8..0125847 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <elog.h> #include <romstage_handoff.h> +#include <string.h> #include <timestamp.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 49bdedb..49d9a94 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -19,6 +19,7 @@ #include <lib.h> #include <arch/io.h> #include <arch/cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <program_loading.h>

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Patch set updated for coreboot: romstage_handoff: add helper to determine resume status
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17647 -gerrit commit f0830a0a9581fef60273c32eac27c0fb253a7044 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:22:42 2016 -0600 romstage_handoff: add helper to determine resume status Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/acpi_s3.c | 9 +-------- src/include/romstage_handoff.h | 13 +++++++++++++ src/lib/prog_loaders.c | 25 ++++++++++++------------- src/soc/intel/apollolake/chip.c | 4 +--- src/soc/intel/quark/chip.c | 5 +---- src/soc/intel/skylake/chip_fsp20.c | 7 +------ 6 files changed, 29 insertions(+), 34 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ffec64d..f3cb097 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -32,14 +32,7 @@ int acpi_slp_type = -1; #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) int acpi_get_sleep_type(void) { - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - return ACPI_S0; - } else if (handoff->s3_resume) { + if (romstage_handoff_is_resume()) { printk(BIOS_DEBUG, "S3 Resume.\n"); return ACPI_S3; } else { diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 3eba0fd..9e254cd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -78,4 +78,17 @@ static inline int romstage_handoff_init(int is_s3_resume) return 0; } +/* Return 1 if resuming or 0 if not. */ +static inline int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +} + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3a6f2e2..58c1a8a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -85,19 +85,19 @@ static void ramstage_cache_invalid(void) } } -static void run_ramstage_from_resume(struct romstage_handoff *handoff, - struct prog *ramstage) +static void run_ramstage_from_resume(struct prog *ramstage) { - if (handoff != NULL && handoff->s3_resume) { - /* Load the cached ramstage to runtime location. */ - stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); - - if (prog_entry(ramstage) != NULL) { - printk(BIOS_DEBUG, "Jumping to image.\n"); - prog_run(ramstage); - } - ramstage_cache_invalid(); + if (!romstage_handoff_is_resume()) + return; + + /* Load the cached ramstage to runtime location. */ + stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); + + if (prog_entry(ramstage) != NULL) { + printk(BIOS_DEBUG, "Jumping to image.\n"); + prog_run(ramstage); } + ramstage_cache_invalid(); } static int load_relocatable_ramstage(struct prog *ramstage) @@ -136,8 +136,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_NO_STAGE_CACHE) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - run_ramstage_from_resume(romstage_handoff_find_or_add(), - &ramstage); + run_ramstage_from_resume(&ramstage); if (prog_locate(&ramstage)) goto fail; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ef5908c..32d68cc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -260,7 +260,6 @@ static void set_power_limits(void) static void soc_init(void *data) { struct global_nvs_t *gnvs; - struct romstage_handoff *handoff; /* Save VBT info and mapping */ vbt = vbt_get(&vbt_rdev); @@ -269,8 +268,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 150df12..5e80463 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -102,8 +102,6 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { - struct romstage_handoff *handoff; - /* Validate the temperature settings */ ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS @@ -120,8 +118,7 @@ static void chip_init(void *chip_info) | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); /* Perform silicon specific init. */ - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f90f6bc..0768779 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -35,13 +35,8 @@ void soc_init_pre_device(void *chip_info) { - struct romstage_handoff *handoff; - - /* Get S3 status to pass to silicon init. */ - handoff = romstage_handoff_find_or_add(); - /* Perform silicon specific init. */ - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev)

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Patch merged into coreboot/master: soc/intel/skylake: Fix top_of_ram calculation
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 721d1b30907d379b1d1cb095f4157229fcedd433 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Nov 16 21:32:04 2016 +0530 soc/intel/skylake: Fix top_of_ram calculation FSP 2.0 implementation conditionally sets PMRR base based on EnableC6Dram UPD. Therefore, handle the case of the PMRR base not being set since FSP 2.0 changed behavior from FSP 1.1 implementation. If prmrr base is non-zero value, then top_of_ram is prmrr base. If Probeless trace is enabled, then deduct trace memory size from calculated top_of_ram. Change-Id: I2633bf78705e36b241668a313d215d0455fba607 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17554 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 6467014046811d86a86e4f143476787a4c35a8cc Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Nov 23 15:25:19 2016 +0530 soc/intel/skylake: Use SendVrMbxCmd1 for FSP 2.0 In FSP 2.0 the UPD to send extra VR Mailbox commands is switched from SendVrMbxCmd to SendVrMbxCmd1. Use the same in silicon initialization. Change-Id: I46bd50c9acc0456e2483f20ccb5e9ec2a0de232a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/17578 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17578 for details. -gerrit

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Patch merged into coreboot/master: soc/skylake: Move IO decode range out from pch_lpc_init
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 544dac692a3a9a22187316a139e1326c76ce7a6f Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Date: Thu Nov 10 01:21:23 2016 +0800 soc/skylake: Move IO decode range out from pch_lpc_init 1. Move existing IO decode range from pch_lpc_init to early stage before SIO init. 2. At the same time, enable SIO decode range (0x2e/0x2f) for platform which use super IO. Change-Id: I72df16d0a784686d8cadfbee09b5aef60576ac43 Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Reviewed-on: https://review.coreboot.org/17337 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17337 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Remove pad configuration size hardcoding
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 0068dfdcc8c2a80508cdd44909d9a2561a30a0e5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Nov 23 00:54:47 2016 +0530 soc/intel/skylake: Remove pad configuration size hardcoding Existing GPIO driver inside coreboot use some hardcoded magic number to calculate gpio pad offset. Avoid this kind of hardcoding. Change-Id: I6110435574b141c57f366ccb1fbe9bf49d4dd70a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/17571 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17571 for details. -gerrit

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coreboot-gerrit November 2016