coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: lib/nhlt: add support for setting the oem_revision
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17650 -gerrit commit 076238973c686d162fef809a53ad1fe68f0b64a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:14:25 2016 -0600 lib/nhlt: add support for setting the oem_revision In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/nhlt.h | 6 ++++-- src/lib/nhlt.c | 6 ++++-- src/mainboard/google/reef/mainboard.c | 3 ++- src/mainboard/intel/kunimitsu/mainboard.c | 2 +- src/soc/intel/common/nhlt.c | 7 ++++--- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/src/include/nhlt.h b/src/include/nhlt.h index 17b7d11..5b72320 100644 --- a/src/include/nhlt.h +++ b/src/include/nhlt.h @@ -162,7 +162,8 @@ uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr); * valid after thisfunction is called. */ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, uintptr_t acpi_addr, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, + uint32_t oem_revision); /* * While very similar to nhlt_serialize() the SoC specific function allows @@ -177,7 +178,8 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr); * as updating ACPI field references for the serialized structure. */ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id); + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision); /* Link and device types. */ enum { diff --git a/src/lib/nhlt.c b/src/lib/nhlt.c index 7bf8ce8..da94415 100644 --- a/src/lib/nhlt.c +++ b/src/lib/nhlt.c @@ -390,11 +390,12 @@ static void nhlt_serialize_endpoints(struct nhlt *nhlt, struct cursor *cur) uintptr_t nhlt_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { - return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); + return nhlt_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0); } uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) { struct cursor cur; acpi_header_t *header; @@ -424,6 +425,7 @@ uintptr_t nhlt_serialize_oem_overrides(struct nhlt *nhlt, memcpy(header->oem_id, oem_id, oem_id_len); memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); + write_le32(&header->oem_revision, oem_revision); memcpy(header->asl_compiler_id, ASLC, 4); cur.buf = (void *)(acpi_addr + sizeof(acpi_header_t)); diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 4d4ef53..44858d4 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -54,6 +54,7 @@ static unsigned long mainboard_write_acpi_tables( struct nhlt *nhlt; const char *oem_id = NULL; const char *oem_table_id = NULL; + uint32_t oem_revision = 0; start_addr = current; @@ -66,7 +67,7 @@ static unsigned long mainboard_write_acpi_tables( variant_nhlt_oem_strings(&oem_id, &oem_table_id); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, oem_revision); if (end_addr != start_addr) acpi_add_table(rsdp, (void *)start_addr); diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 9f79db6..cbadc2e 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -84,7 +84,7 @@ static unsigned long mainboard_write_acpi_tables( printk(BIOS_ERR, "Couldn't add headset codec.\n"); end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, 0); if (end_addr != start_addr) acpi_add_table(rsdp, (void *)start_addr); diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c index 03a4b4f..a268ea6 100644 --- a/src/soc/intel/common/nhlt.c +++ b/src/soc/intel/common/nhlt.c @@ -19,11 +19,12 @@ uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) { - return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL); + return nhlt_soc_serialize_oem_overrides(nhlt, acpi_addr, NULL, NULL, 0); } uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, - uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id) + uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id, + uint32_t oem_revision) { global_nvs_t *gnvs; @@ -37,5 +38,5 @@ uintptr_t nhlt_soc_serialize_oem_overrides(struct nhlt *nhlt, gnvs->nhll = nhlt_current_size(nhlt); return nhlt_serialize_oem_overrides(nhlt, acpi_addr, - oem_id, oem_table_id); + oem_id, oem_table_id, oem_revision); }

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Patch set updated for coreboot: arch/x86: cache postcar in stage cache
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17649 -gerrit commit a8ac92fe424c021b4cd893168dd6671f5eba58ba Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 15:52:08 2016 -0600 arch/x86: cache postcar in stage cache Stash and reload postcar stage in the stage cache for increased S3 resume speed. It's impact is small (2 ms or so), but there's no need to go to the boot media on resume to reload something that was already loaded. This aligns with the same paths we take on ramstage as well. Change-Id: I4313794826120853163c7366e81346858747ed0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/postcar_loader.c | 28 +++++++++++++++++++++------- src/include/stage_cache.h | 1 + 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index d9719ff..948e445 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -20,6 +20,8 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include <rmodule.h> +#include <romstage_handoff.h> +#include <stage_cache.h> static inline void stack_push(struct postcar_frame *pcf, uint32_t val) { @@ -110,18 +112,14 @@ void *postcar_commit_mtrrs(struct postcar_frame *pcf) return (void *) pcf->stack; } -void run_postcar_phase(struct postcar_frame *pcf) +static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) { - struct prog prog = - PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); struct rmod_stage_load rsl = { .cbmem_id = CBMEM_ID_AFTER_CAR, - .prog = &prog, + .prog = prog, }; - postcar_commit_mtrrs(pcf); - - if (prog_locate(&prog)) + if (prog_locate(prog)) die("Failed to locate after CAR program.\n"); if (rmodule_stage_load(&rsl)) die("Failed to load after CAR program.\n"); @@ -139,5 +137,21 @@ void run_postcar_phase(struct postcar_frame *pcf) prog_segment_loaded((uintptr_t)rsl.params, sizeof(uintptr_t), SEG_FINAL); + if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE)) + stage_cache_add(STAGE_POSTCAR, prog); +} + +void run_postcar_phase(struct postcar_frame *pcf) +{ + struct prog prog = + PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar"); + + postcar_commit_mtrrs(pcf); + + if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) && romstage_handoff_is_resume()) + stage_cache_load_stage(STAGE_POSTCAR, &prog); + else + load_postcar_cbfs(&prog, pcf); + prog_run(&prog); } diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index a24ea71..fbf9c46 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -23,6 +23,7 @@ enum { STAGE_RAMSTAGE, STAGE_REFCODE, + STAGE_POSTCAR, }; /* Cache the loaded stage provided according to the parameters. */

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Patch set updated for coreboot: lib: put romstage_handoff implementation in own compilation unit
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17648 -gerrit commit 58922fbdd6a10c8615d3ed077a7ad1806cc4adc2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:37:42 2016 -0600 lib: put romstage_handoff implementation in own compilation unit Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage.c | 1 + src/include/romstage_handoff.h | 74 +------------------- src/lib/Makefile.inc | 3 + src/lib/romstage_handoff.c | 80 ++++++++++++++++++++++ src/mainboard/google/gru/romstage.c | 2 + src/soc/intel/baytrail/romstage/romstage.c | 1 + src/soc/intel/braswell/romstage/romstage.c | 1 + src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 1 + 8 files changed, 91 insertions(+), 72 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index b222082..bb3e96c 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -34,6 +34,7 @@ #include <smbios.h> #include <soc/intel/common/mrc_cache.h> #include <stage_cache.h> +#include <string.h> #include <timestamp.h> #include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 9e254cd..1a6bbf7 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -15,80 +15,10 @@ #ifndef ROMSTAGE_HANDOFF_H #define ROMSTAGE_HANDOFF_H -#include <stdint.h> -#include <string.h> -#include <cbmem.h> -#include <console/console.h> -#include <rules.h> - -/* It is the chipset's responsibility for maintaining the integrity of this - * structure in CBMEM. For instance, if chipset code adds this structure - * using the CBMEM_ID_ROMSTAGE_INFO id it needs to ensure it doesn't clobber - * fields it doesn't own. */ -struct romstage_handoff { - /* Indicate if the current boot is an S3 resume. If - * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is - * responsible for initializing this variable. Otherwise, ramstage - * will be re-loaded from cbfs (which can be slower since it lives - * in flash). */ - uint8_t s3_resume; - uint8_t reboot_required; - uint8_t reserved[2]; -}; - -/* The romstage_handoff_find_or_add() function provides the necessary logic - * for initializing the romstage_handoff structure in cbmem. Different components - * of the romstage may be responsible for setting up different fields. Therefore - * that same logic flow should be used for allocating and initializing the - * structure. A newly allocated structure will be memset to 0. */ -static inline struct romstage_handoff *romstage_handoff_find_or_add(void) -{ - struct romstage_handoff *handoff; - - /* cbmem_add() first does a find and uses the old location before the - * real add. However, it is important to know when the structure is not - * found so it can be initialized to 0. */ - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff) - return handoff; - - handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); - - if (handoff != NULL) - memset(handoff, 0, sizeof(*handoff)); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - return handoff; -} - /* Returns 0 if initialized. Else < 0 if handoff structure not added. */ -static inline int romstage_handoff_init(int is_s3_resume) -{ - struct romstage_handoff *handoff; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) - return -1; - - handoff->s3_resume = is_s3_resume; - - return 0; -} +int romstage_handoff_init(int is_s3_resume); /* Return 1 if resuming or 0 if not. */ -static inline int romstage_handoff_is_resume(void) -{ - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) - return 0; - - return handoff->s3_resume; -} +int romstage_handoff_is_resume(void); #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ddade2b..4157091 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -87,6 +87,8 @@ romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c +ramstage-y += romstage_handoff.c +romstage-y += romstage_handoff.c romstage-y += romstage_stack.c ramstage-y += romstage_stack.c romstage-y += stack.c @@ -153,6 +155,7 @@ postcar-y += cbmem_common.c postcar-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c postcar-y += imd_cbmem.c postcar-y += imd.c +postcar-y += romstage_handoff.c bootblock-y += hexdump.c ramstage-y += hexdump.c diff --git a/src/lib/romstage_handoff.c b/src/lib/romstage_handoff.c new file mode 100644 index 0000000..bdfdb64 --- /dev/null +++ b/src/lib/romstage_handoff.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <romstage_handoff.h> +#include <rules.h> + +struct romstage_handoff { + /* Indicate if the current boot is an S3 resume. If + * CONFIG_RELOCTABLE_RAMSTAGE is enabled the chipset code is + * responsible for initializing this variable. Otherwise, ramstage + * will be re-loaded from cbfs (which can be slower since it lives + * in flash). */ + uint8_t s3_resume; + uint8_t reboot_required; + uint8_t reserved[2]; +}; + +static struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + struct romstage_handoff *handoff; + + /* cbmem_add() first does a find and uses the old location before the + * real add. However, it is important to know when the structure is not + * found so it can be initialized to 0. */ + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff) + return handoff; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + + if (handoff != NULL) + memset(handoff, 0, sizeof(*handoff)); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + return handoff; +} + +int romstage_handoff_init(int is_s3_resume) +{ + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + if (handoff == NULL) + return -1; + + handoff->s3_resume = is_s3_resume; + + return 0; +} + +int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +} diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index 1e2507a..55ed79a 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -19,6 +19,7 @@ #include <arch/exception.h> #include <arch/mmu.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -28,6 +29,7 @@ #include <soc/sdram.h> #include <symbols.h> #include <soc/usb.h> +#include <stdlib.h> #include "pwm_regulator.h" diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 124eb6e..d457151 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -28,6 +28,7 @@ #include <program_loading.h> #include <romstage_handoff.h> #include <stage_cache.h> +#include <string.h> #include <timestamp.h> #include <tpm.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 95880e8..0125847 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <elog.h> #include <romstage_handoff.h> +#include <string.h> #include <timestamp.h> #include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 49bdedb..49d9a94 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -19,6 +19,7 @@ #include <lib.h> #include <arch/io.h> #include <arch/cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <program_loading.h>

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Patch set updated for coreboot: romstage_handoff: add helper to determine resume status
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17647 -gerrit commit 482baa4a760107a862f88340515a0a024ba393a1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 21:22:42 2016 -0600 romstage_handoff: add helper to determine resume status Instead of having callers query the romstage handoff resume status by inspecing the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/acpi_s3.c | 9 +-------- src/include/romstage_handoff.h | 13 +++++++++++++ src/lib/prog_loaders.c | 25 ++++++++++++------------- src/soc/intel/apollolake/chip.c | 4 +--- src/soc/intel/quark/chip.c | 5 +---- src/soc/intel/skylake/chip_fsp20.c | 7 +------ 6 files changed, 29 insertions(+), 34 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ffec64d..f3cb097 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -32,14 +32,7 @@ int acpi_slp_type = -1; #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) int acpi_get_sleep_type(void) { - struct romstage_handoff *handoff; - - handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - - if (handoff == NULL) { - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - return ACPI_S0; - } else if (handoff->s3_resume) { + if (romstage_handoff_is_resume()) { printk(BIOS_DEBUG, "S3 Resume.\n"); return ACPI_S3; } else { diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 3eba0fd..9e254cd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -78,4 +78,17 @@ static inline int romstage_handoff_init(int is_s3_resume) return 0; } +/* Return 1 if resuming or 0 if not. */ +static inline int romstage_handoff_is_resume(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff == NULL) + return 0; + + return handoff->s3_resume; +} + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3a6f2e2..58c1a8a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -85,19 +85,19 @@ static void ramstage_cache_invalid(void) } } -static void run_ramstage_from_resume(struct romstage_handoff *handoff, - struct prog *ramstage) +static void run_ramstage_from_resume(struct prog *ramstage) { - if (handoff != NULL && handoff->s3_resume) { - /* Load the cached ramstage to runtime location. */ - stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); - - if (prog_entry(ramstage) != NULL) { - printk(BIOS_DEBUG, "Jumping to image.\n"); - prog_run(ramstage); - } - ramstage_cache_invalid(); + if (!romstage_handoff_is_resume()) + return; + + /* Load the cached ramstage to runtime location. */ + stage_cache_load_stage(STAGE_RAMSTAGE, ramstage); + + if (prog_entry(ramstage) != NULL) { + printk(BIOS_DEBUG, "Jumping to image.\n"); + prog_run(ramstage); } + ramstage_cache_invalid(); } static int load_relocatable_ramstage(struct prog *ramstage) @@ -136,8 +136,7 @@ void run_ramstage(void) if (IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_NO_STAGE_CACHE) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) - run_ramstage_from_resume(romstage_handoff_find_or_add(), - &ramstage); + run_ramstage_from_resume(&ramstage); if (prog_locate(&ramstage)) goto fail; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ef5908c..32d68cc 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -260,7 +260,6 @@ static void set_power_limits(void) static void soc_init(void *data) { struct global_nvs_t *gnvs; - struct romstage_handoff *handoff; /* Save VBT info and mapping */ vbt = vbt_get(&vbt_rdev); @@ -269,8 +268,7 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); /* Restore GPIO IRQ polarities back to previous settings. */ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index 150df12..5e80463 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -102,8 +102,6 @@ static const struct reg_script thermal_init_script[] = { static void chip_init(void *chip_info) { - struct romstage_handoff *handoff; - /* Validate the temperature settings */ ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS <= 255); ASSERT(PLATFORM_CATASTROPHIC_TRIP_CELSIUS @@ -120,8 +118,7 @@ static void chip_init(void *chip_info) | TS_LOCK_AUX_TRIP_PT_REGS_ENABLE)); /* Perform silicon specific init. */ - handoff = romstage_handoff_find_or_add(); - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f90f6bc..0768779 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -35,13 +35,8 @@ void soc_init_pre_device(void *chip_info) { - struct romstage_handoff *handoff; - - /* Get S3 status to pass to silicon init. */ - handoff = romstage_handoff_find_or_add(); - /* Perform silicon specific init. */ - fsp_silicon_init(handoff->s3_resume); + fsp_silicon_init(romstage_handoff_is_resume()); } static void pci_domain_set_resources(device_t dev)

1 0

Patch set updated for coreboot: romstage_handoff: remove code duplication
by Aaron Durbin 30 Nov '16

30 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17646 -gerrit commit 70f1193890549227b963c9bfabac8f580c659dda Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 17:43:04 2016 -0600 romstage_handoff: remove code duplication The same pattern was being used throughout the code base for initializing the romstage handoff structure. Provide a helper function to initialize the structure with the S3 resume state then utilize it at all the existing call sites. Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/amd/car/post_cache_as_ram.c | 9 +------- src/cpu/intel/haswell/romstage.c | 7 +----- src/drivers/intel/fsp1_1/romstage.c | 10 ++------- src/drivers/intel/fsp2_0/memory_init.c | 7 +----- src/include/romstage_handoff.h | 31 +++++++++++++++++++++----- src/northbridge/intel/sandybridge/early_init.c | 8 +------ src/soc/intel/baytrail/romstage/romstage.c | 7 +----- src/soc/intel/broadwell/romstage/romstage.c | 9 +------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 7 +----- 9 files changed, 35 insertions(+), 60 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 296adc9..88b8637 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -129,14 +129,7 @@ void post_cache_as_ram(void) prepare_romstage_ramstack(s3resume); - if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) { - struct romstage_handoff *handoff; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3resume; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - } + romstage_handoff_init(s3resume); /* from here don't store more data in CAR */ if (family >= 0x1f && family <= 0x3f) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 48920b3..7eb115c 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -172,7 +172,6 @@ void romstage_common(const struct romstage_params *params) { int boot_mode; int wake_from_s3; - struct romstage_handoff *handoff; timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -245,11 +244,7 @@ void romstage_common(const struct romstage_params *params) #endif } - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = wake_from_s3; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(wake_from_s3); post_code(0x3f); if (IS_ENABLED(CONFIG_LPC_TPM)) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 97379b2..b222082 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -99,7 +99,6 @@ void *cache_as_ram_stage_main(FSP_INFO_HEADER *fih) void romstage_common(struct romstage_params *params) { const struct mrc_saved_data *cache; - struct romstage_handoff *handoff; struct pei_data *pei_data; post_code(0x32); @@ -165,14 +164,9 @@ void romstage_common(struct romstage_params *params) mainboard_save_dimm_info(params); /* Create romstage handof information */ - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (params->power_state->prev_sleep_state == - ACPI_S3); - else { - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + if (romstage_handoff_init( + params->power_state->prev_sleep_state == ACPI_S3) < 0) hard_reset(); - } /* * Initialize the TPM, unless the TPM was already initialized diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..c0cb5d3 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -117,7 +117,6 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version) static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) { struct range_entry fsp_mem; - struct romstage_handoff *handoff; if (fsp_find_reserved_memory(&fsp_mem)) die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n"); @@ -144,11 +143,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) save_memory_training_data(s3wake, fsp_version); /* Create romstage handof information */ - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3wake; - else - printk(BIOS_SPEW, "Romstage handoff structure not added!\n"); + romstage_handoff_init(s3wake); } static const char *mrc_cache_get_region_name(void) diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 4aba2ce..3eba0fd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -18,6 +18,8 @@ #include <stdint.h> #include <string.h> #include <cbmem.h> +#include <console/console.h> +#include <rules.h> /* It is the chipset's responsibility for maintaining the integrity of this * structure in CBMEM. For instance, if chipset code adds this structure @@ -48,13 +50,32 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) * found so it can be initialized to 0. */ handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); - if (handoff == NULL) { - handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); - if (handoff != NULL) - memset(handoff, 0, sizeof(*handoff)); - } + if (handoff) + return handoff; + + handoff = cbmem_add(CBMEM_ID_ROMSTAGE_INFO, sizeof(*handoff)); + + if (handoff != NULL) + memset(handoff, 0, sizeof(*handoff)); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); return handoff; } +/* Returns 0 if initialized. Else < 0 if handoff structure not added. */ +static inline int romstage_handoff_init(int is_s3_resume) +{ + struct romstage_handoff *handoff; + + handoff = romstage_handoff_find_or_add(); + + if (handoff == NULL) + return -1; + + handoff->s3_resume = is_s3_resume; + + return 0; +} + #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index ef97a1a..16ea29d 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -227,13 +227,7 @@ void sandybridge_early_initialization(int chipset_type) void northbridge_romstage_finalize(int s3resume) { - struct romstage_handoff *handoff; - MCHBAR16(SSKPD) = 0xCAFE; - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = s3resume; - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(s3resume); } diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index a61b571..124eb6e 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -210,7 +210,6 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps) /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct romstage_handoff *handoff; struct chipset_power_state *ps; int prev_sleep_state; @@ -232,11 +231,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(prev_sleep_state == ACPI_S3); if (IS_ENABLED(CONFIG_LPC_TPM)) { init_tpm(prev_sleep_state == ACPI_S3); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 44df88c..849c55d 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -89,8 +89,6 @@ void * asmlinkage romstage_main(unsigned long bist, /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct romstage_handoff *handoff; - post_code(0x32); timestamp_add_now(TS_BEFORE_INITRAM); @@ -114,12 +112,7 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (params->power_state->prev_sleep_state == - ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); #if CONFIG_LPC_TPM init_tpm(params->power_state->prev_sleep_state == ACPI_S3); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a7ed414..9d204d1 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -218,7 +218,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; - struct romstage_handoff *handoff; timestamp_add_now(TS_AFTER_INITRAM); @@ -257,11 +256,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == ACPI_S3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + romstage_handoff_init(prev_sleep_state == ACPI_S3); post_code(0x4f);

1 0

Patch set updated for coreboot: google/pyro: set i2c bus timings by rise/fall times
by Kevin Chiu 30 Nov '16

30 Nov '16

Kevin Chiu (Kevin.Chiu(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17652 -gerrit commit b3982d4e78fe382849fe3e42a008cc969b1d510a Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Nov 30 16:30:28 2016 +0800 google/pyro: set i2c bus timings by rise/fall times Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- .../google/reef/variants/pyro/devicetree.cb | 41 +++++++--------------- 1 file changed, 12 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index d5745b4..27c5031 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -71,50 +71,33 @@ chip soc/intel/apollolake register "gpe0_dw2" = "PMC_GPE_N_63_32" register "gpe0_dw3" = "PMC_GPE_SW_31_0" - # Limit I2C0 Audio codec da7219 speed to 400kHz with manually tuned values. + # Enable I2C0 for audio codec at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 104, + .fall_time_ns = 52, }" - # Enable I2C2 bus early for TPM access and configure as 400kHz - # with manually tuned values. + # Enable I2C2 bus early for TPM at 400kHz register "i2c[2]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 50, + .fall_time_ns = 23, }" - # Limit I2C3 WACOM touchscreen speed to 400kHz with manually tuned values. + # touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 76, + .fall_time_ns = 164, }" - # Limit trackpad speed to 400kHz with manually tuned values. + # trackpad at 400kHz register "i2c[4]" = "{ .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 0xd0, - .scl_hcnt = 0x68, - .sda_hold = 0x27, - } + .rise_time_ns = 90, + .fall_time_ns = 164, }" # Minimum SLP S3 assertion width 28ms.

1 0

Patch merged into coreboot/master: intel/fsp_rangeley: Fix regression on MMCONF_SUPPORT
by gerrit＠coreboot.org 30 Nov '16

30 Nov '16

the following patch was just integrated into master: commit 1b446a47ea2ea3816782729c1a17d670cf120b06 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 11:46:10 2016 +0200 intel/fsp_rangeley: Fix regression on MMCONF_SUPPORT Following commit did not move this selection to northbridge: bac0fad Remove explicit select MMCONF_SUPPORT Change-Id: I5f3c429dfd160eb439f396db2baf0ecf280022fd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17653 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17653 for details. -gerrit

1 0

New patch to review for coreboot: buildsystem: Promote rules.h to default include
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17656 -gerrit commit e67bd0b9772940bbca064032f955885cc597fce1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 14:53:24 2016 +0200 buildsystem: Promote rules.h to default include Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- Makefile.inc | 1 + src/arch/arm/armv7/cpu.S | 1 - src/arch/arm64/boot.c | 1 - src/arch/arm64/include/arch/header.ld | 1 - src/arch/riscv/boot.c | 1 - src/arch/x86/acpi_s3.c | 1 - src/arch/x86/assembly_entry.S | 1 - src/arch/x86/include/arch/acpi.h | 1 - src/arch/x86/include/arch/cpu.h | 1 - src/arch/x86/include/arch/early_variables.h | 1 - src/arch/x86/include/arch/header.ld | 1 - src/arch/x86/include/arch/io.h | 1 - src/arch/x86/include/arch/memlayout.h | 1 - src/console/console.c | 1 - src/console/init.c | 1 - src/console/post.c | 1 - src/cpu/intel/microcode/microcode.c | 1 - src/cpu/x86/32bit/entry32.inc | 1 - src/drivers/intel/fsp1_1/cache_as_ram.inc | 1 - src/drivers/intel/fsp1_1/include/fsp/util.h | 1 - src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 - src/drivers/spi/spi_flash.c | 1 - src/drivers/uart/uart8250io.c | 1 - src/drivers/uart/uart8250mem.c | 1 - src/include/bootstate.h | 1 - src/include/cbmem.h | 1 - src/include/console/cbmem_console.h | 1 - src/include/console/console.h | 1 - src/include/console/ne2k.h | 1 - src/include/console/qemu_debugcon.h | 1 - src/include/console/spi.h | 1 - src/include/console/spkmodem.h | 1 - src/include/console/uart.h | 1 - src/include/console/usb.h | 1 - src/include/device/device.h | 1 - src/include/device/pci.h | 1 - src/include/device/pnp.h | 1 - src/include/memlayout.h | 1 - src/lib/bootmode.c | 1 - src/lib/cbmem_common.c | 1 - src/lib/ext_stage_cache.c | 1 - src/lib/imd_cbmem.c | 1 - src/lib/prog_loaders.c | 1 - src/lib/timestamp.c | 1 - src/mainboard/google/chell/chromeos.c | 1 - src/mainboard/google/cyan/chromeos.c | 1 - src/mainboard/google/eve/chromeos.c | 1 - src/mainboard/google/glados/chromeos.c | 1 - src/mainboard/google/lars/chromeos.c | 1 - src/mainboard/google/reef/ec.c | 1 - src/mainboard/google/storm/mmu.c | 1 - src/mainboard/intel/kblrvp/chromeos.c | 1 - src/mainboard/intel/kunimitsu/chromeos.c | 1 - src/mainboard/intel/strago/chromeos.c | 1 - src/northbridge/intel/fsp_rangeley/northbridge.h | 1 - src/northbridge/intel/gm45/gm45.h | 1 - src/northbridge/intel/sandybridge/sandybridge.h | 1 - src/soc/intel/apollolake/include/soc/pci_devs.h | 1 - src/soc/intel/apollolake/p2sb.c | 1 - src/soc/intel/apollolake/pmutil.c | 1 - src/soc/intel/braswell/acpi.c | 1 - src/soc/intel/braswell/include/soc/iosf.h | 1 - src/soc/intel/braswell/include/soc/nvs.h | 1 - src/soc/intel/braswell/include/soc/smm.h | 1 - src/soc/intel/braswell/pmutil.c | 1 - src/soc/intel/braswell/spi.c | 1 - src/soc/intel/braswell/tsc_freq.c | 1 - src/soc/intel/quark/romstage/car_stage_entry.S | 1 - src/soc/intel/skylake/bootblock/cache_as_ram.S | 1 - src/soc/intel/skylake/include/soc/flash_controller.h | 1 - src/soc/intel/skylake/include/soc/nvs.h | 1 - src/soc/intel/skylake/include/soc/pch.h | 1 - src/soc/intel/skylake/include/soc/pci_devs.h | 1 - src/soc/intel/skylake/include/soc/xhci.h | 1 - src/soc/intel/skylake/pmutil.c | 1 - src/soc/intel/skylake/romstage/car_stage.S | 1 - src/soc/marvell/mvmap2315/uart.c | 1 - src/soc/nvidia/tegra210/include/soc/memlayout.ld | 1 - src/vboot/bootmode.c | 1 - src/vboot/vboot_common.c | 1 - src/vboot/vboot_loader.c | 1 - src/vendorcode/google/chromeos/chromeos.h | 1 - 82 files changed, 1 insertion(+), 81 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index a193158..5f00244 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -351,6 +351,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h +CPPFLAGS_common += -include $(src)/include/rules.h CPPFLAGS_common += -I3rdparty CFLAGS_common += -pipe -g -nostdinc diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S index 21a16d2..b1ab048 100644 --- a/src/arch/arm/armv7/cpu.S +++ b/src/arch/arm/armv7/cpu.S @@ -31,7 +31,6 @@ */ #include <arch/asm.h> -#include <rules.h> /* * Dcache invalidations by set/way work by passing a [way:sbz:set:sbz:level:0] diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index d498cd9..7909d5f 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include <console/console.h> #include <program_loading.h> -#include <rules.h> #include <string.h> static void run_payload(struct prog *prog) diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index c82cb3f..f610ec0 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 9483c48..0fbfdbc 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -16,7 +16,6 @@ #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> -#include <rules.h> #include <console/console.h> #include <commonlib/configstring.h> diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index ffec64d..fcaeba6 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -21,7 +21,6 @@ #include <timestamp.h> #include <program_loading.h> #include <romstage_handoff.h> -#include <rules.h> #include <symbols.h> #if ENV_RAMSTAGE diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index d1f5d61..e530745 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> /* *Take the path where CAR_GLOBAL variables just need to be cleared when diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7c29648..1765ac0 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -44,7 +44,6 @@ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) #include <stdint.h> -#include <rules.h> #include <commonlib/helpers.h> #include <device/device.h> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index faa2375..013a73d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -16,7 +16,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> /* * EFLAGS bits diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index e78b846..fe32fab 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -18,7 +18,6 @@ #include <arch/symbols.h> #include <stdlib.h> -#include <rules.h> #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) asm(".section .car.global_data,\"w\",@nobits"); diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 77eb187..3bf98fe 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> PHDRS { diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 69922e2..fa91ea5 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -16,7 +16,6 @@ #include <endian.h> #include <stdint.h> -#include <rules.h> /* FIXME: Sources for romstage still use device_t. */ /* Use pci_devfn_t or pnp_devfn_t instead */ diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 83e5b90..f93dece 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,7 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -#include <rules.h> #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE /* No .data or .bss sections. Cache as RAM is handled separately. */ diff --git a/src/console/console.c b/src/console/console.c index 7b0dfc2..dbe503d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -21,7 +21,6 @@ #include <console/uart.h> #include <console/usb.h> #include <console/spi.h> -#include <rules.h> void console_hw_init(void) { diff --git a/src/console/init.c b/src/console/init.c index 189079b..e4d0e6c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -19,7 +19,6 @@ #include <console/streams.h> #include <device/pci.h> #include <option.h> -#include <rules.h> #include <version.h> /* While in romstage, console loglevel is built-time constant. */ diff --git a/src/console/post.c b/src/console/post.c index 481a1f4..08cf640 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <pc80/mc146818rtc.h> #include <smp/spinlock.h> -#include <rules.h> /* Write POST information */ diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 1285c12..f3ea6cb 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/microcode.h> -#include <rules.h> #if !defined(__PRE_RAM__) #include <smp/spinlock.h> diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 8c39008..133f708 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -2,7 +2,6 @@ #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> -#include <rules.h> .code32 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6611fa1..0302cc6 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -24,7 +24,6 @@ * performs the final stage of initialization. */ -#include <rules.h> #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index eea0c33..c243f97 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -17,7 +17,6 @@ #ifndef FSP1_1_UTIL_H #define FSP1_1_UTIL_H -#include <rules.h> #include <fsp/api.h> /* Current users expect to get the SoC's FSP definitions by including util.h. */ #include <fsp/soc_binding.h> diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..2fb08cd 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -13,7 +13,6 @@ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ -#include <rules.h> #include <stdint.h> #include <stdlib.h> #include <types.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b2fdab9..cb85425 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -13,7 +13,6 @@ #include <cbfs.h> #include <cpu/x86/smm.h> #include <delay.h> -#include <rules.h> #include <stdlib.h> #include <string.h> #include <spi-generic.h> diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index ac3315a..b8edd0c 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <stdlib.h> #include <arch/io.h> #include <console/uart.h> diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 4e53a92..7e1a12a 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -19,7 +19,6 @@ #include <console/uart.h> #include <device/device.h> #include <delay.h> -#include <rules.h> #include <stdint.h> #include "uart8250reg.h" diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 09178a5..49f8c2a 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -15,7 +15,6 @@ #ifndef BOOTSTATE_H #define BOOTSTATE_H -#include <rules.h> #include <string.h> #include <stdlib.h> #include <stddef.h> diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5c4b7c7..87b63d8 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -18,7 +18,6 @@ #define _CBMEM_H_ #include <commonlib/cbmem_id.h> -#include <rules.h> #include <stddef.h> #include <stdint.h> #include <boot/coreboot_tables.h> diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index de1144b..04b6b38 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -15,7 +15,6 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#include <rules.h> #include <stdint.h> void cbmemc_init(void); diff --git a/src/include/console/console.h b/src/include/console/console.h index 013ef20..0c66b19 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -17,7 +17,6 @@ #define CONSOLE_CONSOLE_H_ #include <stdint.h> -#include <rules.h> #include <arch/cpu.h> #include <console/post_codes.h> #include <commonlib/loglevel.h> diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index d7974b5..c79d58c 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -16,7 +16,6 @@ #ifndef _NE2K_H__ #define _NE2K_H__ -#include <rules.h> #include <stdint.h> void ne2k_append_data(unsigned char *d, int len, unsigned int base); diff --git a/src/include/console/qemu_debugcon.h b/src/include/console/qemu_debugcon.h index 257ae58..33b274a 100644 --- a/src/include/console/qemu_debugcon.h +++ b/src/include/console/qemu_debugcon.h @@ -1,7 +1,6 @@ #ifndef _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_ -#include <rules.h> #include <stdint.h> void qemu_debugcon_init(void); diff --git a/src/include/console/spi.h b/src/include/console/spi.h index bf58a36..451359c 100644 --- a/src/include/console/spi.h +++ b/src/include/console/spi.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_SPI_H #define CONSOLE_SPI_H 1 -#include <rules.h> #include <stdint.h> void spiconsole_init(void); diff --git a/src/include/console/spkmodem.h b/src/include/console/spkmodem.h index dfd21d4..76760fd 100644 --- a/src/include/console/spkmodem.h +++ b/src/include/console/spkmodem.h @@ -1,7 +1,6 @@ #ifndef SPKMODEM_H #define SPKMODEM_H 1 -#include <rules.h> #include <stdint.h> void spkmodem_init(void); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ffcc088..da82d99 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -16,7 +16,6 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H -#include <rules.h> #include <stdint.h> /* Return the clock frequency UART uses as reference clock for diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..7f5998d 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -17,7 +17,6 @@ #ifndef _CONSOLE_USB_H_ #define _CONSOLE_USB_H_ -#include <rules.h> #include <stdint.h> int usbdebug_init(void); diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..ada985b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,7 +10,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <device/resource.h> #include <device/path.h> diff --git a/src/include/device/pci.h b/src/include/device/pci.h index e167752..1e8adad 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -19,7 +19,6 @@ #include <stdint.h> #include <stddef.h> -#include <rules.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/resource.h> diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index cfed7c7..d84541f 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,7 +2,6 @@ #define DEVICE_PNP_H #include <stdint.h> -#include <rules.h> #include <device/device.h> #include <device/pnp_def.h> #include <arch/io.h> diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a68b21f..4d44be0 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -18,7 +18,6 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H -#include <rules.h> #include <arch/memlayout.h> /* Macros that the architecture can override. */ diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index dcee2d1..29682eb 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 2a057d6..d75597e 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <cbmem.h> #include <bootstate.h> -#include <rules.h> #include <symbols.h> #if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index 2a99188..1f1c0e4 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -18,7 +18,6 @@ #include <cbmem.h> #include <console/console.h> #include <imd.h> -#include <rules.h> #include <stage_cache.h> #include <string.h> diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index b0273f4..2037ec9 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <cbmem.h> #include <imd.h> -#include <rules.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3a6f2e2..54e5967 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -25,7 +25,6 @@ #include <reset.h> #include <romstage_handoff.h> #include <rmodule.h> -#include <rules.h> #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 2f2a5d8..71dd3a9 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -22,7 +22,6 @@ #include <timer.h> #include <timestamp.h> #include <arch/early_variables.h> -#include <rules.h> #include <smp/node.h> #define MAX_TIMESTAMPS 84 diff --git a/src/mainboard/google/chell/chromeos.c b/src/mainboard/google/chell/chromeos.c index fdd1486..416790e 100644 --- a/src/mainboard/google/chell/chromeos.c +++ b/src/mainboard/google/chell/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 672bc97..5ee4bf4 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <rules.h> #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/eve/chromeos.c b/src/mainboard/google/eve/chromeos.c index de83eaa..a03e5cf 100644 --- a/src/mainboard/google/eve/chromeos.c +++ b/src/mainboard/google/eve/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 9ee6e6f..2f655f9 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -15,7 +15,6 @@ */ #include <bootmode.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/lars/chromeos.c b/src/mainboard/google/lars/chromeos.c index 42763a7..6ab7c73 100644 --- a/src/mainboard/google/lars/chromeos.c +++ b/src/mainboard/google/lars/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/google/reef/ec.c b/src/mainboard/google/reef/ec.c index 646216b..0382b6c 100644 --- a/src/mainboard/google/reef/ec.c +++ b/src/mainboard/google/reef/ec.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> -#include <rules.h> #include <soc/lpc.h> #include <variant/ec.h> diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index da15795..ba773c5 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -11,7 +11,6 @@ */ #include <arch/cache.h> -#include <rules.h> #include <soc/soc_services.h> #include <symbols.h> #include "mmu.h" diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index fc1bcd2..bed876d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 42763a7..6ab7c73 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <soc/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 6d00d72..1197efd 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <rules.h> #include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index ba4cfdd..92e99fb 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -23,7 +23,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <rules.h> #include <device/device.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index b9d2cb7..9960951 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,7 +21,6 @@ #ifndef __ACPI__ -#include <rules.h> #include <stdint.h> typedef enum { diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index e737e50..35a56a2 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -62,7 +62,6 @@ /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ -#include <rules.h> /* Device 0:0.0 PCI configuration space (Host Bridge) */ diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index d058f8b..48fa499 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -15,7 +15,6 @@ #ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_ #define _SOC_APOLLOLAKE_PCI_DEVS_H_ -#include <rules.h> #define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) #define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func) diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c index 7834e38..93cdd20 100644 --- a/src/soc/intel/apollolake/p2sb.c +++ b/src/soc/intel/apollolake/p2sb.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/pci_ids.h> diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index c88e5ae..9279545 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -21,7 +21,6 @@ #include <arch/io.h> #include <console/console.h> #include <cbmem.h> -#include <rules.h> #include <device/pci_def.h> #include <halt.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 0e866a5..2972037 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -32,7 +32,6 @@ #include <device/pci_ids.h> #include <ec/google/chromeec/ec.h> #include <fsp/gop.h> -#include <rules.h> #include <soc/acpi.h> #include <soc/gfx.h> #include <soc/iomap.h> diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index c0b3f06..7b5b577 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -17,7 +17,6 @@ #ifndef _SOC_IOSF_H_ #define _SOC_IOSF_H_ -#include <rules.h> #include <stdint.h> #if ENV_RAMSTAGE #include <device/device.h> diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index d3dfd28..44364a0 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -18,7 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 13b511a..93065a2 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -17,7 +17,6 @@ #ifndef _SOC_SMM_H_ #define _SOC_SMM_H_ -#include <rules.h> #if ENV_RAMSTAGE #include <stdint.h> diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 018915c..6e768f2 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <console/console.h> -#include <rules.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 97ca2e5..ebc3fed 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> -#include <rules.h> #include <soc/lpc.h> #include <soc/pci_devs.h> #include <spi-generic.h> diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 929b6b5..24e8b56 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -16,7 +16,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> -#include <rules.h> #include <soc/msr.h> #include <console/console.h> #if ENV_RAMSTAGE diff --git a/src/soc/intel/quark/romstage/car_stage_entry.S b/src/soc/intel/quark/romstage/car_stage_entry.S index b820711..7a7789b 100644 --- a/src/soc/intel/quark/romstage/car_stage_entry.S +++ b/src/soc/intel/quark/romstage/car_stage_entry.S @@ -18,7 +18,6 @@ * Replacement for cache_as_ram.inc when using the C environment boot block. */ -#include <rules.h> #include <soc/sd.h> .section ".text" diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S index 3f8f0f0..a5dab01 100644 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S @@ -18,7 +18,6 @@ #include <cpu/x86/cr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#include <rules.h> #define IA32_PQR_ASSOC 0x0c8f #define IA32_L3_MASK_1 0x0c91 diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h index 0050067..06b7df5 100644 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ b/src/soc/intel/skylake/include/soc/flash_controller.h @@ -16,7 +16,6 @@ #ifndef _SOC_FLASH_CONTROLLER__H_ #define _SOC_FLASH_CONTROLLER__H_ -#include <rules.h> #include <arch/io.h> #include <console/console.h> #include <spi_flash.h> diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index cb3b2c6..c1a4462 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -18,7 +18,6 @@ #ifndef _SOC_NVS_H_ #define _SOC_NVS_H_ -#include <rules.h> #include <vendorcode/google/chromeos/gnvs.h> typedef struct { diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index 701a6f5..43d0fa5 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -19,7 +19,6 @@ #define _SOC_PCH_H_ #include <device/device.h> -#include <rules.h> /* PCH (SunRisePoint LP) */ #define PCH_SPT_LP_SAMPLE 0x9d41 diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 974f1d8..239a1d7 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -18,7 +18,6 @@ #define _SOC_PCI_DEVS_H_ #include <device/pci_def.h> -#include <rules.h> #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h index c520223..2db7579 100644 --- a/src/soc/intel/skylake/include/soc/xhci.h +++ b/src/soc/intel/skylake/include/soc/xhci.h @@ -17,7 +17,6 @@ #ifndef _SOC_XHCI_H_ #define _SOC_XHCI_H_ -#include <rules.h> /* XHCI PCI Registers */ #define XHCI_PWR_CTL_STS 0x74 diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 73dc117..8a9357a 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <console/console.h> #include <halt.h> -#include <rules.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S index c6401fa..7094129 100644 --- a/src/soc/intel/skylake/romstage/car_stage.S +++ b/src/soc/intel/skylake/romstage/car_stage.S @@ -14,7 +14,6 @@ * */ -#include <rules.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> diff --git a/src/soc/marvell/mvmap2315/uart.c b/src/soc/marvell/mvmap2315/uart.c index 51c74fc..ab40a08 100644 --- a/src/soc/marvell/mvmap2315/uart.c +++ b/src/soc/marvell/mvmap2315/uart.c @@ -19,7 +19,6 @@ #include <assert.h> #include <console/uart.h> -#include <rules.h> #include <stdint.h> #include <soc/uart.h> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index c1c581b..13c2966 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -14,7 +14,6 @@ */ #include <memlayout.h> -#include <rules.h> #include <arch/header.ld> diff --git a/src/vboot/bootmode.c b/src/vboot/bootmode.c index 5bb7040..11b86ea 100644 --- a/src/vboot/bootmode.c +++ b/src/vboot/bootmode.c @@ -16,7 +16,6 @@ #include <assert.h> #include <bootmode.h> #include <bootstate.h> -#include <rules.h> #include <string.h> #include <vb2_api.h> #include <vboot/misc.h> diff --git a/src/vboot/vboot_common.c b/src/vboot/vboot_common.c index 515b368..62800a4 100644 --- a/src/vboot/vboot_common.c +++ b/src/vboot/vboot_common.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <fmap.h> #include <reset.h> -#include <rules.h> #include <stddef.h> #include <string.h> #include <vboot/vboot_common.h> diff --git a/src/vboot/vboot_loader.c b/src/vboot/vboot_loader.c index 207aada..2dd4799 100644 --- a/src/vboot/vboot_loader.c +++ b/src/vboot/vboot_loader.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <rmodule.h> -#include <rules.h> #include <string.h> #include <vboot/misc.h> #include <vboot/symbols.h> diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index fd845bf..25c60c9 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -20,7 +20,6 @@ #include <stdint.h> #include <bootmode.h> #include <device/device.h> -#include <rules.h> #include <vboot/misc.h> #include <vboot/vboot_common.h>

1 0

New patch to review for coreboot: buildsystem: Drop explicit (k)config.h includes
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17655 -gerrit commit 7efe1b4e15a85d5395c9fe9e1c2a874c7bb3f271 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Nov 30 14:59:52 2016 +0200 buildsystem: Drop explicit (k)config.h includes We have kconfig.h auto-included and it pulls config.h too. Change-Id: I665a0a168b0d4d3b8f3a27203827b542769988da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/armv7/mmu.c | 1 - src/arch/arm/include/armv4/arch/cache.h | 1 - src/arch/arm64/include/armv8/arch/cache.h | 1 - src/commonlib/configstring.c | 1 - src/cpu/allwinner/a10/ram_segs.h | 1 - src/cpu/ti/am335x/header.c | 1 - src/cpu/ti/am335x/pinmux.c | 1 - src/cpu/ti/am335x/uart.c | 1 - src/cpu/x86/smm/smmhandler.S | 2 -- src/device/pci_device.c | 1 - src/drivers/ricoh/rce822/rce822.c | 1 - src/ec/lenovo/h8/h8.c | 1 - src/northbridge/intel/gm45/gma.c | 1 - src/northbridge/intel/pineview/gma.c | 1 - src/northbridge/intel/x4x/gma.c | 1 - src/northbridge/via/vx900/chrome9hd.c | 1 - src/southbridge/intel/bd82x6x/usb_ehci.c | 1 - src/vendorcode/amd/pi/00730F01/Porting.h | 1 - 18 files changed, 19 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 6c085e9..4123bb4 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,7 +29,6 @@ */ #include <assert.h> -#include <config.h> #include <stdlib.h> #include <stdint.h> #include <symbols.h> diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index 65f5966..ed3b96f 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -32,7 +32,6 @@ #ifndef ARM_CACHE_H #define ARM_CACHE_H -#include <config.h> #include <stddef.h> #include <stdint.h> diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 64afd62..84f051d 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -32,7 +32,6 @@ #ifndef ARM_ARM64_CACHE_H #define ARM_ARM64_CACHE_H -#include <config.h> #include <stddef.h> #include <stdint.h> #include <arch/barrier.h> diff --git a/src/commonlib/configstring.c b/src/commonlib/configstring.c index 4eca6af..fc91a4b 100644 --- a/src/commonlib/configstring.c +++ b/src/commonlib/configstring.c @@ -27,7 +27,6 @@ * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. */ -#include <config.h> #include <string.h> #include <commonlib/configstring.h> diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h index fa3684f..fa915cd 100644 --- a/src/cpu/allwinner/a10/ram_segs.h +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -17,7 +17,6 @@ * How we use DRAM on Allwinner CPUs */ -#include <config.h> #include <symbols.h> /* diff --git a/src/cpu/ti/am335x/header.c b/src/cpu/ti/am335x/header.c index 6837ef8..d59e297 100644 --- a/src/cpu/ti/am335x/header.c +++ b/src/cpu/ti/am335x/header.c @@ -12,7 +12,6 @@ * GNU General Public License for more details. */ -#include <config.h> #include <stddef.h> #include <stdint.h> #include <symbols.h> diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c index 6fea9ad..1e45142 100644 --- a/src/cpu/ti/am335x/pinmux.c +++ b/src/cpu/ti/am335x/pinmux.c @@ -16,7 +16,6 @@ #include "pinmux.h" #include <arch/io.h> -#include <config.h> static struct am335x_pinmux_regs *regs = (struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR; diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index a329298..45a693a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -13,7 +13,6 @@ */ #include <stdlib.h> -#include <config.h> #include <types.h> #include <console/uart.h> #include <arch/io.h> diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index db21539..a16b3ec 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -21,8 +21,6 @@ * to 64k if we can though. */ -#include <kconfig.h> -#include <config.h> #define LAPIC_BASE_MSR 0x1b /* diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 05d4051..06294d0 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -47,7 +47,6 @@ #include <device/pciexp.h> #include <device/hypertransport.h> #include <pc80/i8259.h> -#include <kconfig.h> #include <vboot/vbnv.h> u8 pci_moving_config8(struct device *dev, unsigned int reg) diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c index 30aeabe..7bc3b40 100644 --- a/src/drivers/ricoh/rce822/rce822.c +++ b/src/drivers/ricoh/rce822/rce822.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <kconfig.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index cfc3938..b085094 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pnp.h> #include <ec/acpi/ec.h> -#include <kconfig.h> #include <stdlib.h> #include <string.h> #include <smbios.h> diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 37f81c5..4886bb2 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -24,7 +24,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d670198..c92428e 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <drivers/intel/gma/i915_reg.h> #include "chip.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 62e28aa..76ab893 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -25,7 +25,6 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <kconfig.h> #include <commonlib/helpers.h> #include "drivers/intel/gma/i915_reg.h" diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index c99f10e..333b28d 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -15,7 +15,6 @@ */ #include <arch/io.h> -#include <config.h> #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index c0cb1a9..2712a5b 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <kconfig.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h index 8b1fe65..b77dffe 100644 --- a/src/vendorcode/amd/pi/00730F01/Porting.h +++ b/src/vendorcode/amd/pi/00730F01/Porting.h @@ -278,7 +278,6 @@ #include "gcc-intrin.h" #include <assert.h> -#include <config.h> #include <console/console.h> #include <commonlib/loglevel.h>

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Patch set updated for coreboot: PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access
by Kyösti Mälkki 30 Nov '16

30 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17546 -gerrit commit cccf1864342f52d54c2a6abb94e6e17324c42861 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 20:39:56 2016 +0200 PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access Some PCI-e capability registers are located starting from 0x100, these are not accessible using the conventional PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO was selected. Thus any feature that calls pciexp_find_extended_cap() depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO being enabled on the platform. In theory there can be system without MMCONF_SUPPORT, but with complete PCI Express configuration space available using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF operations here, but rely on the default PCI access method to be able to access all of the configuration space. While at it, convert to IS_ENABLED() everywhere in the source and organize Kconfig file better. With this change, AGESA and binaryPI platforms change to PCI_CFG_EXT_IO method here until MMCONF_SUPPORT_DEFAULT is activated for them. Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 33 +++++++++++++++++---------------- src/device/pciexp_device.c | 42 ++++++++++++++---------------------------- 2 files changed, 31 insertions(+), 44 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index dd31cba..fb0aaba 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -227,11 +227,6 @@ config PCIX_PLUGIN_SUPPORT depends on PCI default y -config PCIEXP_PLUGIN_SUPPORT - bool - depends on PCI - default y - config CARDBUS_PLUGIN_SUPPORT bool depends on PCI @@ -242,10 +237,16 @@ config AZALIA_PLUGIN_SUPPORT depends on PCI default n +config PCIEXP_PLUGIN_SUPPORT + bool + depends on PCI + default y + +if PCIEXP_PLUGIN_SUPPORT + config PCIEXP_COMMON_CLOCK prompt "Enable PCIe Common Clock" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Common Clock on PCIe links. @@ -253,7 +254,6 @@ config PCIEXP_COMMON_CLOCK config PCIEXP_ASPM prompt "Enable PCIe ASPM" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable ASPM on PCIe links. @@ -261,11 +261,20 @@ config PCIEXP_ASPM config PCIEXP_CLK_PM prompt "Enable PCIe Clock Power Management" bool - depends on PCIEXP_PLUGIN_SUPPORT default n help Detect and enable Clock Power Management on PCIe. +config PCIEXP_L1_SUB_STATE + prompt "Enable PCIe ASPM L1 SubState" + bool + depends on (MMCONF_SUPPORT_DEFAULT || PCI_IO_CFG_EXT) + default n + help + Detect and enable ASPM on PCIe links. + +endif # PCIEXP_PLUGIN_SUPPORT + config EARLY_PCI_BRIDGE bool "Early PCI bridge" depends on PCI @@ -278,14 +287,6 @@ config EARLY_PCI_BRIDGE This option enables static configuration for a single pre-defined PCI bridge function on bus 0. -config PCIEXP_L1_SUB_STATE - prompt "Enable PCIe ASPM L1 SubState" - bool - depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT - default n - help - Detect and enable ASPM on PCIe links. - if EARLY_PCI_BRIDGE config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index d14ba02..7228249 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pciexp.h> -#if IS_ENABLED(CONFIG_MMCONF_SUPPORT) unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) { unsigned int this_cap_offset, next_cap_offset; @@ -29,10 +28,10 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) this_cap_offset = PCIE_EXT_CAP_OFFSET; do { - this_cap = pci_mmio_read_config32(dev, this_cap_offset); + this_cap = pci_read_config32(dev, this_cap_offset); next_cap_offset = this_cap >> 20; this_cap &= 0xffff; - cafe = pci_mmio_read_config32(dev, this_cap_offset + 4); + cafe = pci_read_config32(dev, this_cap_offset + 4); cafe &= 0xffff; if (this_cap == cap) return this_cap_offset; @@ -44,9 +43,7 @@ unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap) return 0; } -#endif -#if CONFIG_PCIEXP_COMMON_CLOCK /* * Re-train a PCIe link */ @@ -109,9 +106,7 @@ static void pciexp_enable_common_clock(device_t root, unsigned root_cap, pciexp_retrain_link(root, root_cap); } } -#endif /* CONFIG_PCIEXP_COMMON_CLOCK */ -#if CONFIG_PCIEXP_CLK_PM static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) { /* check if per port clk req is supported in device */ @@ -126,17 +121,15 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) lnkctl = lnkctl | PCI_EXP_EN_CLK_PM; pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -#endif /* CONFIG_PCIEXP_CLK_PM */ -#if IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE) && IS_ENABLED(CONFIG_MMCONF_SUPPORT) static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) { u32 reg32; - reg32 = pci_mmio_read_config32(dev, reg); + reg32 = pci_read_config32(dev, reg); reg32 &= mask; reg32 |= or; - pci_mmio_write_config32(dev, reg, reg32); + pci_write_config32(dev, reg, reg32); } static void pciexp_config_max_latency(device_t root, device_t dev) @@ -170,7 +163,7 @@ static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, unsigned int power_on_scale = (*data >> 16) & 0x3; unsigned int power_on_value = (*data >> 19) & 0x1f; - unsigned int endp_data = pci_mmio_read_config32(dev, endp_cap + 4); + unsigned int endp_data = pci_read_config32(dev, endp_cap + 4); unsigned int endp_L1SubStateSupport = endp_data & 0xf; unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff; unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3; @@ -200,7 +193,7 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, { device_t dev_t; unsigned char L1_ss_ok; - unsigned int rp_L1_support = pci_mmio_read_config32(root, root_cap + 4); + unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4); unsigned int L1SubStateSupport; unsigned int comm_mode_rst_time; unsigned int power_on_scale; @@ -282,9 +275,7 @@ static void pciexp_config_L1_sub_state(device_t root, device_t dev) pciexp_L1_substate_commit(root, dev, root_cap, end_cap); } -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ -#if CONFIG_PCIEXP_ASPM /* * Determine the ASPM L0s or L1 exit latency for a link * by checking both root port and endpoint and returning @@ -371,7 +362,6 @@ static void pciexp_enable_aspm(device_t root, unsigned root_cap, printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]); } -#endif /* CONFIG_PCIEXP_ASPM */ static void pciexp_tune_dev(device_t dev) { @@ -386,25 +376,21 @@ static void pciexp_tune_dev(device_t dev) if (!root_cap) return; -#if CONFIG_PCIEXP_COMMON_CLOCK /* Check for and enable Common Clock */ - pciexp_enable_common_clock(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); -#if CONFIG_PCIEXP_CLK_PM /* Check if per port CLK req is supported by endpoint*/ - pciexp_enable_clock_power_pm(dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM)) + pciexp_enable_clock_power_pm(dev, cap); -#if CONFIG_PCIEXP_L1_SUB_STATE /* Enable L1 Sub-State when both root port and endpoint support */ - pciexp_config_L1_sub_state(root, dev); -#endif /* CONFIG_PCIEXP_L1_SUB_STATE */ + if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE)) + pciexp_config_L1_sub_state(root, dev); -#if CONFIG_PCIEXP_ASPM /* Check for and enable ASPM */ - pciexp_enable_aspm(root, root_cap, dev, cap); -#endif + if (IS_ENABLED(CONFIG_PCIEXP_ASPM)) + pciexp_enable_aspm(root, root_cap, dev, cap); } void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,

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coreboot-gerrit November 2016