coreboot-gerrit November 2016

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Patch set updated for coreboot: rockchip/rk3399: display: Update edp initialization retry
by Martin Roth 29 Nov '16

29 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17642 -gerrit commit 4b58a76950ae81ef4f6450747d409e9a74ef6d93 Author: Martin Roth <martinroth(a)google.com> Date: Tue Nov 29 10:50:52 2016 -0700 rockchip/rk3399: display: Update edp initialization retry Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails) cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Reduce the jumping around via goto statements - Break the retry code out into a separate function that also prints the error messages. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/rockchip/rk3399/display.c | 44 +++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 4261b26..0e4f2be 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,6 +36,17 @@ #include "chip.h" +static void reset_edp(void) +{ + /* rst edp */ + write32(&cru_ptr->softrst_con[17], + RK_SETBITS(1 << 12 | 1 << 13)); + udelay(1); + write32(&cru_ptr->softrst_con[17], + RK_CLRBITS(1 << 12 | 1 << 13)); + printk(BIOS_WARNING, "Retrying epd initialization.\n"); +} + void rk_display_init(device_t dev) { struct edid edid; @@ -65,14 +76,17 @@ void rk_display_init(device_t dev) write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); retry_edp: - rk_edp_init(); - if (rk_edp_get_edid(&edid) == 0) { - detected_mode = VOP_MODE_EDP; - break; + while (retry_count++ < 3) { + rk_edp_init(); + if (rk_edp_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_EDP; + break; + } + reset_edp(); } - goto edp_error; + printk(BIOS_WARNING, "Warning: epd initialization failed.\n"); + return; - /* fall thru */ case VOP_MODE_HDMI: printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n"); return; @@ -100,24 +114,14 @@ retry_edp: case VOP_MODE_EDP: default: /* will enable edp in depthcharge */ - if (rk_edp_prepare()) - goto edp_error; + if (rk_edp_prepare()) { + reset_edp(); + goto retry_edp; /* Rerun entire init sequence */ + } mainboard_power_on_backlight(); break; } set_vbe_mode_info_valid(&edid, (uintptr_t)0); return; - -edp_error: - if (retry_count++ < 3) { - /* rst edp */ - write32(&cru_ptr->softrst_con[17], - RK_SETBITS(1 << 12 | 1 << 13)); - udelay(1); - write32(&cru_ptr->softrst_con[17], - RK_CLRBITS(1 << 12 | 1 << 13)); - goto retry_edp; - } - printk(BIOS_WARNING, "epd initial error\n"); }

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Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
by Naresh Solanki 29 Nov '16

29 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435 -gerrit commit f79bb6e9606448951bc13c935bb62d1d35451d04 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 15 19:35:33 2016 +0530 mb/intel/kblrvp: Use common lib spd_bin to get spd Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/romstage.c | 21 +++++-- src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 ----- src/mainboard/intel/kblrvp/spd/spd.c | 94 ----------------------------- src/mainboard/intel/kblrvp/spd/spd.h | 18 +----- src/mainboard/intel/kblrvp/spd/spd_util.c | 34 ----------- 6 files changed, 19 insertions(+), 163 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 446266d..e53c446 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index d4fd113..bc39a80 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -23,20 +23,33 @@ #include <soc/gpio.h> #include "spd/spd.h" #include <string.h> +#include <spd_bin.h> +#include "board_id.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; + struct region_device spd_rdev; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + /* RVP3 SPD */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { + die("spd.bin not found\n"); + } + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 83f4831..0c864fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100 SPD_SOURCES += empty # 5b101 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB SPD_SOURCES += empty # 7b111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c deleted file mode 100644 index 1abee81..0000000 --- a/src/mainboard/intel/kblrvp/spd/spd.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - case SPD_DRAM_LPDDR3_INTEL: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index a9f8645..3ef2dd8 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -15,25 +15,11 @@ */ #ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #include <gpio.h> #include "../gpio.h" -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0B -#define SPD_DRAM_LPDDR3 0x0F -#define SPD_DRAM_LPDDR3_INTEL 0xF1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #define RCOMP_TARGET_PARAMS 0x5 @@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -uintptr_t mainboard_get_spd_data(void); -int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9ffc8ee..181af9f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - int spd_index, spd_span; - size_t spd_file_len; - - spd_index = (get_board_id() >> 5) & 0xF; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - spd_span = spd_index * SPD_LEN; - return (uintptr_t)(spd_file + spd_span); -} - -int mainboard_has_dual_channel_mem(void) -{ - return 1; -}

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Patch set updated for coreboot: lib: Add library to handle SPD data in CBFS or DIMM
by Naresh Solanki 29 Nov '16

29 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17434 -gerrit commit d839617b0ede2a23301240f70768a589f6cb9cea Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Oct 26 19:43:14 2016 +0530 lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/Kconfig | 25 ++++++++ src/include/spd_bin.h | 57 +++++++++++++++++ src/lib/Makefile.inc | 18 ++++++ src/lib/spd_bin.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 268 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index be38af1..92817a0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. +config GENERIC_SPD_BIN + bool + default n + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 2 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + config BOARD_ID_AUTO bool default n diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h new file mode 100644 index 0000000..a0c1bbd --- /dev/null +++ b/src/include/spd_bin.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_BIN_H +#define SPD_BIN_H + +#include <arch/early_variables.h> +#include <stdint.h> +#include <commonlib/region.h> + +#define SPD_PAGE_LEN 256 +#define SPD_PAGE_LEN_DDR4 512 +#define SPD_PAGE_0 (0x6C >> 1) +#define SPD_PAGE_1 (0x6E >> 1) +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0B +#define SPD_DRAM_LPDDR3_INTEL 0xF1 +#define SPD_DRAM_LPDDR3_JEDEC 0x0F +#define SPD_DRAM_DDR4 0x0C +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_SPD_PART_OFF 128 +#define DDR3_SPD_PART_LEN 18 +#define LPDDR3_SPD_PART_OFF 128 +#define LPDDR3_SPD_PART_LEN 18 +#define DDR4_SPD_PART_OFF 329 +#define DDR4_SPD_PART_LEN 20 +#define LPDDR4_SPD_PART_OFF 329 +#define LPDDR4_SPD_PART_LEN 20 + +struct spd_block { + u8 *spd_array[CONFIG_DIMM_MAX]; + /* Length of each dimm */ + u16 len; +}; + +void print_spd_info(uint8_t spd[]); +/* Return 0 on success & -1 on failure */ +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); +void dump_spd_info(struct spd_block *blk); +void get_spd_smbus(struct spd_block *blk); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 36591ad..2fb63d0 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -269,3 +269,21 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ + +romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c + +LIB_SPD_BIN = $(obj)/spd.bin + +LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(LIB_SPD_BIN): $(LIB_SPD_DEPS) + for f in $(LIB_SPD_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +spd.bin-file := $(LIB_SPD_BIN) +spd.bin-type := spd diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c new file mode 100644 index 0000000..343d48a --- /dev/null +++ b/src/lib/spd_bin.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <spd_bin.h> +#include <string.h> +#include <device/early_smbus.h> + +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; + +void dump_spd_info(struct spd_block *blk) +{ + u8 i; + + for (i = 0; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { + printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); + print_spd_info(blk->spd_array[i]); + } +} + +void print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; + const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + printk(BIOS_INFO, "LPDDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], + LPDDR3_SPD_PART_LEN); + spd_name[LPDDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_DDR4: + printk(BIOS_INFO, "DDR4\n"); + memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); + spd_name[DDR4_SPD_PART_LEN] = 0; + ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + devw = spd_devw[spd[12] & 7]; + busw = spd_busw[spd[13] & 7]; + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void update_spd_len(struct spd_block *blk) +{ + u8 i, j = 0; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL) + j |= blk->spd_array[i][SPD_DRAM_TYPE]; + + /* If spd used is DDR4, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; +} + +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) +{ + struct cbfsf fh; + + uint32_t cbfs_type = CBFS_TYPE_SPD; + + cbfs_boot_locate(&fh, "spd.bin", &cbfs_type); + cbfs_file_data(spd_rdev, &fh); + return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, + CONFIG_DIMM_SPD_SIZE); +} + +static void get_spd(u8 *spd, u8 addr) +{ + u16 i; + /* Assuming addr is 8 bit address, make it 7 bit */ + addr = addr >> 1; + if (smbus_read_byte(0, addr, 0) == 0xff) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", + addr << 1); + /* Make sure spd is zeroed if dimm doesn't exist. */ + memset(spd, 0, CONFIG_DIMM_SPD_SIZE); + return; + } + + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i] = smbus_read_byte(0, addr, i); + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) { + /* Switch to page 1 */ + smbus_write_byte(0, SPD_PAGE_1, 0, 0); + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i); + /* Restore to page 0 */ + smbus_write_byte(0, SPD_PAGE_0, 0, 0); + } +} + +void get_spd_smbus(struct spd_block *blk) +{ + u8 i, j; + unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); + + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, + 0xA0 + (i << 1)); + blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + } + + for (j = i; j < CONFIG_DIMM_MAX; j++) + blk->spd_array[j] = NULL; + + update_spd_len(blk); +}

1 0

Patch set updated for coreboot: lib: Add library to handle SPD data in CBFS or DIMM
by Naresh Solanki 29 Nov '16

29 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17434 -gerrit commit ac3dc9f9a04be60ce1d97ceb5e9532433d3da504 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Wed Oct 26 19:43:14 2016 +0530 lib: Add library to handle SPD data in CBFS or DIMM Add library to: 1. add spd.bin in cbfs, generated from mainboard/spd/*.spd.hex files. 2. runtime get spd data with spd index as input. 3. fetch spd over smbus using early smbus functions. Change-Id: I44fe1cdb883dd1037484d4bb5c87d2d4f9862bf8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/Kconfig | 25 ++++++++ src/include/spd_bin.h | 56 +++++++++++++++++ src/lib/Makefile.inc | 18 ++++++ src/lib/spd_bin.c | 168 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 267 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index be38af1..92817a0 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -316,6 +316,31 @@ config GENERIC_GPIO_LIB implies configurability usually found on SoCs, particularly the ability to control internal pull resistors. +config GENERIC_SPD_BIN + bool + default n + help + If enabled, add support for adding spd.hex files in cbfs as spd.bin + and locating it runtime to load SPD. Additionally provide provision to + fetch SPD over SMBus. + +config DIMM_MAX + int + default 2 + depends on GENERIC_SPD_BIN + help + Total number of memory DIMM slots available on motherboard. + It is multiplication of number of channel to number of DIMMs per + channel + +config DIMM_SPD_SIZE + int + default 256 + depends on GENERIC_SPD_BIN + help + Total SPD size that will be used for DIMM. + Ex: DDR3 256, DDR4 512. + config BOARD_ID_AUTO bool default n diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h new file mode 100644 index 0000000..3c9b61f --- /dev/null +++ b/src/include/spd_bin.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_BIN_H +#define SPD_BIN_H + +#include <arch/early_variables.h> +#include <stdint.h> +#include <commonlib/region.h> + +#define SPD_PAGE_LEN 256 +#define SPD_PAGE_LEN_DDR4 512 +#define SPD_PAGE_0 (0x6C >> 1) +#define SPD_PAGE_1 (0x6E >> 1) +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0B +#define SPD_DRAM_LPDDR3_INTEL 0xF1 +#define SPD_DRAM_LPDDR3_JEDEC 0x0F +#define SPD_DRAM_DDR4 0x0C +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_SPD_PART_OFF 128 +#define DDR3_SPD_PART_LEN 18 +#define LPDDR3_SPD_PART_OFF 128 +#define LPDDR3_SPD_PART_LEN 18 +#define DDR4_SPD_PART_OFF 329 +#define DDR4_SPD_PART_LEN 20 +#define LPDDR4_SPD_PART_OFF 329 +#define LPDDR4_SPD_PART_LEN 20 + +struct spd_block { + u8 *spd_array[CONFIG_DIMM_MAX]; + /* Length of each dimm */ + u16 len; +}; + +void print_spd_info(uint8_t spd[]); +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); +void dump_spd_info(struct spd_block *blk); +void get_spd_smbus(struct spd_block *blk); + +#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 36591ad..681ba11 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -269,3 +269,21 @@ $(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) $(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) $(RMODTOOL) -i $< -o $@ + +romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c + +SPD_BIN = $(obj)/spd.bin + +SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $(SPD_DEPS); \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c new file mode 100644 index 0000000..bf7141b --- /dev/null +++ b/src/lib/spd_bin.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <spd_bin.h> +#include <string.h> +#include <device/early_smbus.h> + +static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; + +void dump_spd_info(struct spd_block *blk) +{ + u8 i; + + for (i = 0; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { + printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); + print_spd_info(blk->spd_array[i]); + } +} + +void print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; + const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); + spd_name[DDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_LPDDR3_INTEL: + case SPD_DRAM_LPDDR3_JEDEC: + printk(BIOS_INFO, "LPDDR3\n"); + /* Module Part Number */ + memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], + LPDDR3_SPD_PART_LEN); + spd_name[LPDDR3_SPD_PART_LEN] = 0; + break; + case SPD_DRAM_DDR4: + printk(BIOS_INFO, "DDR4\n"); + memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); + spd_name[DDR4_SPD_PART_LEN] = 0; + ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + devw = spd_devw[spd[12] & 7]; + busw = spd_busw[spd[13] & 7]; + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void update_spd_len(struct spd_block *blk) +{ + u8 i, j = 0; + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) + if (blk->spd_array[i] != NULL) + j |= blk->spd_array[i][SPD_DRAM_TYPE]; + + /* If spd used is DDR4, then its length is 512 byte. */ + if (j == SPD_DRAM_DDR4) + blk->len = SPD_PAGE_LEN_DDR4; + else + blk->len = SPD_PAGE_LEN; +} + +int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) +{ + struct cbfsf fh; + + uint32_t cbfs_type = CBFS_TYPE_SPD; + + cbfs_boot_locate(&fh, "spd.bin", &cbfs_type); + + return rdev_chain(spd_rdev, &fh.data, spd_index * CONFIG_DIMM_SPD_SIZE, + CONFIG_DIMM_SPD_SIZE); +} + +static void get_spd(u8 *spd, u8 addr) +{ + u16 i; + /* Assuming addr is 8 bit address, make it 7 bit */ + addr = addr >> 1; + if (smbus_read_byte(0, addr, 0) == 0xff) { + printk(BIOS_INFO, "No memory dimm at address %02X\n", + addr << 1); + /* Make sure spd is zeroed if dimm doesn't exist. */ + memset(spd, 0, CONFIG_DIMM_SPD_SIZE); + return; + } + + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i] = smbus_read_byte(0, addr, i); + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) { + /* Switch to page 1 */ + smbus_write_byte(0, SPD_PAGE_1, 0, 0); + for (i = 0; i < SPD_PAGE_LEN; i++) + spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i); + /* Restore to page 0 */ + smbus_write_byte(0, SPD_PAGE_0, 0, 0); + } +} + +void get_spd_smbus(struct spd_block *blk) +{ + u8 i, j; + unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); + + for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { + get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, + 0xA0 + (i << 1)); + blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + } + + for (j = i; j < CONFIG_DIMM_MAX; j++) + blk->spd_array[j] = NULL; + + update_spd_len(blk); +}

1 0

Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
by Naresh Solanki 29 Nov '16

29 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435 -gerrit commit 56cd64fc0a7560508f829119982c9fa900ddb3d4 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 15 19:35:33 2016 +0530 mb/intel/kblrvp: Use common lib spd_bin to get spd Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/romstage.c | 21 +++++-- src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 ----- src/mainboard/intel/kblrvp/spd/spd.c | 94 ----------------------------- src/mainboard/intel/kblrvp/spd/spd.h | 18 +----- src/mainboard/intel/kblrvp/spd/spd_util.c | 34 ----------- 6 files changed, 19 insertions(+), 163 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 446266d..e53c446 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index d4fd113..bc39a80 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -23,20 +23,33 @@ #include <soc/gpio.h> #include "spd/spd.h" #include <string.h> +#include <spd_bin.h> +#include "board_id.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; + struct region_device spd_rdev; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + /* RVP3 SPD */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { + die("spd.bin not found\n"); + } + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 83f4831..0c864fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100 SPD_SOURCES += empty # 5b101 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB SPD_SOURCES += empty # 7b111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c deleted file mode 100644 index 1abee81..0000000 --- a/src/mainboard/intel/kblrvp/spd/spd.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - case SPD_DRAM_LPDDR3_INTEL: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index a9f8645..3ef2dd8 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -15,25 +15,11 @@ */ #ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #include <gpio.h> #include "../gpio.h" -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0B -#define SPD_DRAM_LPDDR3 0x0F -#define SPD_DRAM_LPDDR3_INTEL 0xF1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #define RCOMP_TARGET_PARAMS 0x5 @@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -uintptr_t mainboard_get_spd_data(void); -int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9ffc8ee..181af9f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - int spd_index, spd_span; - size_t spd_file_len; - - spd_index = (get_board_id() >> 5) & 0xF; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - spd_span = spd_index * SPD_LEN; - return (uintptr_t)(spd_file + spd_span); -} - -int mainboard_has_dual_channel_mem(void) -{ - return 1; -}

1 0

Patch set updated for coreboot: util/lint: Add check for symbolic links in the coreboot tree
by Martin Roth 29 Nov '16

29 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17633 -gerrit commit 309d4f851635848d89c9636ffecd0c32a82a59e8 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 28 13:16:24 2016 -0700 util/lint: Add check for symbolic links in the coreboot tree Because of the varied environments that coreboot is built under, we don't want to have symbolic links in the tree. Change-Id: I4cf9d95a437626cb52e3032a5e6cba83320a334b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-018-symlinks | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/util/lint/lint-stable-018-symlinks b/util/lint/lint-stable-018-symlinks new file mode 100755 index 0000000..7865f55 --- /dev/null +++ b/util/lint/lint-stable-018-symlinks @@ -0,0 +1,33 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Report any symbolic links + +LC_ALL=C export LC_ALL + +EXCLUDED_DIRS='^3rdparty\|^site-local' + +# If the code is in a git repo, only print files that are checked in +if [ -n "$(command -v git)" ] && [ -d .git ]; then + git ls-tree -r HEAD | \ + grep ^120000 | \ + cut -f2 | \ + grep -v "$EXCLUDED_DIRS" +else + # If the code isn't in a git repo, print everything + find . -type l | \ + sed 's|\.\/||' | \ + grep -v "$EXCLUDED_DIRS" +fi +

1 0

Patch set updated for coreboot: util/lint: Add check for symbolic links in the coreboot tree
by Martin Roth 29 Nov '16

29 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17633 -gerrit commit eb737c6e91e7834ae1d3c833e1e4cad616152ed3 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 28 13:16:24 2016 -0700 util/lint: Add check for symbolic links in the coreboot tree Because of the varied environments that coreboot is built under, we don't want to have symbolic links in the tree. Change-Id: I4cf9d95a437626cb52e3032a5e6cba83320a334b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-018-symlinks | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/util/lint/lint-stable-018-symlinks b/util/lint/lint-stable-018-symlinks new file mode 100755 index 0000000..78a97db --- /dev/null +++ b/util/lint/lint-stable-018-symlinks @@ -0,0 +1,33 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Report any symbolic links + +LC_ALL=C export LC_ALL + +EXCLUDED_DIRS='^3rdparty\|^site-local' + +# If the code is in a git repo, only print files that are checked in +if [ -n "$(command -v git)" ] && [ -d .git ]; then + git ls-tree -r HEAD | \ + grep ^120000 | \ + cut -f1 | \ + grep -v "$EXCLUDED_DIRS" +else + # If the code isn't in a git repo, print everything + find . -type l | \ + sed 's|\.\/||' | \ + grep -v "$EXCLUDED_DIRS" +fi +

1 0

Patch set updated for coreboot: mainboard/intel/kblrvp: Revert back USB OC pin programming
by Barnali Sarkar 29 Nov '16

29 Nov '16

Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17635 -gerrit commit 8cd0e651f6404b98ceeb786628ae4b4ad8c87fbc Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Tue Nov 29 12:05:28 2016 +0530 mainboard/intel/kblrvp: Revert back USB OC pin programming With commit 2c3054c1(soc/intel/skylake: Add USB Port Over Current (OC) Pin programming) USB OC pin programming is already initiated from devicetree.cb, hence remove it from ramstage.c. BUG=none BRANCH=none TEST=Built and booted KBLRVP from USB device Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- src/mainboard/intel/kblrvp/ramstage.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index d33c967..bcd72bc 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -21,21 +21,10 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { - size_t i; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Set proper OC for various USB ports*/ - u8 usb2_oc[] = {0x0, 0x2, 0x8, 0x8, 0x2, 0x8, 0x8, 0x8, 0x1, 0x8}; - u8 usb3_oc[] = {0x0, 0x8, 0x8, 0x1, 0x8, 0x8}; - - for (i = 0; i < ARRAY_SIZE(usb2_oc); i++) - params->Usb2OverCurrentPin[i] = usb2_oc[i]; - - for (i = 0; i < ARRAY_SIZE(usb3_oc); i++) - params->Usb3OverCurrentPin[i] = usb3_oc[i]; } static void ioexpander_init(void *unused)

1 0

Patch set updated for coreboot: rockchip/rk3399: display: Update edp initialization retry
by Martin Roth 29 Nov '16

29 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17642 -gerrit commit cd4b55bb0b5a54146b5acc9afe79368367c7503f Author: Martin Roth <martinroth(a)google.com> Date: Tue Nov 29 10:50:52 2016 -0700 rockchip/rk3399: display: Update edp initialization retry Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Get rid of the gotos that jump to the retry code from two separate locations in the switch statement, then return to just one. - Break the retry code out into a separate function that also prints the error messages. - Create a #define for the Max number of retries, since it's used in multiple locations. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/rockchip/rk3399/display.c | 56 ++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 4261b26..5217906 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,6 +36,25 @@ #include "chip.h" +#define MAX_EDP_RETRIES 3 + +static int reset_edp(int retry_count) +{ + if (retry_count == MAX_EDP_RETRIES) { + printk(BIOS_WARNING, "Warning: epd initialization failed.\n"); + return 1; + } + + /* rst edp */ + write32(&cru_ptr->softrst_con[17], + RK_SETBITS(1 << 12 | 1 << 13)); + udelay(1); + write32(&cru_ptr->softrst_con[17], + RK_CLRBITS(1 << 12 | 1 << 13)); + printk(BIOS_WARNING, "Retrying epd initialization.\n"); + return 0; +} + void rk_display_init(device_t dev) { struct edid edid; @@ -64,15 +83,17 @@ void rk_display_init(device_t dev) */ write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); -retry_edp: - rk_edp_init(); - if (rk_edp_get_edid(&edid) == 0) { - detected_mode = VOP_MODE_EDP; - break; + while (retry_count++ < MAX_EDP_RETRIES) { + rk_edp_init(); + if (rk_edp_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_EDP; + break; + } + if (reset_edp(retry_count)) + return; } - goto edp_error; + return; - /* fall thru */ case VOP_MODE_HDMI: printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n"); return; @@ -100,24 +121,15 @@ retry_edp: case VOP_MODE_EDP: default: /* will enable edp in depthcharge */ - if (rk_edp_prepare()) - goto edp_error; + while (retry_count++ < MAX_EDP_RETRIES) { + if (rk_edp_prepare() == 0) + break; + if (reset_edp(retry_count)) + return; + } mainboard_power_on_backlight(); break; } set_vbe_mode_info_valid(&edid, (uintptr_t)0); - return; - -edp_error: - if (retry_count++ < 3) { - /* rst edp */ - write32(&cru_ptr->softrst_con[17], - RK_SETBITS(1 << 12 | 1 << 13)); - udelay(1); - write32(&cru_ptr->softrst_con[17], - RK_CLRBITS(1 << 12 | 1 << 13)); - goto retry_edp; - } - printk(BIOS_WARNING, "epd initial error\n"); }

1 0

New patch to review for coreboot: rockchip/rk3399: display: Update edp initialization retry
by Martin Roth 29 Nov '16

29 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17642 -gerrit commit 375705943d1024ea6a548ee1cfd62ff2ac8ae2a2 Author: Martin Roth <martinroth(a)google.com> Date: Tue Nov 29 10:50:52 2016 -0700 rockchip/rk3399: display: Update edp initialization retry Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Get rid of the gotos that jump to the retry code from two separate locations in the switch statement, then return to just one. - Break the retry code out into a separate function that also prints the error messages. - Create a #define for the Max number of retries, since it's used in multiple locations. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/rockchip/rk3399/display.c | 56 ++++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 4261b26..c2f83cb 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,6 +36,25 @@ #include "chip.h" +#define MAX_EDP_RETRIES 3 + +static int reset_edp(int retry_count) +{ + if (retry_count == MAX_EDP_RETRIES) { + printk(BIOS_WARNING, "Warning: epd initialization failed.\n"); + return 1; + } + + /* rst edp */ + write32(&cru_ptr->softrst_con[17], + RK_SETBITS(1 << 12 | 1 << 13)); + udelay(1); + write32(&cru_ptr->softrst_con[17], + RK_CLRBITS(1 << 12 | 1 << 13)); + printk(BIOS_WARNING, "Retrying epd initialization.\n"); + return 0; +} + void rk_display_init(device_t dev) { struct edid edid; @@ -64,15 +83,17 @@ void rk_display_init(device_t dev) */ write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); -retry_edp: - rk_edp_init(); - if (rk_edp_get_edid(&edid) == 0) { - detected_mode = VOP_MODE_EDP; - break; + while (retry_count++ < MAX_EDP_RETRIES) { + rk_edp_init(); + if (rk_edp_get_edid(&edid) != 0) { + detected_mode = VOP_MODE_EDP; + break; + } + if (reset_edp(retry_count)) + return; } - goto edp_error; + return; - /* fall thru */ case VOP_MODE_HDMI: printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n"); return; @@ -100,24 +121,15 @@ retry_edp: case VOP_MODE_EDP: default: /* will enable edp in depthcharge */ - if (rk_edp_prepare()) - goto edp_error; + while (retry_count++ < MAX_EDP_RETRIES) { + if (rk_edp_prepare() == 0) + break; + if (reset_edp(retry_count)) + return; + } mainboard_power_on_backlight(); break; } set_vbe_mode_info_valid(&edid, (uintptr_t)0); - return; - -edp_error: - if (retry_count++ < 3) { - /* rst edp */ - write32(&cru_ptr->softrst_con[17], - RK_SETBITS(1 << 12 | 1 << 13)); - udelay(1); - write32(&cru_ptr->softrst_con[17], - RK_CLRBITS(1 << 12 | 1 << 13)); - goto retry_edp; - } - printk(BIOS_WARNING, "epd initial error\n"); }

1 0

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coreboot-gerrit November 2016