coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: device/dram/ddr3: add FTB timings
by Nicola Corna 29 Nov '16

29 Nov '16

Nicola Corna (nicola(a)corna.info) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17476 -gerrit commit 15fda93a8eda9de2a52a35f63474a42ee1679016 Author: Nicola Corna <nicola(a)corna.info> Date: Wed Nov 16 08:57:15 2016 +0100 device/dram/ddr3: add FTB timings SPD revision 1.1 introduced FTB timings, an extra set of SPD values that specify a more precise tCKmin, tAAmin, tRCDmin, tRPmin and tRCmin. For backwards compatibility, the MTB is usually rounded up and the FTB part is negative. For this reason some memories were not set up optimally, as the FTB part was ignored and the resulting timing wasn't set to the minimum value. The tests were performed on a Lenovo X220 with two Micron 8KTF51264HZ-1G9E (1866 MHz): reading only the MTB part, Coreboot reported a tCKmin of 1.125 ns, corresponding to a working frequency of 800 MHz; with the additional tCKmin FTB part (-0.054 ns) the new (rounded) value is 1.070 ns, valid for a 933 MHz operation. Some manufacturers (like Micron) seems to expect a small rounding on the timings, so a nearest-value rounding is performed. If this assumption isn't correct, an error up to ~2 ps can be committed, which is low enough to be safely ignored. Change-Id: Ib98f2e70820f207429d04ca6421680109a81f457 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- src/device/dram/ddr3.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index cb5b685..1034852 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -108,9 +108,10 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) { int ret; u16 crc, spd_crc; - u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width; + u8 capacity_shift, bus_width; u8 reg8; u32 mtb; /* medium time base */ + u32 ftb; /* fine time base */ unsigned int val, param; ret = SPD_STATUS_OK; @@ -242,12 +243,6 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width * dimm->ranks) / dimm->width; - /* Fine Timebase (FTB) Dividend/Divisor */ - /* Dividend */ - ftb_dividend = (spd[9] >> 4) & 0x0f; - /* Divisor */ - ftb_divisor = spd[9] & 0x0f; - /* Medium Timebase = * Medium Timebase (MTB) Dividend / * Medium Timebase (MTB) Divisor */ @@ -280,6 +275,29 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Minimum Four Activate Window Delay Time (tFAWmin) */ dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + /* FTB is introduced in SPD revision 1.1 */ + if (spd[1] >= 0x11 && spd[9]) + { + /* Fine timebase (1/256 ps) = + * Fine Timebase (FTB) Dividend / + * Fine Timebase (FTB) Divisor */ + ftb = (((u16) spd[9] & 0xf0) << 4) / (spd[9] & 0x0f); + + /* SPD recommends to round up the MTB part and use a negative + * FTB, so a negative rounding should be always safe */ + + /* SDRAM Minimum Cycle Time (tCKmin) correction */ + dimm->tCK +=(s32)((s8) spd[34] * ftb - 500) / 1000; + /* Minimum CAS Latency Time (tAAmin) correction */ + dimm->tAA += (s32)((s8) spd[35] * ftb - 500) / 1000; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) correction */ + dimm->tRCD += (s32)((s8) spd[36] * ftb - 500) / 1000; + /* Minimum Row Precharge Delay Time (tRPmin) correction */ + dimm->tRP += (s32)((s8) spd[37] * ftb - 500) / 1000; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) corr. */ + dimm->tRC += (s32)((s8) spd[38] * ftb - 500) / 1000; + } + /* SDRAM Optional Features */ reg8 = spd[30]; printram(" Optional features :");

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Patch merged into coreboot/master: nb/intel/i945/gma: Declare count variable outside 'for' loop
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 533a3859c8306772e585a734361bc2f0b242c075 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Nov 27 22:17:44 2016 +0100 nb/intel/i945/gma: Declare count variable outside 'for' loop Building an image for the Lenovo X60 on Debian 8.5 (jessie) with GCC 4.9.2, compilation fails with the error below. ``` $ gcc --version gcc (Debian 4.9.2-10) 4.9.2 […] $ make # lenovo/x60 with native graphics initialization […] CC ramstage/northbridge/intel/i945/gma.o src/northbridge/intel/i945/gma.c: In function 'probe_edid': src/northbridge/intel/i945/gma.c:570:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode for (int i = 0; i < 8; i++) { ^ src/northbridge/intel/i945/gma.c:570:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code Makefile:316: recipe for target 'build/ramstage/northbridge/intel/i945/gma.o' failed make: *** [build/ramstage/northbridge/intel/i945/gma.o] Error 1 ``` Fix this by declaring the count variable outside the 'for' loop. Change-Id: Icf69337ee46c86bafc4e1320fd99f8f8f5155bfe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17623 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/17623 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Support CL > 11
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 2966c9958985ed5a856f9aa6cfdb6dfa45ea8bf9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Nov 19 15:46:42 2016 +0100 nb/intel/sandybridge/raminit: Support CL > 11 The code won't allow anything beyond CL11 due to short CAS Latency mask and a bug in mr0 which had the wrong bit set for CL > 11. Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies from CL 5 to CL 18. Use defines instead of hardcoding min and max CAS latencies. Tested on X220 with two 1866 MHz, CL13 memories Tested-By: Nicola Corna <nicola(a)corna.info> Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/17502 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/17502 for details. -gerrit

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Patch merged into coreboot/master: google/pyro: disable unused devices
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit ca387539b540fb4cbf4f4c2be860d6d8a752b7e5 Author: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Date: Wed Nov 23 18:06:39 2016 +0800 google/pyro: disable unused devices The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17589 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/snappy: Add digitizer device to devicetree
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 5cad9883f22234faa483fa7b6e2771a558cd3c64 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Sun Nov 27 16:31:22 2016 +0800 mainboard/google/snappy: Add digitizer device to devicetree BUG=chrome-os-partner:59034 BRANCH=none TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Reviewed-on: https://review.coreboot.org/17618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17618 for details. -gerrit

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Patch merged into coreboot/master: intel/sch: Switch to MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 02ca68d9fa46a136ed200d8fc9684cfbaebe69a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 17:45:56 2016 +0200 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Forgot to actually "flip the bit" in commit ebc21d1 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Change-Id: Ic095594acb08bae17a6443bc302eb8bfb1ce2083 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17640 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17640 for details. -gerrit

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New patch to review for coreboot: intel/sch: Switch to MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 29 Nov '16

29 Nov '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17640 -gerrit commit 532621c302bfeeaf903890bf92a9aa3751e273f2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 17:45:56 2016 +0200 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Forgot to actually "flip the bit" in commit ebc21d1 intel/sch: Switch to MMCONF_SUPPORT_DEFAULT Change-Id: Ic095594acb08bae17a6443bc302eb8bfb1ce2083 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/sch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index e97d6b3..ed3e003 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -15,7 +15,7 @@ config SOC_INTEL_SCH bool - select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT select INTEL_GMA_ACPI select SOUTHBRIDGE_INTEL_COMMON

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Patch merged into coreboot/master: mainboard/google/reef: Set DPTF CPU passive temperature trip point to 95C
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 5a1a1b5fe699f389fef945c0dbb608aaa0ec91d7 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Thu Nov 24 14:31:54 2016 +0530 mainboard/google/reef: Set DPTF CPU passive temperature trip point to 95C This pach sets the DPTF passive temperature trip point for CPU back to 95 degree celsius from 61 degree celsius as per previous thermal optimizations (https://review.coreboot.org/#/c/16766/). BUG=chrome-os-partner:60038 BRANCH=master TEST=built, booted on Reef and verified the passive trip point funtionality. Change-Id: I83ce69b19a94e4ea8ebedfc06f259579ed6dd5d3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://review.coreboot.org/17598 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17598 for details. -gerrit

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Patch merged into coreboot/master: google/oak: Add DRAM configuration for Samsung K4E8E324EB
by gerrit＠coreboot.org 29 Nov '16

29 Nov '16

the following patch was just integrated into master: commit 1cae20c47fa40be1b61dcad6029fa718c5c59af9 Author: PH Hsu <ph.hsu(a)mediatek.com> Date: Mon Nov 14 16:21:20 2016 +0800 google/oak: Add DRAM configuration for Samsung K4E8E324EB Add the configuration for Samsung K4E8E324EB and assign it to RAM_CODE 5. BUG=chrome-os-partner:58983 TEST=verified on Hana EVT. Change-Id: Iea55eb393b21e37f36d454706531f588101ee651 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 38d34ed0a0b420e1ab300a47b99035153be5b5d0 Original-Change-Id: I28724c1cf5cf12f47911a571c20280ddab4500d5 Original-Signed-off-by: PH Hsu <ph.hsu(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/410926 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17567 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17567 for details. -gerrit

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Patch set updated for coreboot: mb/intel/kblrvp: Use common lib spd_bin to get spd
by Naresh Solanki 29 Nov '16

29 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17435 -gerrit commit 0e209ae2917c8eddba6aede1c010f8e7d417f6cc Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Nov 15 19:35:33 2016 +0530 mb/intel/kblrvp: Use common lib spd_bin to get spd Use common lib spd_bin to get spd. Change-Id: If94413fc36a98f7694f560955bbb80abefe32166 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/Kconfig | 1 + src/mainboard/intel/kblrvp/romstage.c | 19 ++++-- src/mainboard/intel/kblrvp/spd/Makefile.inc | 14 ----- src/mainboard/intel/kblrvp/spd/spd.c | 94 ----------------------------- src/mainboard/intel/kblrvp/spd/spd.h | 18 +----- src/mainboard/intel/kblrvp/spd/spd_util.c | 34 ----------- 6 files changed, 17 insertions(+), 163 deletions(-) diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 446266d..e53c446 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOC_INTEL_SKYLAKE select MAINBOARD_USES_FSP2_0 select MAINBOARD_HAS_CHROMEOS + select GENERIC_SPD_BIN config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index d4fd113..5c6ecde 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -23,20 +23,31 @@ #include <soc/gpio.h> #include "spd/spd.h" #include <string.h> +#include <spd_bin.h> +#include "board_id.h" + void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; + struct region_device spd_rdev; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + /* RVP3 SPD */ mem_cfg->DqPinsInterleaved = 0; - mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); - if (mainboard_has_dual_channel_mem()) - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + + get_spd_cbfs_rdev(&spd_rdev, spd_index); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + mem_cfg->MemorySpdPtr00 = (uintptr_t) rdev_mmap(&spd_rdev, 0, + mem_cfg->MemorySpdDataLen); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc index 83f4831..0c864fe 100644 --- a/src/mainboard/intel/kblrvp/spd/Makefile.inc +++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc @@ -26,17 +26,3 @@ SPD_SOURCES += empty # 4b100 SPD_SOURCES += empty # 5b101 SPD_SOURCES += hynix_dimm_H9CCNNNBJTMLAR # 6b110 Dual Channel 8GB SPD_SOURCES += empty # 7b111 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd ROM data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c deleted file mode 100644 index 1abee81..0000000 --- a/src/mainboard/intel/kblrvp/spd/spd.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <string.h> - -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - case SPD_DRAM_LPDDR3_INTEL: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - uintptr_t spd_data; - spd_data = mainboard_get_spd_data(); - - memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN); - - if (mainboard_has_dual_channel_mem()) - memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index a9f8645..3ef2dd8 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -15,25 +15,11 @@ */ #ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H #include <gpio.h> #include "../gpio.h" -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0B -#define SPD_DRAM_LPDDR3 0x0F -#define SPD_DRAM_LPDDR3_INTEL 0xF1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #define RCOMP_TARGET_PARAMS 0x5 @@ -41,6 +27,4 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); -uintptr_t mainboard_get_spd_data(void); -int mainboard_has_dual_channel_mem(void); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 9ffc8ee..181af9f 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -58,37 +58,3 @@ void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } - -uintptr_t mainboard_get_spd_data(void) -{ - char *spd_file; - int spd_index, spd_span; - size_t spd_file_len; - - spd_index = (get_board_id() >> 5) & 0xF; - printk(BIOS_INFO, "SPD index %d\n", spd_index); - - /* Load SPD data from CBFS */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - spd_span = spd_index * SPD_LEN; - return (uintptr_t)(spd_file + spd_span); -} - -int mainboard_has_dual_channel_mem(void) -{ - return 1; -}

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coreboot-gerrit November 2016